| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/Transforms/InstCombine/ |
| H A D | vector-mul.ll | 7 define <4 x i8> @Zero_i8(<4 x i8> %InVec) {
13 %mul = mul <4 x i8> %InVec, <i8 0, i8 0, i8 0, i8 0>
17 define <4 x i8> @Identity_i8(<4 x i8> %InVec) {
27 define <4 x i8> @AddToSelf_i8(<4 x i8> %InVec) {
60 define <4 x i8> @MulTest1_i8(<4 x i8> %InVec) {
71 define <4 x i8> @MulTest2_i8(<4 x i8> %InVec) {
82 define <4 x i8> @MulTest3_i8(<4 x i8> %InVec) {
93 define <4 x i8> @MulTest4_i8(<4 x i8> %InVec) {
104 define <4 x i16> @Zero_i16(<4 x i16> %InVec) {
201 define <4 x i32> @Zero_i32(<4 x i32> %InVec) {
[all …]
|
| /dports/devel/llvm11/llvm-11.0.1.src/test/Transforms/InstCombine/ |
| H A D | vector-mul.ll | 7 define <4 x i8> @Zero_i8(<4 x i8> %InVec) {
13 %mul = mul <4 x i8> %InVec, <i8 0, i8 0, i8 0, i8 0>
17 define <4 x i8> @Identity_i8(<4 x i8> %InVec) {
27 define <4 x i8> @AddToSelf_i8(<4 x i8> %InVec) {
60 define <4 x i8> @MulTest1_i8(<4 x i8> %InVec) {
71 define <4 x i8> @MulTest2_i8(<4 x i8> %InVec) {
82 define <4 x i8> @MulTest3_i8(<4 x i8> %InVec) {
93 define <4 x i8> @MulTest4_i8(<4 x i8> %InVec) {
104 define <4 x i16> @Zero_i16(<4 x i16> %InVec) {
201 define <4 x i32> @Zero_i32(<4 x i32> %InVec) {
[all …]
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/Transforms/InstCombine/ |
| H A D | vector-mul.ll | 7 define <4 x i8> @Zero_i8(<4 x i8> %InVec) {
13 %mul = mul <4 x i8> %InVec, <i8 0, i8 0, i8 0, i8 0>
17 define <4 x i8> @Identity_i8(<4 x i8> %InVec) {
27 define <4 x i8> @AddToSelf_i8(<4 x i8> %InVec) {
60 define <4 x i8> @MulTest1_i8(<4 x i8> %InVec) {
71 define <4 x i8> @MulTest2_i8(<4 x i8> %InVec) {
82 define <4 x i8> @MulTest3_i8(<4 x i8> %InVec) {
93 define <4 x i8> @MulTest4_i8(<4 x i8> %InVec) {
104 define <4 x i16> @Zero_i16(<4 x i16> %InVec) {
201 define <4 x i32> @Zero_i32(<4 x i32> %InVec) {
[all …]
|
| /dports/devel/llvm90/llvm-9.0.1.src/test/Transforms/InstCombine/ |
| H A D | vector-mul.ll | 7 define <4 x i8> @Zero_i8(<4 x i8> %InVec) {
13 %mul = mul <4 x i8> %InVec, <i8 0, i8 0, i8 0, i8 0>
17 define <4 x i8> @Identity_i8(<4 x i8> %InVec) {
27 define <4 x i8> @AddToSelf_i8(<4 x i8> %InVec) {
60 define <4 x i8> @MulTest1_i8(<4 x i8> %InVec) {
71 define <4 x i8> @MulTest2_i8(<4 x i8> %InVec) {
82 define <4 x i8> @MulTest3_i8(<4 x i8> %InVec) {
93 define <4 x i8> @MulTest4_i8(<4 x i8> %InVec) {
104 define <4 x i16> @Zero_i16(<4 x i16> %InVec) {
201 define <4 x i32> @Zero_i32(<4 x i32> %InVec) {
[all …]
|
| /dports/devel/llvm10/llvm-10.0.1.src/test/Transforms/InstCombine/ |
| H A D | vector-mul.ll | 7 define <4 x i8> @Zero_i8(<4 x i8> %InVec) {
13 %mul = mul <4 x i8> %InVec, <i8 0, i8 0, i8 0, i8 0>
17 define <4 x i8> @Identity_i8(<4 x i8> %InVec) {
27 define <4 x i8> @AddToSelf_i8(<4 x i8> %InVec) {
60 define <4 x i8> @MulTest1_i8(<4 x i8> %InVec) {
71 define <4 x i8> @MulTest2_i8(<4 x i8> %InVec) {
82 define <4 x i8> @MulTest3_i8(<4 x i8> %InVec) {
93 define <4 x i8> @MulTest4_i8(<4 x i8> %InVec) {
104 define <4 x i16> @Zero_i16(<4 x i16> %InVec) {
201 define <4 x i32> @Zero_i32(<4 x i32> %InVec) {
[all …]
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/Transforms/InstCombine/ |
| H A D | vector-mul.ll | 7 define <4 x i8> @Zero_i8(<4 x i8> %InVec) {
13 %mul = mul <4 x i8> %InVec, <i8 0, i8 0, i8 0, i8 0>
17 define <4 x i8> @Identity_i8(<4 x i8> %InVec) {
27 define <4 x i8> @AddToSelf_i8(<4 x i8> %InVec) {
60 define <4 x i8> @MulTest1_i8(<4 x i8> %InVec) {
71 define <4 x i8> @MulTest2_i8(<4 x i8> %InVec) {
82 define <4 x i8> @MulTest3_i8(<4 x i8> %InVec) {
93 define <4 x i8> @MulTest4_i8(<4 x i8> %InVec) {
104 define <4 x i16> @Zero_i16(<4 x i16> %InVec) {
201 define <4 x i32> @Zero_i32(<4 x i32> %InVec) {
[all …]
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/Transforms/InstCombine/ |
| H A D | vector-mul.ll | 7 define <4 x i8> @Zero_i8(<4 x i8> %InVec) {
13 %mul = mul <4 x i8> %InVec, <i8 0, i8 0, i8 0, i8 0>
17 define <4 x i8> @Identity_i8(<4 x i8> %InVec) {
27 define <4 x i8> @AddToSelf_i8(<4 x i8> %InVec) {
60 define <4 x i8> @MulTest1_i8(<4 x i8> %InVec) {
71 define <4 x i8> @MulTest2_i8(<4 x i8> %InVec) {
82 define <4 x i8> @MulTest3_i8(<4 x i8> %InVec) {
93 define <4 x i8> @MulTest4_i8(<4 x i8> %InVec) {
104 define <4 x i16> @Zero_i16(<4 x i16> %InVec) {
201 define <4 x i32> @Zero_i32(<4 x i32> %InVec) {
[all …]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/Transforms/InstCombine/ |
| H A D | vector-mul.ll | 7 define <4 x i8> @Zero_i8(<4 x i8> %InVec) {
13 %mul = mul <4 x i8> %InVec, <i8 0, i8 0, i8 0, i8 0>
17 define <4 x i8> @Identity_i8(<4 x i8> %InVec) {
27 define <4 x i8> @AddToSelf_i8(<4 x i8> %InVec) {
60 define <4 x i8> @MulTest1_i8(<4 x i8> %InVec) {
71 define <4 x i8> @MulTest2_i8(<4 x i8> %InVec) {
82 define <4 x i8> @MulTest3_i8(<4 x i8> %InVec) {
93 define <4 x i8> @MulTest4_i8(<4 x i8> %InVec) {
104 define <4 x i16> @Zero_i16(<4 x i16> %InVec) {
201 define <4 x i32> @Zero_i32(<4 x i32> %InVec) {
[all …]
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/Transforms/InstCombine/ |
| H A D | vector-mul.ll | 7 define <4 x i8> @Zero_i8(<4 x i8> %InVec) {
13 %mul = mul <4 x i8> %InVec, <i8 0, i8 0, i8 0, i8 0>
17 define <4 x i8> @Identity_i8(<4 x i8> %InVec) {
27 define <4 x i8> @AddToSelf_i8(<4 x i8> %InVec) {
60 define <4 x i8> @MulTest1_i8(<4 x i8> %InVec) {
71 define <4 x i8> @MulTest2_i8(<4 x i8> %InVec) {
82 define <4 x i8> @MulTest3_i8(<4 x i8> %InVec) {
93 define <4 x i8> @MulTest4_i8(<4 x i8> %InVec) {
104 define <4 x i16> @Zero_i16(<4 x i16> %InVec) {
201 define <4 x i32> @Zero_i32(<4 x i32> %InVec) {
[all …]
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/Transforms/InstCombine/ |
| H A D | vector-mul.ll | 7 define <4 x i8> @Zero_i8(<4 x i8> %InVec) {
13 %mul = mul <4 x i8> %InVec, <i8 0, i8 0, i8 0, i8 0>
17 define <4 x i8> @Identity_i8(<4 x i8> %InVec) {
27 define <4 x i8> @AddToSelf_i8(<4 x i8> %InVec) {
60 define <4 x i8> @MulTest1_i8(<4 x i8> %InVec) {
71 define <4 x i8> @MulTest2_i8(<4 x i8> %InVec) {
82 define <4 x i8> @MulTest3_i8(<4 x i8> %InVec) {
93 define <4 x i8> @MulTest4_i8(<4 x i8> %InVec) {
104 define <4 x i16> @Zero_i16(<4 x i16> %InVec) {
201 define <4 x i32> @Zero_i32(<4 x i32> %InVec) {
[all …]
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/Transforms/InstCombine/ |
| H A D | vector-mul.ll | 7 define <4 x i8> @Zero_i8(<4 x i8> %InVec) {
13 %mul = mul <4 x i8> %InVec, <i8 0, i8 0, i8 0, i8 0>
17 define <4 x i8> @Identity_i8(<4 x i8> %InVec) {
27 define <4 x i8> @AddToSelf_i8(<4 x i8> %InVec) {
60 define <4 x i8> @MulTest1_i8(<4 x i8> %InVec) {
71 define <4 x i8> @MulTest2_i8(<4 x i8> %InVec) {
82 define <4 x i8> @MulTest3_i8(<4 x i8> %InVec) {
93 define <4 x i8> @MulTest4_i8(<4 x i8> %InVec) {
104 define <4 x i16> @Zero_i16(<4 x i16> %InVec) {
201 define <4 x i32> @Zero_i32(<4 x i32> %InVec) {
[all …]
|
| /dports/devel/llvm80/llvm-8.0.1.src/test/Transforms/InstCombine/ |
| H A D | vector-mul.ll | 7 define <4 x i8> @Zero_i8(<4 x i8> %InVec) {
13 %mul = mul <4 x i8> %InVec, <i8 0, i8 0, i8 0, i8 0>
17 define <4 x i8> @Identity_i8(<4 x i8> %InVec) {
27 define <4 x i8> @AddToSelf_i8(<4 x i8> %InVec) {
60 define <4 x i8> @MulTest1_i8(<4 x i8> %InVec) {
71 define <4 x i8> @MulTest2_i8(<4 x i8> %InVec) {
82 define <4 x i8> @MulTest3_i8(<4 x i8> %InVec) {
93 define <4 x i8> @MulTest4_i8(<4 x i8> %InVec) {
104 define <4 x i16> @Zero_i16(<4 x i16> %InVec) {
201 define <4 x i32> @Zero_i32(<4 x i32> %InVec) {
[all …]
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/test/Transforms/InstCombine/ |
| H A D | vector-mul.ll | 7 define <4 x i8> @Zero_i8(<4 x i8> %InVec) {
13 %mul = mul <4 x i8> %InVec, <i8 0, i8 0, i8 0, i8 0>
17 define <4 x i8> @Identity_i8(<4 x i8> %InVec) {
27 define <4 x i8> @AddToSelf_i8(<4 x i8> %InVec) {
60 define <4 x i8> @MulTest1_i8(<4 x i8> %InVec) {
71 define <4 x i8> @MulTest2_i8(<4 x i8> %InVec) {
82 define <4 x i8> @MulTest3_i8(<4 x i8> %InVec) {
93 define <4 x i8> @MulTest4_i8(<4 x i8> %InVec) {
104 define <4 x i16> @Zero_i16(<4 x i16> %InVec) {
201 define <4 x i32> @Zero_i32(<4 x i32> %InVec) {
[all …]
|
| /dports/devel/llvm70/llvm-7.0.1.src/test/Transforms/InstCombine/ |
| H A D | vector-mul.ll | 7 define <4 x i8> @Zero_i8(<4 x i8> %InVec) {
13 %mul = mul <4 x i8> %InVec, <i8 0, i8 0, i8 0, i8 0>
17 define <4 x i8> @Identity_i8(<4 x i8> %InVec) {
27 define <4 x i8> @AddToSelf_i8(<4 x i8> %InVec) {
60 define <4 x i8> @MulTest1_i8(<4 x i8> %InVec) {
71 define <4 x i8> @MulTest2_i8(<4 x i8> %InVec) {
82 define <4 x i8> @MulTest3_i8(<4 x i8> %InVec) {
93 define <4 x i8> @MulTest4_i8(<4 x i8> %InVec) {
104 define <4 x i16> @Zero_i16(<4 x i16> %InVec) {
201 define <4 x i32> @Zero_i32(<4 x i32> %InVec) {
[all …]
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/Transforms/InstCombine/ |
| H A D | vector-mul.ll | 7 define <4 x i8> @Zero_i8(<4 x i8> %InVec) {
13 %mul = mul <4 x i8> %InVec, <i8 0, i8 0, i8 0, i8 0>
17 define <4 x i8> @Identity_i8(<4 x i8> %InVec) {
27 define <4 x i8> @AddToSelf_i8(<4 x i8> %InVec) {
60 define <4 x i8> @MulTest1_i8(<4 x i8> %InVec) {
71 define <4 x i8> @MulTest2_i8(<4 x i8> %InVec) {
82 define <4 x i8> @MulTest3_i8(<4 x i8> %InVec) {
93 define <4 x i8> @MulTest4_i8(<4 x i8> %InVec) {
104 define <4 x i16> @Zero_i16(<4 x i16> %InVec) {
201 define <4 x i32> @Zero_i32(<4 x i32> %InVec) {
[all …]
|
| /dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/X86/ |
| H A D | sse2-vector-shifts.ll | 6 define <8 x i16> @test_sllw_1(<8 x i16> %InVec) {
15 define <8 x i16> @test_sllw_2(<8 x i16> %InVec) {
25 define <8 x i16> @test_sllw_3(<8 x i16> %InVec) {
35 define <4 x i32> @test_slld_1(<4 x i32> %InVec) {
44 define <4 x i32> @test_slld_2(<4 x i32> %InVec) {
54 define <4 x i32> @test_slld_3(<4 x i32> %InVec) {
69 %shl = shl <2 x i64> %InVec, <i64 0, i64 0>
79 %shl = shl <2 x i64> %InVec, <i64 1, i64 1>
89 %shl = shl <2 x i64> %InVec, <i64 63, i64 63>
218 %shl = lshr <2 x i64> %InVec, <i64 0, i64 0>
[all …]
|
| /dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/X86/ |
| H A D | sse2-vector-shifts.ll | 6 define <8 x i16> @test_sllw_1(<8 x i16> %InVec) {
15 define <8 x i16> @test_sllw_2(<8 x i16> %InVec) {
25 define <8 x i16> @test_sllw_3(<8 x i16> %InVec) {
35 define <4 x i32> @test_slld_1(<4 x i32> %InVec) {
44 define <4 x i32> @test_slld_2(<4 x i32> %InVec) {
54 define <4 x i32> @test_slld_3(<4 x i32> %InVec) {
69 %shl = shl <2 x i64> %InVec, <i64 0, i64 0>
79 %shl = shl <2 x i64> %InVec, <i64 1, i64 1>
89 %shl = shl <2 x i64> %InVec, <i64 63, i64 63>
218 %shl = lshr <2 x i64> %InVec, <i64 0, i64 0>
[all …]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/X86/ |
| H A D | sse2-vector-shifts.ll | 8 define <8 x i16> @test_sllw_1(<8 x i16> %InVec) {
17 define <8 x i16> @test_sllw_2(<8 x i16> %InVec) {
27 define <8 x i16> @test_sllw_3(<8 x i16> %InVec) {
37 define <4 x i32> @test_slld_1(<4 x i32> %InVec) {
46 define <4 x i32> @test_slld_2(<4 x i32> %InVec) {
56 define <4 x i32> @test_slld_3(<4 x i32> %InVec) {
71 %shl = shl <2 x i64> %InVec, <i64 0, i64 0>
81 %shl = shl <2 x i64> %InVec, <i64 1, i64 1>
91 %shl = shl <2 x i64> %InVec, <i64 63, i64 63>
220 %shl = lshr <2 x i64> %InVec, <i64 0, i64 0>
[all …]
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/X86/ |
| H A D | sse2-vector-shifts.ll | 8 define <8 x i16> @test_sllw_1(<8 x i16> %InVec) {
17 define <8 x i16> @test_sllw_2(<8 x i16> %InVec) {
27 define <8 x i16> @test_sllw_3(<8 x i16> %InVec) {
37 define <4 x i32> @test_slld_1(<4 x i32> %InVec) {
46 define <4 x i32> @test_slld_2(<4 x i32> %InVec) {
56 define <4 x i32> @test_slld_3(<4 x i32> %InVec) {
71 %shl = shl <2 x i64> %InVec, <i64 0, i64 0>
81 %shl = shl <2 x i64> %InVec, <i64 1, i64 1>
91 %shl = shl <2 x i64> %InVec, <i64 63, i64 63>
220 %shl = lshr <2 x i64> %InVec, <i64 0, i64 0>
[all …]
|
| /dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/X86/ |
| H A D | sse2-vector-shifts.ll | 8 define <8 x i16> @test_sllw_1(<8 x i16> %InVec) {
17 define <8 x i16> @test_sllw_2(<8 x i16> %InVec) {
27 define <8 x i16> @test_sllw_3(<8 x i16> %InVec) {
37 define <4 x i32> @test_slld_1(<4 x i32> %InVec) {
46 define <4 x i32> @test_slld_2(<4 x i32> %InVec) {
56 define <4 x i32> @test_slld_3(<4 x i32> %InVec) {
71 %shl = shl <2 x i64> %InVec, <i64 0, i64 0>
81 %shl = shl <2 x i64> %InVec, <i64 1, i64 1>
91 %shl = shl <2 x i64> %InVec, <i64 63, i64 63>
220 %shl = lshr <2 x i64> %InVec, <i64 0, i64 0>
[all …]
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/X86/ |
| H A D | sse2-vector-shifts.ll | 8 define <8 x i16> @test_sllw_1(<8 x i16> %InVec) {
17 define <8 x i16> @test_sllw_2(<8 x i16> %InVec) {
27 define <8 x i16> @test_sllw_3(<8 x i16> %InVec) {
37 define <4 x i32> @test_slld_1(<4 x i32> %InVec) {
46 define <4 x i32> @test_slld_2(<4 x i32> %InVec) {
56 define <4 x i32> @test_slld_3(<4 x i32> %InVec) {
71 %shl = shl <2 x i64> %InVec, <i64 0, i64 0>
81 %shl = shl <2 x i64> %InVec, <i64 1, i64 1>
91 %shl = shl <2 x i64> %InVec, <i64 63, i64 63>
220 %shl = lshr <2 x i64> %InVec, <i64 0, i64 0>
[all …]
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/X86/ |
| H A D | sse2-vector-shifts.ll | 8 define <8 x i16> @test_sllw_1(<8 x i16> %InVec) {
17 define <8 x i16> @test_sllw_2(<8 x i16> %InVec) {
27 define <8 x i16> @test_sllw_3(<8 x i16> %InVec) {
37 define <4 x i32> @test_slld_1(<4 x i32> %InVec) {
46 define <4 x i32> @test_slld_2(<4 x i32> %InVec) {
56 define <4 x i32> @test_slld_3(<4 x i32> %InVec) {
71 %shl = shl <2 x i64> %InVec, <i64 0, i64 0>
81 %shl = shl <2 x i64> %InVec, <i64 1, i64 1>
91 %shl = shl <2 x i64> %InVec, <i64 63, i64 63>
220 %shl = lshr <2 x i64> %InVec, <i64 0, i64 0>
[all …]
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/X86/ |
| H A D | sse2-vector-shifts.ll | 8 define <8 x i16> @test_sllw_1(<8 x i16> %InVec) {
17 define <8 x i16> @test_sllw_2(<8 x i16> %InVec) {
27 define <8 x i16> @test_sllw_3(<8 x i16> %InVec) {
37 define <4 x i32> @test_slld_1(<4 x i32> %InVec) {
46 define <4 x i32> @test_slld_2(<4 x i32> %InVec) {
56 define <4 x i32> @test_slld_3(<4 x i32> %InVec) {
71 %shl = shl <2 x i64> %InVec, <i64 0, i64 0>
81 %shl = shl <2 x i64> %InVec, <i64 1, i64 1>
91 %shl = shl <2 x i64> %InVec, <i64 63, i64 63>
220 %shl = lshr <2 x i64> %InVec, <i64 0, i64 0>
[all …]
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/X86/ |
| H A D | sse2-vector-shifts.ll | 8 define <8 x i16> @test_sllw_1(<8 x i16> %InVec) {
17 define <8 x i16> @test_sllw_2(<8 x i16> %InVec) {
27 define <8 x i16> @test_sllw_3(<8 x i16> %InVec) {
37 define <4 x i32> @test_slld_1(<4 x i32> %InVec) {
46 define <4 x i32> @test_slld_2(<4 x i32> %InVec) {
56 define <4 x i32> @test_slld_3(<4 x i32> %InVec) {
71 %shl = shl <2 x i64> %InVec, <i64 0, i64 0>
81 %shl = shl <2 x i64> %InVec, <i64 1, i64 1>
91 %shl = shl <2 x i64> %InVec, <i64 63, i64 63>
220 %shl = lshr <2 x i64> %InVec, <i64 0, i64 0>
[all …]
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| /dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/X86/ |
| H A D | sse2-vector-shifts.ll | 8 define <8 x i16> @test_sllw_1(<8 x i16> %InVec) {
17 define <8 x i16> @test_sllw_2(<8 x i16> %InVec) {
27 define <8 x i16> @test_sllw_3(<8 x i16> %InVec) {
37 define <4 x i32> @test_slld_1(<4 x i32> %InVec) {
46 define <4 x i32> @test_slld_2(<4 x i32> %InVec) {
56 define <4 x i32> @test_slld_3(<4 x i32> %InVec) {
71 %shl = shl <2 x i64> %InVec, <i64 0, i64 0>
81 %shl = shl <2 x i64> %InVec, <i64 1, i64 1>
91 %shl = shl <2 x i64> %InVec, <i64 63, i64 63>
220 %shl = lshr <2 x i64> %InVec, <i64 0, i64 0>
[all …]
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