/dports/devel/avr-gdb/gdb-7.3.1/sim/mips/ |
H A D | sim-main.c | 56 int IorD, in address_translation() argument 65 …sim_io_printf (sd, "AddressTranslation(0x%s,%s,%s,...);\n", pr_addr (vAddr), (IorD ? "isDATA" : "i… in address_translation() 133 int IorD) in load_memory() argument 139 …s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINS… in load_memory() 157 …dotrace (SD, CPU, tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLengt… in load_memory()
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H A D | sim-main.h | 944 …ARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_… 945 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \ argument 946 address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw) 948 …* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD)); 949 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \ argument 950 load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
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/dports/devel/gdb761/gdb-7.6.1/sim/mips/ |
H A D | sim-main.c | 55 int IorD, in address_translation() argument 64 …sim_io_printf (sd, "AddressTranslation(0x%s,%s,%s,...);\n", pr_addr (vAddr), (IorD ? "isDATA" : "i… in address_translation() 132 int IorD) in load_memory() argument 138 …s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINS… in load_memory() 156 …dotrace (SD, CPU, tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLengt… in load_memory()
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H A D | sim-main.h | 943 …ARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_… 944 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \ argument 945 address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw) 947 …* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD)); 948 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \ argument 949 load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
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/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/mips/ |
H A D | sim-main.c | 56 int IorD, in address_translation() argument 65 …sim_io_printf (sd, "AddressTranslation(0x%s,%s,%s,...);\n", pr_addr (vAddr), (IorD ? "isDATA" : "i… in address_translation() 133 int IorD) in load_memory() argument 139 …s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINS… in load_memory() 157 …dotrace (SD, CPU, tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLengt… in load_memory()
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H A D | sim-main.h | 898 …ARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_… 899 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \ argument 900 address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw) 902 …* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD)); 903 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \ argument 904 load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
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/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/mips/ |
H A D | sim-main.c | 56 int IorD, in address_translation() argument 65 …sim_io_printf (sd, "AddressTranslation(0x%s,%s,%s,...);\n", pr_addr (vAddr), (IorD ? "isDATA" : "i… in address_translation() 133 int IorD) in load_memory() argument 139 …s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINS… in load_memory() 157 …dotrace (SD, CPU, tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLengt… in load_memory()
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H A D | sim-main.h | 898 …ARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_… 899 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \ argument 900 address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw) 902 …* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD)); 903 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \ argument 904 load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
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/dports/biology/ncbi-toolkit/ncbi/algo/blast/core/ |
H A D | greedy_align.c | 201 Int4 gap_extend, EGapAlignOpType IorD) in s_GetNextAffineTbackFromIndel() argument 218 if (IorD == eGapAlignIns) in s_GetNextAffineTbackFromIndel() 229 if (IorD == eGapAlignIns) in s_GetNextAffineTbackFromIndel() 257 return IorD; in s_GetNextAffineTbackFromIndel()
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/dports/biology/ncbi-cxx-toolkit/ncbi_cxx--25_2_0/src/algo/blast/core/ |
H A D | greedy_align.c | 201 Int4 gap_extend, EGapAlignOpType IorD) in s_GetNextAffineTbackFromIndel() argument 218 if (IorD == eGapAlignIns) in s_GetNextAffineTbackFromIndel() 229 if (IorD == eGapAlignIns) in s_GetNextAffineTbackFromIndel() 257 return IorD; in s_GetNextAffineTbackFromIndel()
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/dports/biology/ncbi-blast+/ncbi-blast-2.12.0+-src/c++/src/algo/blast/core/ |
H A D | greedy_align.c | 201 Int4 gap_extend, EGapAlignOpType IorD) in s_GetNextAffineTbackFromIndel() argument 218 if (IorD == eGapAlignIns) in s_GetNextAffineTbackFromIndel() 229 if (IorD == eGapAlignIns) in s_GetNextAffineTbackFromIndel() 257 return IorD; in s_GetNextAffineTbackFromIndel()
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/dports/biology/ncbi-toolkit/ncbi/tools/ |
H A D | mbalign.c | 457 Int4 GE_cost, Int4 IorD) in get_last_ID() argument 462 if (IorD == sI) { ndiag = diag -1;} else ndiag = diag+1; in get_last_ID() 464 row = (IorD == sI)? flast_d[(*d)-GE_cost][ndiag].I: flast_d[(*d)-GE_cost][ndiag].D; in get_last_ID() 471 return IorD; in get_last_ID()
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/dports/math/py-heyoka/heyoka.py-0.16.0/doc/notebooks/ |
H A D | tides_spokes.ipynb | 730846 "gLe/7S08e8e3mDh2KJSVQ1QB0R635b2gsh9U9E9uK/tBeW+IorD/uySpQBnQkhRKezM0rYTtq2Dn\\\n",
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