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Searched refs:LD1 (Results 1 – 25 of 932) sorted by relevance

12 3 4 5 6 7 8 9 10 >>...38

/dports/multimedia/opentoonz/opentoonz-1.5.0/thirdparty/openblas/xianyi-OpenBLAS-e6e87a2/
H A D	cpuid_x86.c	`220 LD1.size = 0; LD1.associative = 0; LD1.linesize = 0; LD1.shared = 0; in get_cacheinfo() 304 LD1.size = 8; in get_cacheinfo() 305 LD1.associative = 2; in get_cacheinfo() 310 LD1.associative = 4; in get_cacheinfo() 315 LD1.associative = 4; in get_cacheinfo() 320 LD1.associative = 6; in get_cacheinfo() 325 LD1.associative = 4; in get_cacheinfo() 365 LD1.associative = 8; in get_cacheinfo() 556 LD1.associative = 8; in get_cacheinfo() 560 LD1.size = 8; in get_cacheinfo() [all …]`
/dports/cad/meshlab/meshlab-Meshlab-2020.05/src/plugins_unsupported/external/GotoBLAS2/
H A D	cpuid_x86.c	`203 LD1.size = 0; LD1.associative = 0; LD1.linesize = 0; LD1.shared = 0; in get_cacheinfo() 287 LD1.size = 8; in get_cacheinfo() 288 LD1.associative = 2; in get_cacheinfo() 293 LD1.associative = 4; in get_cacheinfo() 298 LD1.associative = 4; in get_cacheinfo() 303 LD1.associative = 6; in get_cacheinfo() 308 LD1.associative = 4; in get_cacheinfo() 348 LD1.associative = 8; in get_cacheinfo() 539 LD1.associative = 8; in get_cacheinfo() 543 LD1.size = 8; in get_cacheinfo() [all …]`
/dports/math/gotoblas/GotoBLAS2/
H A D	cpuid_x86.c	`220 LD1.size = 0; LD1.associative = 0; LD1.linesize = 0; LD1.shared = 0; in get_cacheinfo() 304 LD1.size = 8; in get_cacheinfo() 305 LD1.associative = 2; in get_cacheinfo() 310 LD1.associative = 4; in get_cacheinfo() 315 LD1.associative = 4; in get_cacheinfo() 320 LD1.associative = 6; in get_cacheinfo() 325 LD1.associative = 4; in get_cacheinfo() 365 LD1.associative = 8; in get_cacheinfo() 556 LD1.associative = 8; in get_cacheinfo() 560 LD1.size = 8; in get_cacheinfo() [all …]`
/dports/science/quantum-espresso/q-e-qe-6.7.0/atomic/examples/paw_examples/
H A D	test	10 LD1=$(cd ../../../bin/; echo `pwd`/ld1.x) 11 test -x $LD1 \|\| 20 $LD1 < gen.in > gen.out \|\| 23 $LD1 < test.in > test.out \|\| 26 $LD1 < spin.in > spin.out \|\| 46 $LD1 < ../input/$input > ${input/.in/.out} \|\|
/dports/math/openblas/OpenBLAS-0.3.18/
H A D	cpuid_x86.c	`389 LD1.size = 0; LD1.associative = 0; LD1.linesize = 0; LD1.shared = 0; in get_cacheinfo() 472 LD1.size = 8; in get_cacheinfo() 473 LD1.associative = 2; in get_cacheinfo() 478 LD1.associative = 4; in get_cacheinfo() 483 LD1.associative = 4; in get_cacheinfo() 488 LD1.associative = 6; in get_cacheinfo() 493 LD1.associative = 4; in get_cacheinfo() 533 LD1.associative = 8; in get_cacheinfo() 724 LD1.associative = 8; in get_cacheinfo() 736 LD1.size = 8; in get_cacheinfo() [all …]`
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/docs/
H A D	BigEndianNEON.rst	52 ``LDR`` and ``LD1`` 66 Big endian vector load using ``LD1``. Note that the lanes retain the correct ordering. 76 …2. The content of a vector register is the same as if it had been loaded with an ``LD1`` instruc… 78 Because ``LD1 == LDR + REV`` and similarly ``LDR == LD1 + REV`` (on a big endian system), we can si… 133 …LD1`` only requires it to be as aligned as the lane size. If we canonicalised on using ``LDR``, we… 143 \| \| ``LDR`` layout \| ``LD1`` layout \| 145 \| Lane ordering \| ``LDR + REV`` \| ``LD1`` \| 147 \| AAPCS \| ``LDR`` \| ``LD1 + REV`` \| 149 \| Alignment for strict mode \| ``LDR`` / ``LD1 + REV`` \| ``LD1`` \| 188 …LD1`` of type ``X`` (converting the in-register representation to the same as if it had been loade… [all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/docs/
H A D	BigEndianNEON.rst	52 ``LDR`` and ``LD1`` 66 Big endian vector load using ``LD1``. Note that the lanes retain the correct ordering. 76 …2. The content of a vector register is the same as if it had been loaded with an ``LD1`` instruc… 78 Because ``LD1 == LDR + REV`` and similarly ``LDR == LD1 + REV`` (on a big endian system), we can si… 133 …LD1`` only requires it to be as aligned as the lane size. If we canonicalised on using ``LDR``, we… 143 \| \| ``LDR`` layout \| ``LD1`` layout \| 145 \| Lane ordering \| ``LDR + REV`` \| ``LD1`` \| 147 \| AAPCS \| ``LDR`` \| ``LD1 + REV`` \| 149 \| Alignment for strict mode \| ``LDR`` / ``LD1 + REV`` \| ``LD1`` \| 188 …LD1`` of type ``X`` (converting the in-register representation to the same as if it had been loade… [all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/docs/
H A D	BigEndianNEON.rst	52 ``LDR`` and ``LD1`` 66 Big endian vector load using ``LD1``. Note that the lanes retain the correct ordering. 76 …2. The content of a vector register is the same as if it had been loaded with an ``LD1`` instruc… 78 Because ``LD1 == LDR + REV`` and similarly ``LDR == LD1 + REV`` (on a big endian system), we can si… 133 …LD1`` only requires it to be as aligned as the lane size. If we canonicalised on using ``LDR``, we… 143 \| \| ``LDR`` layout \| ``LD1`` layout \| 145 \| Lane ordering \| ``LDR + REV`` \| ``LD1`` \| 147 \| AAPCS \| ``LDR`` \| ``LD1 + REV`` \| 149 \| Alignment for strict mode \| ``LDR`` / ``LD1 + REV`` \| ``LD1`` \| 188 …LD1`` of type ``X`` (converting the in-register representation to the same as if it had been loade… [all …]
/dports/devel/llvm10/llvm-10.0.1.src/docs/
H A D	BigEndianNEON.rst	52 ``LDR`` and ``LD1`` 66 Big endian vector load using ``LD1``. Note that the lanes retain the correct ordering. 76 …2. The content of a vector register is the same as if it had been loaded with an ``LD1`` instruc… 78 Because ``LD1 == LDR + REV`` and similarly ``LDR == LD1 + REV`` (on a big endian system), we can si… 133 …LD1`` only requires it to be as aligned as the lane size. If we canonicalised on using ``LDR``, we… 143 \| \| ``LDR`` layout \| ``LD1`` layout \| 145 \| Lane ordering \| ``LDR + REV`` \| ``LD1`` \| 147 \| AAPCS \| ``LDR`` \| ``LD1 + REV`` \| 149 \| Alignment for strict mode \| ``LDR`` / ``LD1 + REV`` \| ``LD1`` \| 188 …LD1`` of type ``X`` (converting the in-register representation to the same as if it had been loade… [all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/docs/
H A D	BigEndianNEON.rst	52 ``LDR`` and ``LD1`` 66 Big endian vector load using ``LD1``. Note that the lanes retain the correct ordering. 76 …2. The content of a vector register is the same as if it had been loaded with an ``LD1`` instruc… 78 Because ``LD1 == LDR + REV`` and similarly ``LDR == LD1 + REV`` (on a big endian system), we can si… 133 …LD1`` only requires it to be as aligned as the lane size. If we canonicalised on using ``LDR``, we… 143 \| \| ``LDR`` layout \| ``LD1`` layout \| 145 \| Lane ordering \| ``LDR + REV`` \| ``LD1`` \| 147 \| AAPCS \| ``LDR`` \| ``LD1 + REV`` \| 149 \| Alignment for strict mode \| ``LDR`` / ``LD1 + REV`` \| ``LD1`` \| 188 …LD1`` of type ``X`` (converting the in-register representation to the same as if it had been loade… [all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/docs/
H A D	BigEndianNEON.rst	52 ``LDR`` and ``LD1`` 66 Big endian vector load using ``LD1``. Note that the lanes retain the correct ordering. 76 …2. The content of a vector register is the same as if it had been loaded with an ``LD1`` instruc… 78 Because ``LD1 == LDR + REV`` and similarly ``LDR == LD1 + REV`` (on a big endian system), we can si… 133 …LD1`` only requires it to be as aligned as the lane size. If we canonicalised on using ``LDR``, we… 143 \| \| ``LDR`` layout \| ``LD1`` layout \| 145 \| Lane ordering \| ``LDR + REV`` \| ``LD1`` \| 147 \| AAPCS \| ``LDR`` \| ``LD1 + REV`` \| 149 \| Alignment for strict mode \| ``LDR`` / ``LD1 + REV`` \| ``LD1`` \| 188 …LD1`` of type ``X`` (converting the in-register representation to the same as if it had been loade… [all …]
/dports/devel/llvm11/llvm-11.0.1.src/docs/
H A D	BigEndianNEON.rst	52 ``LDR`` and ``LD1`` 66 Big endian vector load using ``LD1``. Note that the lanes retain the correct ordering. 76 …2. The content of a vector register is the same as if it had been loaded with an ``LD1`` instruc… 78 Because ``LD1 == LDR + REV`` and similarly ``LDR == LD1 + REV`` (on a big endian system), we can si… 133 …LD1`` only requires it to be as aligned as the lane size. If we canonicalised on using ``LDR``, we… 143 \| \| ``LDR`` layout \| ``LD1`` layout \| 145 \| Lane ordering \| ``LDR + REV`` \| ``LD1`` \| 147 \| AAPCS \| ``LDR`` \| ``LD1 + REV`` \| 149 \| Alignment for strict mode \| ``LDR`` / ``LD1 + REV`` \| ``LD1`` \| 188 …LD1`` of type ``X`` (converting the in-register representation to the same as if it had been loade… [all …]
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/docs/
H A D	BigEndianNEON.rst	52 ``LDR`` and ``LD1`` 66 Big endian vector load using ``LD1``. Note that the lanes retain the correct ordering. 76 …2. The content of a vector register is the same as if it had been loaded with an ``LD1`` instruc… 78 Because ``LD1 == LDR + REV`` and similarly ``LDR == LD1 + REV`` (on a big endian system), we can si… 133 …LD1`` only requires it to be as aligned as the lane size. If we canonicalised on using ``LDR``, we… 143 \| \| ``LDR`` layout \| ``LD1`` layout \| 145 \| Lane ordering \| ``LDR + REV`` \| ``LD1`` \| 147 \| AAPCS \| ``LDR`` \| ``LD1 + REV`` \| 149 \| Alignment for strict mode \| ``LDR`` / ``LD1 + REV`` \| ``LD1`` \| 188 …LD1`` of type ``X`` (converting the in-register representation to the same as if it had been loade… [all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/docs/
H A D	BigEndianNEON.rst	52 ``LDR`` and ``LD1`` 66 Big endian vector load using ``LD1``. Note that the lanes retain the correct ordering. 76 …2. The content of a vector register is the same as if it had been loaded with an ``LD1`` instruc… 78 Because ``LD1 == LDR + REV`` and similarly ``LDR == LD1 + REV`` (on a big endian system), we can si… 133 …LD1`` only requires it to be as aligned as the lane size. If we canonicalised on using ``LDR``, we… 143 \| \| ``LDR`` layout \| ``LD1`` layout \| 145 \| Lane ordering \| ``LDR + REV`` \| ``LD1`` \| 147 \| AAPCS \| ``LDR`` \| ``LD1 + REV`` \| 149 \| Alignment for strict mode \| ``LDR`` / ``LD1 + REV`` \| ``LD1`` \| 188 …LD1`` of type ``X`` (converting the in-register representation to the same as if it had been loade… [all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/docs/
H A D	BigEndianNEON.rst	52 ``LDR`` and ``LD1`` 66 Big endian vector load using ``LD1``. Note that the lanes retain the correct ordering. 76 …2. The content of a vector register is the same as if it had been loaded with an ``LD1`` instruc… 78 Because ``LD1 == LDR + REV`` and similarly ``LDR == LD1 + REV`` (on a big endian system), we can si… 133 …LD1`` only requires it to be as aligned as the lane size. If we canonicalised on using ``LDR``, we… 143 \| \| ``LDR`` layout \| ``LD1`` layout \| 145 \| Lane ordering \| ``LDR + REV`` \| ``LD1`` \| 147 \| AAPCS \| ``LDR`` \| ``LD1 + REV`` \| 149 \| Alignment for strict mode \| ``LDR`` / ``LD1 + REV`` \| ``LD1`` \| 188 …LD1`` of type ``X`` (converting the in-register representation to the same as if it had been loade… [all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/docs/
H A D	BigEndianNEON.rst	52 ``LDR`` and ``LD1`` 66 Big endian vector load using ``LD1``. Note that the lanes retain the correct ordering. 76 …2. The content of a vector register is the same as if it had been loaded with an ``LD1`` instruc… 78 Because ``LD1 == LDR + REV`` and similarly ``LDR == LD1 + REV`` (on a big endian system), we can si… 133 …LD1`` only requires it to be as aligned as the lane size. If we canonicalised on using ``LDR``, we… 143 \| \| ``LDR`` layout \| ``LD1`` layout \| 145 \| Lane ordering \| ``LDR + REV`` \| ``LD1`` \| 147 \| AAPCS \| ``LDR`` \| ``LD1 + REV`` \| 149 \| Alignment for strict mode \| ``LDR`` / ``LD1 + REV`` \| ``LD1`` \| 188 …LD1`` of type ``X`` (converting the in-register representation to the same as if it had been loade… [all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/docs/
H A D	BigEndianNEON.rst	52 ``LDR`` and ``LD1`` 66 Big endian vector load using ``LD1``. Note that the lanes retain the correct ordering. 76 …2. The content of a vector register is the same as if it had been loaded with an ``LD1`` instruc… 78 Because ``LD1 == LDR + REV`` and similarly ``LDR == LD1 + REV`` (on a big endian system), we can si… 133 …LD1`` only requires it to be as aligned as the lane size. If we canonicalised on using ``LDR``, we… 143 \| \| ``LDR`` layout \| ``LD1`` layout \| 145 \| Lane ordering \| ``LDR + REV`` \| ``LD1`` \| 147 \| AAPCS \| ``LDR`` \| ``LD1 + REV`` \| 149 \| Alignment for strict mode \| ``LDR`` / ``LD1 + REV`` \| ``LD1`` \| 188 …LD1`` of type ``X`` (converting the in-register representation to the same as if it had been loade… [all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/docs/
H A D	BigEndianNEON.rst	52 ``LDR`` and ``LD1`` 66 Big endian vector load using ``LD1``. Note that the lanes retain the correct ordering. 76 …2. The content of a vector register is the same as if it had been loaded with an ``LD1`` instruc… 78 Because ``LD1 == LDR + REV`` and similarly ``LDR == LD1 + REV`` (on a big endian system), we can si… 133 …LD1`` only requires it to be as aligned as the lane size. If we canonicalised on using ``LDR``, we… 143 \| \| ``LDR`` layout \| ``LD1`` layout \| 145 \| Lane ordering \| ``LDR + REV`` \| ``LD1`` \| 147 \| AAPCS \| ``LDR`` \| ``LD1 + REV`` \| 149 \| Alignment for strict mode \| ``LDR`` / ``LD1 + REV`` \| ``LD1`` \| 188 …LD1`` of type ``X`` (converting the in-register representation to the same as if it had been loade… [all …]
/dports/devel/llvm90/llvm-9.0.1.src/docs/
H A D	BigEndianNEON.rst	52 ``LDR`` and ``LD1`` 66 Big endian vector load using ``LD1``. Note that the lanes retain the correct ordering. 76 …2. The content of a vector register is the same as if it had been loaded with an ``LD1`` instruc… 78 Because ``LD1 == LDR + REV`` and similarly ``LDR == LD1 + REV`` (on a big endian system), we can si… 133 …LD1`` only requires it to be as aligned as the lane size. If we canonicalised on using ``LDR``, we… 143 \| \| ``LDR`` layout \| ``LD1`` layout \| 145 \| Lane ordering \| ``LDR + REV`` \| ``LD1`` \| 147 \| AAPCS \| ``LDR`` \| ``LD1 + REV`` \| 149 \| Alignment for strict mode \| ``LDR`` / ``LD1 + REV`` \| ``LD1`` \| 188 …LD1`` of type ``X`` (converting the in-register representation to the same as if it had been loade… [all …]
/dports/devel/llvm80/llvm-8.0.1.src/docs/
H A D	BigEndianNEON.rst	52 ``LDR`` and ``LD1`` 66 Big endian vector load using ``LD1``. Note that the lanes retain the correct ordering. 76 …2. The content of a vector register is the same as if it had been loaded with an ``LD1`` instruc… 78 Because ``LD1 == LDR + REV`` and similarly ``LDR == LD1 + REV`` (on a big endian system), we can si… 133 …LD1`` only requires it to be as aligned as the lane size. If we canonicalised on using ``LDR``, we… 143 \| \| ``LDR`` layout \| ``LD1`` layout \| 145 \| Lane ordering \| ``LDR + REV`` \| ``LD1`` \| 147 \| AAPCS \| ``LDR`` \| ``LD1 + REV`` \| 149 \| Alignment for strict mode \| ``LDR`` / ``LD1 + REV`` \| ``LD1`` \| 188 …LD1`` of type ``X`` (converting the in-register representation to the same as if it had been loade… [all …]
/dports/devel/llvm70/llvm-7.0.1.src/docs/
H A D	BigEndianNEON.rst	52 ``LDR`` and ``LD1`` 66 Big endian vector load using ``LD1``. Note that the lanes retain the correct ordering. 76 …2. The content of a vector register is the same as if it had been loaded with an ``LD1`` instruc… 78 Because ``LD1 == LDR + REV`` and similarly ``LDR == LD1 + REV`` (on a big endian system), we can si… 133 …LD1`` only requires it to be as aligned as the lane size. If we canonicalised on using ``LDR``, we… 143 \| \| ``LDR`` layout \| ``LD1`` layout \| 145 \| Lane ordering \| ``LDR + REV`` \| ``LD1`` \| 147 \| AAPCS \| ``LDR`` \| ``LD1 + REV`` \| 149 \| Alignment for strict mode \| ``LDR`` / ``LD1 + REV`` \| ``LD1`` \| 188 …LD1`` of type ``X`` (converting the in-register representation to the same as if it had been loade… [all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/ARM/
H A D	vcombine.ll	`7 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1] 10 ; CHECK-LE-DAG: vmov r2, r3, [[LD1]] 23 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1] 26 ; CHECK-LE-DAG: vmov r2, r3, [[LD1]] 40 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1] 42 ; CHECK-LE: vmov r2, r3, [[LD1]] 57 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1] 59 ; CHECK-LE: vmov r2, r3, [[LD1]] 73 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1] 75 ; CHECK-LE: vmov r2, r3, [[LD1]] [all …]`
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/ARM/
H A D	vcombine.ll	`7 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1] 10 ; CHECK-LE-DAG: vmov r2, r3, [[LD1]] 23 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1] 26 ; CHECK-LE-DAG: vmov r2, r3, [[LD1]] 40 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1] 42 ; CHECK-LE: vmov r2, r3, [[LD1]] 57 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1] 59 ; CHECK-LE: vmov r2, r3, [[LD1]] 73 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1] 75 ; CHECK-LE: vmov r2, r3, [[LD1]] [all …]`
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/ARM/
H A D	vcombine.ll	`7 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1] 10 ; CHECK-LE-DAG: vmov r2, r3, [[LD1]] 23 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1] 26 ; CHECK-LE-DAG: vmov r2, r3, [[LD1]] 40 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1] 42 ; CHECK-LE: vmov r2, r3, [[LD1]] 57 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1] 59 ; CHECK-LE: vmov r2, r3, [[LD1]] 73 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1] 75 ; CHECK-LE: vmov r2, r3, [[LD1]] [all …]`
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/ARM/
H A D	vcombine.ll	`7 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1] 10 ; CHECK-LE-DAG: vmov r2, r3, [[LD1]] 23 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1] 26 ; CHECK-LE-DAG: vmov r2, r3, [[LD1]] 40 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1] 42 ; CHECK-LE: vmov r2, r3, [[LD1]] 57 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1] 59 ; CHECK-LE: vmov r2, r3, [[LD1]] 73 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1] 75 ; CHECK-LE: vmov r2, r3, [[LD1]] [all …]`

12 3 4 5 6 7 8 9 10 >>...38