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Searched refs:LPCR_VPM0 (Results 1 – 25 of 36) sorted by relevance

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/dports/emulators/qemu42/qemu-4.2.1/target/ppc/
H A Dmmu-hash64.c685 vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0); in ppc_hash64_set_isi()
711 vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0); in ppc_hash64_set_dsi()
799 if (env->spr[SPR_LPCR] & LPCR_VPM0) { in ppc_hash64_handle_mmu_fault()
962 if (env->spr[SPR_LPCR] & LPCR_VPM0) { in ppc_hash64_get_phys_page_debug()
1050 if (!(lpcr & LPCR_VPM0)) { in ppc_hash64_update_vrma()
1127 lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | in ppc_store_lpcr()
1134 lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | in ppc_store_lpcr()
H A Dcpu.h348 #define LPCR_VPM0 PPC_BIT(0) macro
/dports/emulators/qemu-utils/qemu-4.2.1/target/ppc/
H A Dmmu-hash64.c685 vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0); in ppc_hash64_set_isi()
711 vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0); in ppc_hash64_set_dsi()
799 if (env->spr[SPR_LPCR] & LPCR_VPM0) { in ppc_hash64_handle_mmu_fault()
962 if (env->spr[SPR_LPCR] & LPCR_VPM0) { in ppc_hash64_get_phys_page_debug()
1050 if (!(lpcr & LPCR_VPM0)) { in ppc_hash64_update_vrma()
1127 lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | in ppc_store_lpcr()
1134 lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | in ppc_store_lpcr()
H A Dcpu.h348 #define LPCR_VPM0 PPC_BIT(0) macro
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/ppc/
H A Dmmu-hash64.c661 vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0); in ppc_hash64_set_isi()
687 vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0); in ppc_hash64_set_dsi()
772 if (env->spr[SPR_LPCR] & LPCR_VPM0) { in ppc_hash64_handle_mmu_fault()
932 if (env->spr[SPR_LPCR] & LPCR_VPM0) { in ppc_hash64_get_phys_page_debug()
1020 if (!(lpcr & LPCR_VPM0)) { in ppc_hash64_update_vrma()
1095 lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | in ppc_store_lpcr()
1102 lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | in ppc_store_lpcr()
H A Dcpu.h384 #define LPCR_VPM0 PPC_BIT(0) macro
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/ppc/
H A Dspapr_cpu_core.c62 lpcr &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm); in spapr_cpu_reset()
/dports/emulators/qemu42/qemu-4.2.1/hw/ppc/
H A Dspapr_cpu_core.c61 lpcr &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm); in spapr_reset_vcpu()
/dports/emulators/qemu-utils/qemu-4.2.1/hw/ppc/
H A Dspapr_cpu_core.c61 lpcr &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm); in spapr_reset_vcpu()
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/powerpc/kernel/
H A Ddt_cpu_ftrs.c278 lpcr |= LPCR_VPM0; in feat_enable_mmu_hash()
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/powerpc/kernel/
H A Ddt_cpu_ftrs.c278 lpcr |= LPCR_VPM0; in feat_enable_mmu_hash()
/dports/multimedia/libv4l/linux-5.13-rc2/arch/powerpc/kernel/
H A Ddt_cpu_ftrs.c278 lpcr |= LPCR_VPM0; in feat_enable_mmu_hash()
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/powerpc/include/asm/
H A Dreg.h431 #define LPCR_VPM0 ASM_CONST(0x8000000000000000) macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/powerpc/include/asm/
H A Dreg.h431 #define LPCR_VPM0 ASM_CONST(0x8000000000000000) macro
/dports/multimedia/libv4l/linux-5.13-rc2/arch/powerpc/include/asm/
H A Dreg.h431 #define LPCR_VPM0 ASM_CONST(0x8000000000000000) macro
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/ppc/
H A Dmmu-hash64.c742 return !!(env->spr[SPR_LPCR] & LPCR_VPM0); in ppc_hash64_use_vrma()
/dports/emulators/qemu/qemu-6.2.0/target/ppc/
H A Dmmu-hash64.c742 return !!(env->spr[SPR_LPCR] & LPCR_VPM0); in ppc_hash64_use_vrma()
/dports/emulators/qemu5/qemu-5.2.0/target/ppc/
H A Dmmu-hash64.c734 return !!(env->spr[SPR_LPCR] & LPCR_VPM0); in ppc_hash64_use_vrma()
H A Dcpu.h345 #define LPCR_VPM0 PPC_BIT(0) macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/ppc/
H A Dmmu-hash64.c734 return !!(env->spr[SPR_LPCR] & LPCR_VPM0); in ppc_hash64_use_vrma()
H A Dcpu.h343 #define LPCR_VPM0 PPC_BIT(0) macro
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/ppc/
H A Dmmu-hash64.c683 return !!(env->spr[SPR_LPCR] & LPCR_VPM0); in ppc_hash64_use_vrma()
H A Dcpu.h343 #define LPCR_VPM0 PPC_BIT(0) macro
/dports/emulators/qemu60/qemu-6.0.0/target/ppc/
H A Dmmu-hash64.c734 return !!(env->spr[SPR_LPCR] & LPCR_VPM0); in ppc_hash64_use_vrma()
H A Dcpu.h345 #define LPCR_VPM0 PPC_BIT(0) macro

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