| /dports/devel/llvm90/llvm-9.0.1.src/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 186 MFVSR, enumerator
|
| H A D | PPCISelLowering.cpp | 1336 case PPCISD::MFVSR: return "PPCISD::MFVSR"; in getTargetNodeName()
7337 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i32, Tmp); in LowerFP_TO_INTDirectMove()
7345 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i64, Tmp); in LowerFP_TO_INTDirectMove()
12442 assert(FirstInput.getOpcode() == PPCISD::MFVSR && in combineElementTruncationToVectorTruncation()
12460 if (NextOp.getOpcode() != PPCISD::MFVSR) in combineElementTruncationToVectorTruncation()
12752 if (FirstInput.getOpcode() == PPCISD::MFVSR) { in DAGCombineBuildVector()
|
| /dports/devel/llvm80/llvm-8.0.1.src/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 188 MFVSR, enumerator
|
| H A D | PPCISelLowering.cpp | 1309 case PPCISD::MFVSR: return "PPCISD::MFVSR"; in getTargetNodeName()
7082 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i32, Tmp); in LowerFP_TO_INTDirectMove()
7090 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i64, Tmp); in LowerFP_TO_INTDirectMove()
11983 assert(FirstInput.getOpcode() == PPCISD::MFVSR && in combineElementTruncationToVectorTruncation()
12001 if (NextOp.getOpcode() != PPCISD::MFVSR) in combineElementTruncationToVectorTruncation()
12288 if (FirstInput.getOpcode() == PPCISD::MFVSR) { in DAGCombineBuildVector()
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 184 MFVSR, enumerator
|
| H A D | PPCISelLowering.cpp | 1300 case PPCISD::MFVSR: return "PPCISD::MFVSR";
7027 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i32, Tmp);
7035 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i64, Tmp);
11778 assert(FirstInput.getOpcode() == PPCISD::MFVSR &&
11796 if (NextOp.getOpcode() != PPCISD::MFVSR)
12082 if (FirstInput.getOpcode() == PPCISD::MFVSR) {
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 198 MFVSR, enumerator
|
| H A D | PPCISelLowering.cpp | 1410 case PPCISD::MFVSR: return "PPCISD::MFVSR"; in getTargetNodeName()
7788 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i32, Tmp); in LowerFP_TO_INTDirectMove()
7796 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i64, Tmp); in LowerFP_TO_INTDirectMove()
12979 assert(FirstInput.getOpcode() == PPCISD::MFVSR && in combineElementTruncationToVectorTruncation()
12997 if (NextOp.getOpcode() != PPCISD::MFVSR) in combineElementTruncationToVectorTruncation()
13289 if (FirstInput.getOpcode() == PPCISD::MFVSR) { in DAGCombineBuildVector()
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 207 MFVSR, enumerator
|
| H A D | PPCISelLowering.cpp | 1507 case PPCISD::MFVSR: return "PPCISD::MFVSR"; in getTargetNodeName()
8290 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i32, Tmp); in LowerFP_TO_INTDirectMove()
8298 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i64, Tmp); in LowerFP_TO_INTDirectMove()
13834 assert(FirstInput.getOpcode() == PPCISD::MFVSR && in combineElementTruncationToVectorTruncation()
13852 if (NextOp.getOpcode() != PPCISD::MFVSR) in combineElementTruncationToVectorTruncation()
14149 if (FirstInput.getOpcode() == PPCISD::MFVSR) { in DAGCombineBuildVector()
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 198 MFVSR, enumerator
|
| H A D | PPCISelLowering.cpp | 1410 case PPCISD::MFVSR: return "PPCISD::MFVSR"; in getTargetNodeName()
7788 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i32, Tmp); in LowerFP_TO_INTDirectMove()
7796 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i64, Tmp); in LowerFP_TO_INTDirectMove()
12979 assert(FirstInput.getOpcode() == PPCISD::MFVSR && in combineElementTruncationToVectorTruncation()
12997 if (NextOp.getOpcode() != PPCISD::MFVSR) in combineElementTruncationToVectorTruncation()
13289 if (FirstInput.getOpcode() == PPCISD::MFVSR) { in DAGCombineBuildVector()
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 212 MFVSR, enumerator
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 207 MFVSR, enumerator
|
| H A D | PPCISelLowering.cpp | 1506 case PPCISD::MFVSR: return "PPCISD::MFVSR"; in getTargetNodeName()
8289 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i32, Tmp); in LowerFP_TO_INTDirectMove()
8297 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i64, Tmp); in LowerFP_TO_INTDirectMove()
13860 assert(FirstInput.getOpcode() == PPCISD::MFVSR && in combineElementTruncationToVectorTruncation()
13878 if (NextOp.getOpcode() != PPCISD::MFVSR) in combineElementTruncationToVectorTruncation()
14175 if (FirstInput.getOpcode() == PPCISD::MFVSR) { in DAGCombineBuildVector()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 198 MFVSR, enumerator
|
| H A D | PPCISelLowering.cpp | 1392 case PPCISD::MFVSR: return "PPCISD::MFVSR"; in getTargetNodeName()
7767 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i32, Tmp); in LowerFP_TO_INTDirectMove()
7775 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i64, Tmp); in LowerFP_TO_INTDirectMove()
12951 assert(FirstInput.getOpcode() == PPCISD::MFVSR && in combineElementTruncationToVectorTruncation()
12969 if (NextOp.getOpcode() != PPCISD::MFVSR) in combineElementTruncationToVectorTruncation()
13261 if (FirstInput.getOpcode() == PPCISD::MFVSR) { in DAGCombineBuildVector()
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 212 MFVSR, enumerator
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 207 MFVSR, enumerator
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 212 MFVSR, in PPCTargetLowering()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 212 MFVSR, enumerator
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 212 MFVSR, enumerator
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 212 MFVSR, enumerator
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 212 MFVSR, enumerator
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 212 MFVSR, enumerator
|