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Searched refs:MIPS_VFPU4 (Results 1 – 6 of 6) sorted by relevance

/dports/emulators/ppsspp-qt5/ppsspp-1.12.3/ext/armips/Archs/MIPS/
H A DMipsOpcodes.h87 #define MIPS_VFPU4(VALUE) (MIPS_OP(52) | MIPS_RS(VALUE)) macro
88 #define MIPS_VFPU4_11(VALUE) (MIPS_VFPU4(0) | MIPS_RT(VALUE))
89 #define MIPS_VFPU4_12(VALUE) (MIPS_VFPU4(1) | MIPS_RT(VALUE))
90 #define MIPS_VFPU4_13(VALUE) (MIPS_VFPU4(2) | MIPS_RT(VALUE))
H A DMipsOpcodes.cpp687 { "vcst.S", "vd,Wc", MIPS_VFPU4(0x03), MA_PSP, MO_VFPU },
688 { "vf2in.S", "vd,vs,i5", MIPS_VFPU4(0x10), MA_PSP, MO_VFPU },
689 { "vf2iz.S", "vd,vs,i5", MIPS_VFPU4(0x11), MA_PSP, MO_VFPU },
690 { "vf2iu.S", "vd,vs,i5", MIPS_VFPU4(0x12), MA_PSP, MO_VFPU },
691 { "vf2id.S", "vd,vs,i5", MIPS_VFPU4(0x13), MA_PSP, MO_VFPU },
692 { "vi2f.S", "vd,vs,i5", MIPS_VFPU4(0x14), MA_PSP, MO_VFPU },
693 { "vcmovt.S", "vd,vs,i5", MIPS_VFPU4(0x15)|0, MA_PSP, MO_VFPU },
694 { "vcmovf.S", "vd,vs,i5", MIPS_VFPU4(0x15)|(1<<19), MA_PSP, MO_VFPU },
695 { "vwbn.S", "vd,vs,i5", MIPS_VFPU4(0x18), MA_PSP, MO_VFPU },
/dports/emulators/ppsspp/ppsspp-1.12.3/ext/armips/Archs/MIPS/
H A DMipsOpcodes.h87 #define MIPS_VFPU4(VALUE) (MIPS_OP(52) | MIPS_RS(VALUE)) macro
88 #define MIPS_VFPU4_11(VALUE) (MIPS_VFPU4(0) | MIPS_RT(VALUE))
89 #define MIPS_VFPU4_12(VALUE) (MIPS_VFPU4(1) | MIPS_RT(VALUE))
90 #define MIPS_VFPU4_13(VALUE) (MIPS_VFPU4(2) | MIPS_RT(VALUE))
H A DMipsOpcodes.cpp687 { "vcst.S", "vd,Wc", MIPS_VFPU4(0x03), MA_PSP, MO_VFPU },
688 { "vf2in.S", "vd,vs,i5", MIPS_VFPU4(0x10), MA_PSP, MO_VFPU },
689 { "vf2iz.S", "vd,vs,i5", MIPS_VFPU4(0x11), MA_PSP, MO_VFPU },
690 { "vf2iu.S", "vd,vs,i5", MIPS_VFPU4(0x12), MA_PSP, MO_VFPU },
691 { "vf2id.S", "vd,vs,i5", MIPS_VFPU4(0x13), MA_PSP, MO_VFPU },
692 { "vi2f.S", "vd,vs,i5", MIPS_VFPU4(0x14), MA_PSP, MO_VFPU },
693 { "vcmovt.S", "vd,vs,i5", MIPS_VFPU4(0x15)|0, MA_PSP, MO_VFPU },
694 { "vcmovf.S", "vd,vs,i5", MIPS_VFPU4(0x15)|(1<<19), MA_PSP, MO_VFPU },
695 { "vwbn.S", "vd,vs,i5", MIPS_VFPU4(0x18), MA_PSP, MO_VFPU },
/dports/emulators/libretro-ppsspp/ppsspp-1.12.3/ext/armips/Archs/MIPS/
H A DMipsOpcodes.h87 #define MIPS_VFPU4(VALUE) (MIPS_OP(52) | MIPS_RS(VALUE)) macro
88 #define MIPS_VFPU4_11(VALUE) (MIPS_VFPU4(0) | MIPS_RT(VALUE))
89 #define MIPS_VFPU4_12(VALUE) (MIPS_VFPU4(1) | MIPS_RT(VALUE))
90 #define MIPS_VFPU4_13(VALUE) (MIPS_VFPU4(2) | MIPS_RT(VALUE))
H A DMipsOpcodes.cpp687 { "vcst.S", "vd,Wc", MIPS_VFPU4(0x03), MA_PSP, MO_VFPU },
688 { "vf2in.S", "vd,vs,i5", MIPS_VFPU4(0x10), MA_PSP, MO_VFPU },
689 { "vf2iz.S", "vd,vs,i5", MIPS_VFPU4(0x11), MA_PSP, MO_VFPU },
690 { "vf2iu.S", "vd,vs,i5", MIPS_VFPU4(0x12), MA_PSP, MO_VFPU },
691 { "vf2id.S", "vd,vs,i5", MIPS_VFPU4(0x13), MA_PSP, MO_VFPU },
692 { "vi2f.S", "vd,vs,i5", MIPS_VFPU4(0x14), MA_PSP, MO_VFPU },
693 { "vcmovt.S", "vd,vs,i5", MIPS_VFPU4(0x15)|0, MA_PSP, MO_VFPU },
694 { "vcmovf.S", "vd,vs,i5", MIPS_VFPU4(0x15)|(1<<19), MA_PSP, MO_VFPU },
695 { "vwbn.S", "vd,vs,i5", MIPS_VFPU4(0x18), MA_PSP, MO_VFPU },