1 #pragma once 2 #include "Mips.h" 3 4 #define MA_MIPS1 0x00000001 5 #define MA_MIPS2 0x00000002 6 #define MA_MIPS3 0x00000004 7 #define MA_MIPS4 0x00000008 8 #define MA_PSX 0x00000010 9 #define MA_PS2 0x00000040 10 #define MA_PSP 0x00000080 11 #define MA_RSP 0x00000100 12 13 #define MA_EXPSX 0x00001000 14 #define MA_EXN64 0x00002000 15 #define MA_EXPS2 0x00004000 16 #define MA_EXPSP 0x00008000 17 #define MA_EXRSP 0x00010000 18 19 #define MO_IPCA 0x00000001 // pc >> 2 20 #define MO_IPCR 0x00000002 // PC, -> difference >> 2 21 #define MO_RSD 0x00000004 // rs = rd 22 #define MO_RST 0x00000008 // rs = rt 23 #define MO_RDT 0x00000010 // rd = rt 24 #define MO_DELAY 0x00000020 // delay slot follows 25 #define MO_NODELAYSLOT 0x00000040 // can't be in a delay slot 26 #define MO_DELAYRT 0x00000080 // rt won't be available for one instruction 27 #define MO_IGNORERTD 0x00000100 // don't care for rt delay 28 #define MO_FRSD 0x00000200 // float rs + rd 29 #define MO_IMMALIGNED 0x00000400 // immediate 4 byte aligned 30 #define MO_VFPU_MIXED 0x00000800 // mixed mode vfpu register 31 #define MO_VFPU_6BIT 0x00001000 // vfpu register can have 6 bits max 32 #define MO_VFPU_SINGLE 0x00002000 // single vfpu reg 33 #define MO_VFPU_QUAD 0x00004000 // quad vfpu reg 34 #define MO_VFPU 0x00008000 // vfpu type opcode 35 #define MO_64BIT 0x00010000 // only available on 64 bit cpus 36 #define MO_FPU 0x00020000 // only available with an fpu 37 #define MO_TRANSPOSE_VS 0x00040000 // matrix vs has to be transposed 38 #define MO_VFPU_PAIR 0x00080000 // pair vfpu reg 39 #define MO_VFPU_TRIPLE 0x00100000 // triple vfpu reg 40 #define MO_DFPU 0x00200000 // double-precision fpu opcodes 41 #define MO_RSPVRSD 0x00400000 // rsp vector rs + rd 42 #define MO_NEGIMM 0x00800000 // negated immediate (for subi) 43 #define MO_RSP_HWOFFSET 0x01000000 // RSP halfword load/store offset 44 #define MO_RSP_WOFFSET 0x02000000 // RSP word load/store offset 45 #define MO_RSP_DWOFFSET 0x04000000 // RSP doubleword load/store offset 46 #define MO_RSP_QWOFFSET 0x08000000 // RSP quadword load/store offset 47 48 #define BITFIELD(START,LENGTH,VALUE) (((VALUE) & ((1 << (LENGTH)) - 1)) << (START)) 49 #define MIPS_FUNC(VALUE) BITFIELD(0,6,(VALUE)) 50 #define MIPS_SA(VALUE) BITFIELD(6,5,(VALUE)) 51 #define MIPS_SECFUNC(VALUE) MIPS_SA((VALUE)) 52 #define MIPS_OP(VALUE) BITFIELD(26,6,(VALUE)) 53 54 #define MIPS_RS(VALUE) BITFIELD(21,5,(VALUE)) 55 #define MIPS_RT(VALUE) BITFIELD(16,5,(VALUE)) 56 #define MIPS_RD(VALUE) BITFIELD(11,5,(VALUE)) 57 #define MIPS_FS(VALUE) MIPS_RD((VALUE)) 58 #define MIPS_FT(VALUE) MIPS_RT((VALUE)) 59 #define MIPS_FD(VALUE) MIPS_SA((VALUE)) 60 61 #define MIPS_SPECIAL(VALUE) (MIPS_OP(0) | MIPS_FUNC(VALUE)) 62 #define MIPS_REGIMM(VALUE) (MIPS_OP(1) | MIPS_RT(VALUE)) 63 #define MIPS_COP0(VALUE) (MIPS_OP(16) | MIPS_RS(VALUE)) 64 #define MIPS_COP0FUNCT(VALUE) (MIPS_COP0(16) | MIPS_FUNC(VALUE)) 65 #define MIPS_COP1(VALUE) (MIPS_OP(17) | MIPS_RS(VALUE)) 66 #define MIPS_COP1BC(VALUE) (MIPS_COP1(8) | MIPS_RT(VALUE)) 67 #define MIPS_COP1S(VALUE) (MIPS_COP1(16) | MIPS_FUNC(VALUE)) 68 #define MIPS_COP1D(VALUE) (MIPS_COP1(17) | MIPS_FUNC(VALUE)) 69 #define MIPS_COP1W(VALUE) (MIPS_COP1(20) | MIPS_FUNC(VALUE)) 70 #define MIPS_COP1L(VALUE) (MIPS_COP1(21) | MIPS_FUNC(VALUE)) 71 72 #define MIPS_VFPUSIZE(VALUE) ( (((VALUE) & 1) << 7) | (((VALUE) & 2) << 14) ) 73 #define MIPS_VFPUFUNC(VALUE) BITFIELD(23, 3, (VALUE)) 74 #define MIPS_COP2(VALUE) (MIPS_OP(18) | MIPS_RS(VALUE)) 75 #define MIPS_COP2BC(VALUE) (MIPS_COP2(8) | MIPS_RT(VALUE)) 76 #define MIPS_RSP_COP2(VALUE) (MIPS_OP(18) | (1 << 25) | MIPS_FUNC(VALUE)) 77 #define MIPS_RSP_LWC2(VALUE) (MIPS_OP(50) | MIPS_RD(VALUE)) 78 #define MIPS_RSP_SWC2(VALUE) (MIPS_OP(58) | MIPS_RD(VALUE)) 79 #define MIPS_RSP_VE(VALUE) BITFIELD(21, 4, (VALUE)) 80 #define MIPS_RSP_VDE(VALUE) BITFIELD(11, 4, (VALUE)) 81 #define MIPS_RSP_VEALT(VALUE) BITFIELD(7, 4, (VALUE)) 82 #define MIPS_VFPU0(VALUE) (MIPS_OP(24) | MIPS_VFPUFUNC(VALUE)) 83 #define MIPS_VFPU1(VALUE) (MIPS_OP(25) | MIPS_VFPUFUNC(VALUE)) 84 #define MIPS_VFPU3(VALUE) (MIPS_OP(27) | MIPS_VFPUFUNC(VALUE)) 85 #define MIPS_SPECIAL3(VALUE) (MIPS_OP(31) | MIPS_FUNC(VALUE)) 86 #define MIPS_ALLEGREX0(VALUE) (MIPS_SPECIAL3(32) | MIPS_SECFUNC(VALUE)) 87 #define MIPS_VFPU4(VALUE) (MIPS_OP(52) | MIPS_RS(VALUE)) 88 #define MIPS_VFPU4_11(VALUE) (MIPS_VFPU4(0) | MIPS_RT(VALUE)) 89 #define MIPS_VFPU4_12(VALUE) (MIPS_VFPU4(1) | MIPS_RT(VALUE)) 90 #define MIPS_VFPU4_13(VALUE) (MIPS_VFPU4(2) | MIPS_RT(VALUE)) 91 #define MIPS_VFPU5(VALUE) (MIPS_OP(55) | MIPS_VFPUFUNC(VALUE)) 92 #define MIPS_VFPU6(VALUE) (MIPS_OP(60) | MIPS_VFPUFUNC(VALUE)) 93 #define MIPS_VFPU6_1(VALUE) (MIPS_VFPU6(7) | BITFIELD(20, 3, VALUE)) 94 // This is a bit ugly, VFPU opcodes are encoded strangely. 95 #define MIPS_VFPU6_1VROT() (MIPS_VFPU6(7) | BITFIELD(21, 2, 1)) 96 #define MIPS_VFPU6_2(VALUE) (MIPS_VFPU6_1(0) | MIPS_RT(VALUE)) 97 98 99 struct MipsArchDefinition 100 { 101 const char* name; 102 int supportSets; 103 int excludeMask; 104 int flags; 105 }; 106 107 extern const MipsArchDefinition mipsArchs[]; 108 109 typedef struct { 110 const char* name; 111 const char* encoding; 112 int destencoding; 113 int archs; 114 int flags; 115 } tMipsOpcode; 116 117 extern const tMipsOpcode MipsOpcodes[]; 118