/dports/lang/gnatdroid-binutils-x86/binutils-2.27/opcodes/ |
H A D | mips16-opc.c | 152 #define MOD_1 (WR_1|RD_1) macro 189 {"addiu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 }, 196 {"addu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 }, 233 {"daddiu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 }, 240 {"daddu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 }, 355 {"seb", "x", 0xe891, 0xf8ff, MOD_1, 0, I32, 0, 0 }, 356 {"seh", "x", 0xe8b1, 0xf8ff, MOD_1, 0, I32, 0, 0 }, 357 {"sew", "x", 0xe8d1, 0xf8ff, MOD_1, 0, I64, 0, 0 }, 358 {"zeb", "x", 0xe811, 0xf8ff, MOD_1, 0, I32, 0, 0 }, 359 {"zeh", "x", 0xe831, 0xf8ff, MOD_1, 0, I32, 0, 0 }, [all …]
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H A D | micromips-opc.c | 216 #define MOD_1 (WR_1|RD_1) macro 334 {"addius5", "mp,mX", 0x4c00, 0xfc01, MOD_1, 0, I1, 0, 0 }, 341 {"and", "mf,mt,mg", 0x4480, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 }, 342 {"and", "mf,mg,mx", 0x4480, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 }, 914 {"or", "mf,mt,mg", 0x44c0, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 }, 915 {"or", "mf,mg,mx", 0x44c0, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 }, 955 {"sc", "t,~(b)", 0x6000b000, 0xfc00f000, MOD_1|RD_3|SM, 0, I1, 0, 0 }, 1126 {"xor", "mf,mt,mg", 0x4440, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 }, 1127 {"xor", "mf,mg,mx", 0x4440, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 }, 1280 {"append", "t,s,h", 0x00000215, 0xfc0007ff, MOD_1|RD_2, 0, 0, D33, 0 }, [all …]
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H A D | mips-opc.c | 235 #define MOD_1 (WR_1|RD_1) macro 1796 {"sc", "t,+j(b)", 0x7c000026, 0xfc00007f, MOD_1|RD_3|SM, 0, I37, 0, 0 }, 1799 {"scd", "t,+j(b)", 0x7c000027, 0xfc00007f, MOD_1|RD_3|SM, 0, I69, 0, 0 }, 1940 {"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, 1942 {"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, 2906 {"sldi.b", "+d,+e+o", 0x78000019, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, 2907 {"sldi.h", "+d,+e+u", 0x78200019, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 }, 2908 {"sldi.w", "+d,+e+v", 0x78300019, 0xfffc003f, MOD_1|RD_2, 0, 0, MSA, 0 }, 2909 {"sldi.d", "+d,+e+w", 0x78380019, 0xfffe003f, MOD_1|RD_2, 0, 0, MSA, 0 }, 3226 {"dahi", "s,-d,u", 0x04060000, 0xfc1f0000, MOD_1, 0, I69, 0, 0 }, [all …]
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H A D | ChangeLog-2013 | 342 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI): 348 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): 358 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
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/dports/lang/gnatdroid-binutils/binutils-2.27/opcodes/ |
H A D | mips16-opc.c | 152 #define MOD_1 (WR_1|RD_1) macro 189 {"addiu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 }, 196 {"addu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 }, 233 {"daddiu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 }, 240 {"daddu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 }, 355 {"seb", "x", 0xe891, 0xf8ff, MOD_1, 0, I32, 0, 0 }, 356 {"seh", "x", 0xe8b1, 0xf8ff, MOD_1, 0, I32, 0, 0 }, 357 {"sew", "x", 0xe8d1, 0xf8ff, MOD_1, 0, I64, 0, 0 }, 358 {"zeb", "x", 0xe811, 0xf8ff, MOD_1, 0, I32, 0, 0 }, 359 {"zeh", "x", 0xe831, 0xf8ff, MOD_1, 0, I32, 0, 0 }, [all …]
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H A D | micromips-opc.c | 216 #define MOD_1 (WR_1|RD_1) macro 334 {"addius5", "mp,mX", 0x4c00, 0xfc01, MOD_1, 0, I1, 0, 0 }, 341 {"and", "mf,mt,mg", 0x4480, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 }, 342 {"and", "mf,mg,mx", 0x4480, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 }, 914 {"or", "mf,mt,mg", 0x44c0, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 }, 915 {"or", "mf,mg,mx", 0x44c0, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 }, 955 {"sc", "t,~(b)", 0x6000b000, 0xfc00f000, MOD_1|RD_3|SM, 0, I1, 0, 0 }, 1126 {"xor", "mf,mt,mg", 0x4440, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 }, 1127 {"xor", "mf,mg,mx", 0x4440, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 }, 1280 {"append", "t,s,h", 0x00000215, 0xfc0007ff, MOD_1|RD_2, 0, 0, D33, 0 }, [all …]
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H A D | mips-opc.c | 235 #define MOD_1 (WR_1|RD_1) macro 1796 {"sc", "t,+j(b)", 0x7c000026, 0xfc00007f, MOD_1|RD_3|SM, 0, I37, 0, 0 }, 1799 {"scd", "t,+j(b)", 0x7c000027, 0xfc00007f, MOD_1|RD_3|SM, 0, I69, 0, 0 }, 1940 {"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, 1942 {"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, 2906 {"sldi.b", "+d,+e+o", 0x78000019, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, 2907 {"sldi.h", "+d,+e+u", 0x78200019, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 }, 2908 {"sldi.w", "+d,+e+v", 0x78300019, 0xfffc003f, MOD_1|RD_2, 0, 0, MSA, 0 }, 2909 {"sldi.d", "+d,+e+w", 0x78380019, 0xfffe003f, MOD_1|RD_2, 0, 0, MSA, 0 }, 3226 {"dahi", "s,-d,u", 0x04060000, 0xfc1f0000, MOD_1, 0, I69, 0, 0 }, [all …]
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H A D | ChangeLog-2013 | 342 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI): 348 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): 358 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
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/dports/devel/arm-elf-binutils/binutils-2.37/opcodes/ |
H A D | mips16-opc.c | 171 #define MOD_1 (WR_1|RD_1) macro 217 {"addiu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 }, 227 {"addu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 }, 270 {"daddiu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 }, 277 {"daddu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 }, 304 {"dsra", "y,]", 0xe813, 0xf81f, MOD_1, 0, I3, 0, 0 }, 307 {"dsrl", "y,]", 0xe808, 0xf81f, MOD_1, 0, I3, 0, 0 }, 451 {"seb", "x", 0xe891, 0xf8ff, MOD_1, SH, I32, 0, 0 }, 452 {"seh", "x", 0xe8b1, 0xf8ff, MOD_1, SH, I32, 0, 0 }, 453 {"sew", "x", 0xe8d1, 0xf8ff, MOD_1, SH, I64, 0, 0 }, [all …]
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H A D | micromips-opc.c | 217 #define MOD_1 (WR_1|RD_1) macro 342 {"addius5", "mp,mX", 0x4c00, 0xfc01, MOD_1, 0, I1, 0, 0 }, 349 {"and", "mf,mt,mg", 0x4480, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 }, 350 {"and", "mf,mg,mx", 0x4480, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 }, 937 {"or", "mf,mt,mg", 0x44c0, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 }, 938 {"or", "mf,mg,mx", 0x44c0, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 }, 978 {"sc", "t,~(b)", 0x6000b000, 0xfc00f000, MOD_1|RD_3|SM, 0, I1, 0, 0 }, 1149 {"xor", "mf,mt,mg", 0x4440, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 }, 1150 {"xor", "mf,mg,mx", 0x4440, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 }, 1303 {"append", "t,s,h", 0x00000215, 0xfc0007ff, MOD_1|RD_2, 0, 0, D33, 0 }, [all …]
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H A D | mips-opc.c | 239 #define MOD_1 (WR_1|RD_1) macro 1832 {"sc", "t,+j(b)", 0x7c000026, 0xfc00007f, MOD_1|RD_3|SM, 0, I37, 0, 0 }, 2882 {"sldi.b", "+d,+e+o", 0x78000019, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, 2883 {"sldi.h", "+d,+e+u", 0x78200019, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 }, 2884 {"sldi.w", "+d,+e+v", 0x78300019, 0xfffc003f, MOD_1|RD_2, 0, 0, MSA, 0 }, 2885 {"sldi.d", "+d,+e+w", 0x78380019, 0xfffe003f, MOD_1|RD_2, 0, 0, MSA, 0 }, 3206 {"dahi", "s,-d,u", 0x04060000, 0xfc1f0000, MOD_1, 0, I69, 0, 0 }, 3207 {"dati", "s,-d,u", 0x041e0000, 0xfc1f0000, MOD_1, 0, I69, 0, 0 }, 3319 {"crc32b", "t,s,-d", 0x7c00000f, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC, 0 }, 3320 {"crc32h", "t,s,-d", 0x7c00004f, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC, 0 }, [all …]
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H A D | ChangeLog-2013 | 342 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI): 348 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): 358 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
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/dports/devel/gdb/gdb-11.1/opcodes/ |
H A D | mips16-opc.c | 171 #define MOD_1 (WR_1|RD_1) macro 217 {"addiu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 }, 227 {"addu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 }, 270 {"daddiu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 }, 277 {"daddu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 }, 304 {"dsra", "y,]", 0xe813, 0xf81f, MOD_1, 0, I3, 0, 0 }, 307 {"dsrl", "y,]", 0xe808, 0xf81f, MOD_1, 0, I3, 0, 0 }, 451 {"seb", "x", 0xe891, 0xf8ff, MOD_1, SH, I32, 0, 0 }, 452 {"seh", "x", 0xe8b1, 0xf8ff, MOD_1, SH, I32, 0, 0 }, 453 {"sew", "x", 0xe8d1, 0xf8ff, MOD_1, SH, I64, 0, 0 }, [all …]
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H A D | micromips-opc.c | 217 #define MOD_1 (WR_1|RD_1) macro 342 {"addius5", "mp,mX", 0x4c00, 0xfc01, MOD_1, 0, I1, 0, 0 }, 349 {"and", "mf,mt,mg", 0x4480, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 }, 350 {"and", "mf,mg,mx", 0x4480, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 }, 937 {"or", "mf,mt,mg", 0x44c0, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 }, 938 {"or", "mf,mg,mx", 0x44c0, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 }, 978 {"sc", "t,~(b)", 0x6000b000, 0xfc00f000, MOD_1|RD_3|SM, 0, I1, 0, 0 }, 1149 {"xor", "mf,mt,mg", 0x4440, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 }, 1150 {"xor", "mf,mg,mx", 0x4440, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 }, 1303 {"append", "t,s,h", 0x00000215, 0xfc0007ff, MOD_1|RD_2, 0, 0, D33, 0 }, [all …]
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H A D | mips-opc.c | 239 #define MOD_1 (WR_1|RD_1) macro 1832 {"sc", "t,+j(b)", 0x7c000026, 0xfc00007f, MOD_1|RD_3|SM, 0, I37, 0, 0 }, 2882 {"sldi.b", "+d,+e+o", 0x78000019, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, 2883 {"sldi.h", "+d,+e+u", 0x78200019, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 }, 2884 {"sldi.w", "+d,+e+v", 0x78300019, 0xfffc003f, MOD_1|RD_2, 0, 0, MSA, 0 }, 2885 {"sldi.d", "+d,+e+w", 0x78380019, 0xfffe003f, MOD_1|RD_2, 0, 0, MSA, 0 }, 3206 {"dahi", "s,-d,u", 0x04060000, 0xfc1f0000, MOD_1, 0, I69, 0, 0 }, 3207 {"dati", "s,-d,u", 0x041e0000, 0xfc1f0000, MOD_1, 0, I69, 0, 0 }, 3319 {"crc32b", "t,s,-d", 0x7c00000f, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC, 0 }, 3320 {"crc32h", "t,s,-d", 0x7c00004f, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC, 0 }, [all …]
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H A D | ChangeLog-2013 | 342 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI): 348 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): 358 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
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/dports/devel/gnulibiberty/binutils-2.37/opcodes/ |
H A D | mips16-opc.c | 171 #define MOD_1 (WR_1|RD_1) macro 217 {"addiu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 }, 227 {"addu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 }, 270 {"daddiu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 }, 277 {"daddu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 }, 304 {"dsra", "y,]", 0xe813, 0xf81f, MOD_1, 0, I3, 0, 0 }, 307 {"dsrl", "y,]", 0xe808, 0xf81f, MOD_1, 0, I3, 0, 0 }, 451 {"seb", "x", 0xe891, 0xf8ff, MOD_1, SH, I32, 0, 0 }, 452 {"seh", "x", 0xe8b1, 0xf8ff, MOD_1, SH, I32, 0, 0 }, 453 {"sew", "x", 0xe8d1, 0xf8ff, MOD_1, SH, I64, 0, 0 }, [all …]
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H A D | micromips-opc.c | 217 #define MOD_1 (WR_1|RD_1) macro 342 {"addius5", "mp,mX", 0x4c00, 0xfc01, MOD_1, 0, I1, 0, 0 }, 349 {"and", "mf,mt,mg", 0x4480, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 }, 350 {"and", "mf,mg,mx", 0x4480, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 }, 937 {"or", "mf,mt,mg", 0x44c0, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 }, 938 {"or", "mf,mg,mx", 0x44c0, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 }, 978 {"sc", "t,~(b)", 0x6000b000, 0xfc00f000, MOD_1|RD_3|SM, 0, I1, 0, 0 }, 1149 {"xor", "mf,mt,mg", 0x4440, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 }, 1150 {"xor", "mf,mg,mx", 0x4440, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 }, 1303 {"append", "t,s,h", 0x00000215, 0xfc0007ff, MOD_1|RD_2, 0, 0, D33, 0 }, [all …]
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H A D | mips-opc.c | 239 #define MOD_1 (WR_1|RD_1) macro 1832 {"sc", "t,+j(b)", 0x7c000026, 0xfc00007f, MOD_1|RD_3|SM, 0, I37, 0, 0 }, 2882 {"sldi.b", "+d,+e+o", 0x78000019, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, 2883 {"sldi.h", "+d,+e+u", 0x78200019, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 }, 2884 {"sldi.w", "+d,+e+v", 0x78300019, 0xfffc003f, MOD_1|RD_2, 0, 0, MSA, 0 }, 2885 {"sldi.d", "+d,+e+w", 0x78380019, 0xfffe003f, MOD_1|RD_2, 0, 0, MSA, 0 }, 3206 {"dahi", "s,-d,u", 0x04060000, 0xfc1f0000, MOD_1, 0, I69, 0, 0 }, 3207 {"dati", "s,-d,u", 0x041e0000, 0xfc1f0000, MOD_1, 0, I69, 0, 0 }, 3319 {"crc32b", "t,s,-d", 0x7c00000f, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC, 0 }, 3320 {"crc32h", "t,s,-d", 0x7c00004f, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC, 0 }, [all …]
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H A D | ChangeLog-2013 | 342 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI): 348 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): 358 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
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/dports/devel/binutils/binutils-2.37/opcodes/ |
H A D | mips16-opc.c | 171 #define MOD_1 (WR_1|RD_1) macro 217 {"addiu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 }, 227 {"addu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 }, 270 {"daddiu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 }, 277 {"daddu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 }, 304 {"dsra", "y,]", 0xe813, 0xf81f, MOD_1, 0, I3, 0, 0 }, 307 {"dsrl", "y,]", 0xe808, 0xf81f, MOD_1, 0, I3, 0, 0 }, 451 {"seb", "x", 0xe891, 0xf8ff, MOD_1, SH, I32, 0, 0 }, 452 {"seh", "x", 0xe8b1, 0xf8ff, MOD_1, SH, I32, 0, 0 }, 453 {"sew", "x", 0xe8d1, 0xf8ff, MOD_1, SH, I64, 0, 0 }, [all …]
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H A D | micromips-opc.c | 217 #define MOD_1 (WR_1|RD_1) macro 342 {"addius5", "mp,mX", 0x4c00, 0xfc01, MOD_1, 0, I1, 0, 0 }, 349 {"and", "mf,mt,mg", 0x4480, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 }, 350 {"and", "mf,mg,mx", 0x4480, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 }, 937 {"or", "mf,mt,mg", 0x44c0, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 }, 938 {"or", "mf,mg,mx", 0x44c0, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 }, 978 {"sc", "t,~(b)", 0x6000b000, 0xfc00f000, MOD_1|RD_3|SM, 0, I1, 0, 0 }, 1149 {"xor", "mf,mt,mg", 0x4440, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 }, 1150 {"xor", "mf,mg,mx", 0x4440, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 }, 1303 {"append", "t,s,h", 0x00000215, 0xfc0007ff, MOD_1|RD_2, 0, 0, D33, 0 }, [all …]
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H A D | mips-opc.c | 239 #define MOD_1 (WR_1|RD_1) macro 1832 {"sc", "t,+j(b)", 0x7c000026, 0xfc00007f, MOD_1|RD_3|SM, 0, I37, 0, 0 }, 2882 {"sldi.b", "+d,+e+o", 0x78000019, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, 2883 {"sldi.h", "+d,+e+u", 0x78200019, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 }, 2884 {"sldi.w", "+d,+e+v", 0x78300019, 0xfffc003f, MOD_1|RD_2, 0, 0, MSA, 0 }, 2885 {"sldi.d", "+d,+e+w", 0x78380019, 0xfffe003f, MOD_1|RD_2, 0, 0, MSA, 0 }, 3206 {"dahi", "s,-d,u", 0x04060000, 0xfc1f0000, MOD_1, 0, I69, 0, 0 }, 3207 {"dati", "s,-d,u", 0x041e0000, 0xfc1f0000, MOD_1, 0, I69, 0, 0 }, 3319 {"crc32b", "t,s,-d", 0x7c00000f, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC, 0 }, 3320 {"crc32h", "t,s,-d", 0x7c00004f, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC, 0 }, [all …]
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H A D | ChangeLog-2013 | 342 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI): 348 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): 358 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
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/dports/games/libretro-paralleln64/parallel-n64-6e26fbb/glide2gl/src/Glide64/ |
H A D | Combine.c | 65 #define MOD_1(mode) cmb.mod_1 = mode macro 2496 MOD_1 (TMOD_TEX_MUL_COL); in cc__t0_add__t1_mul_scale__mul_env_sub_center_add_prim() 5013 MOD_1 (TMOD_COL_INTER_COL1_USING_TEX); in cc_prim_sub_env_mul_t1_add_env_mul_t0() 9115 MOD_1 (TMOD_TEX_SUB_COL); in ac_t1_sub_prim_mul_shade_add_prim() 9931 MOD_1 (TMOD_TEX_SCALE_FAC_ADD_FAC); in ac__t1_sub_one_mul_enva_add_t0__mul_prim()
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