1 /* mips16-opc.c.  Mips16 opcode table.
2    Copyright (C) 1996-2016 Free Software Foundation, Inc.
3    Contributed by Ian Lance Taylor, Cygnus Support
4 
5    This file is part of the GNU opcodes library.
6 
7    This library is free software; you can redistribute it and/or modify
8    it under the terms of the GNU General Public License as published by
9    the Free Software Foundation; either version 3, or (at your option)
10    any later version.
11 
12    It is distributed in the hope that it will be useful, but WITHOUT
13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15    License for more details.
16 
17    You should have received a copy of the GNU General Public License
18    along with this file; see the file COPYING.  If not, write to the
19    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20    MA 02110-1301, USA.  */
21 
22 #include "sysdep.h"
23 #include <stdio.h>
24 #include "opcode/mips.h"
25 #include "mips-formats.h"
26 
27 static unsigned char reg_0_map[] = { 0 };
28 static unsigned char reg_29_map[] = { 29 };
29 static unsigned char reg_31_map[] = { 31 };
30 static unsigned char reg_m16_map[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
31 static unsigned char reg32r_map[] = {
32   0, 8, 16, 24,
33   1, 9, 17, 25,
34   2, 10, 18, 26,
35   3, 11, 19, 27,
36   4, 12, 20, 28,
37   5, 13, 21, 29,
38   6, 14, 22, 30,
39   7, 15, 23, 31
40 };
41 
42 /* Return the meaning of operand character TYPE, or null if it isn't
43    recognized.  If the operand is affected by the EXTEND instruction,
44    EXTENDED_P selects between the extended and unextended forms.
45    The extended forms all have an lsb of 0.  */
46 
47 const struct mips_operand *
decode_mips16_operand(char type,bfd_boolean extended_p)48 decode_mips16_operand (char type, bfd_boolean extended_p)
49 {
50   switch (type)
51     {
52     case '0': MAPPED_REG (0, 0, GP, reg_0_map);
53 
54     case 'L': SPECIAL (6, 5, ENTRY_EXIT_LIST);
55     case 'M': SPECIAL (7, 0, SAVE_RESTORE_LIST);
56     case 'P': SPECIAL (0, 0, PC);
57     case 'R': MAPPED_REG (0, 0, GP, reg_31_map);
58     case 'S': MAPPED_REG (0, 0, GP, reg_29_map);
59     case 'X': REG (5, 0, GP);
60     case 'Y': MAPPED_REG (5, 3, GP, reg32r_map);
61     case 'Z': MAPPED_REG (3, 0, GP, reg_m16_map);
62 
63     case 'a': JUMP (26, 0, 2);
64     case 'e': UINT (11, 0);
65     case 'i': JALX (26, 0, 2);
66     case 'l': SPECIAL (6, 5, ENTRY_EXIT_LIST);
67     case 'm': SPECIAL (7, 0, SAVE_RESTORE_LIST);
68     case 'v': OPTIONAL_MAPPED_REG (3, 8, GP, reg_m16_map);
69     case 'w': OPTIONAL_MAPPED_REG (3, 5, GP, reg_m16_map);
70     case 'x': MAPPED_REG (3, 8, GP, reg_m16_map);
71     case 'y': MAPPED_REG (3, 5, GP, reg_m16_map);
72     case 'z': MAPPED_REG (3, 2, GP, reg_m16_map);
73     }
74 
75   if (extended_p)
76     switch (type)
77       {
78       case '<': UINT (5, 0);
79       case '>': UINT (5, 0);
80       case '[': UINT (6, 0);
81       case ']': UINT (6, 0);
82 
83       case '4': SINT (15, 0);
84       case '5': SINT (16, 0);
85       case '6': SINT (16, 0);
86       case '8': SINT (16, 0);
87 
88       case 'A': PCREL (16, 0, TRUE, 0, 2, FALSE, FALSE);
89       case 'B': PCREL (16, 0, TRUE, 0, 3, FALSE, FALSE);
90       case 'C': SINT (16, 0);
91       case 'D': SINT (16, 0);
92       case 'E': PCREL (16, 0, TRUE, 0, 2, FALSE, FALSE);
93       case 'H': SINT (16, 0);
94       case 'K': SINT (16, 0);
95       case 'U': UINT (16, 0);
96       case 'V': SINT (16, 0);
97       case 'W': SINT (16, 0);
98 
99       case 'j': SINT (16, 0);
100       case 'k': SINT (16, 0);
101       case 'p': BRANCH (16, 0, 1);
102       case 'q': BRANCH (16, 0, 1);
103       }
104   else
105     switch (type)
106       {
107       case '<': INT_ADJ (3, 2, 8, 0, FALSE);
108       case '>': INT_ADJ (3, 8, 8, 0, FALSE);
109       case '[': INT_ADJ (3, 2, 8, 0, FALSE);
110       case ']': INT_ADJ (3, 8, 8, 0, FALSE);
111 
112       case '4': SINT (4, 0);
113       case '5': UINT (5, 0);
114       case '6': UINT (6, 5);
115       case '8': UINT (8, 0);
116 
117       case 'A': PCREL (8, 0, FALSE, 2, 2, FALSE, FALSE);
118       case 'B': PCREL (5, 0, FALSE, 3, 3, FALSE, FALSE);
119       case 'C': INT_ADJ (8, 0, 255, 3, FALSE);	/* (0 .. 255) << 3 */
120       case 'D': INT_ADJ (5, 0, 31, 3, FALSE);	/* (0 .. 31) << 3 */
121       case 'E': PCREL (5, 0, FALSE, 2, 2, FALSE, FALSE);
122       case 'H': INT_ADJ (5, 0, 31, 1, FALSE);	/* (0 .. 31) << 1 */
123       case 'K': INT_ADJ (8, 0, 127, 3, FALSE);	/* (-128 .. 127) << 3 */
124       case 'U': UINT (8, 0);
125       case 'V': INT_ADJ (8, 0, 255, 2, FALSE);	/* (0 .. 255) << 2 */
126       case 'W': INT_ADJ (5, 0, 31, 2, FALSE);	/* (0 .. 31) << 2 */
127 
128       case 'j': SINT (5, 0);
129       case 'k': SINT (8, 0);
130       case 'p': BRANCH (8, 0, 1);
131       case 'q': BRANCH (11, 0, 1);
132       }
133   return 0;
134 }
135 
136 /* This is the opcodes table for the mips16 processor.  The format of
137    this table is intentionally identical to the one in mips-opc.c.
138    However, the special letters that appear in the argument string are
139    different, and the table uses some different flags.  */
140 
141 /* Use some short hand macros to keep down the length of the lines in
142    the opcodes table.  */
143 
144 #define UBD     INSN_UNCOND_BRANCH_DELAY
145 
146 #define WR_1	INSN_WRITE_1
147 #define WR_2	INSN_WRITE_2
148 #define RD_1	INSN_READ_1
149 #define RD_2	INSN_READ_2
150 #define RD_3	INSN_READ_3
151 #define RD_4	INSN_READ_4
152 #define MOD_1	(WR_1|RD_1)
153 #define MOD_2	(WR_2|RD_2)
154 
155 #define RD_T	INSN_READ_GPR_24
156 #define WR_T	INSN_WRITE_GPR_24
157 #define WR_31	INSN_WRITE_GPR_31
158 
159 #define WR_HI	INSN_WRITE_HI
160 #define WR_LO	INSN_WRITE_LO
161 #define RD_HI	INSN_READ_HI
162 #define RD_LO	INSN_READ_LO
163 
164 #define NODS	INSN_NO_DELAY_SLOT
165 #define TRAP	INSN_NO_DELAY_SLOT
166 
167 #define RD_16	INSN2_READ_GPR_16
168 #define RD_SP	INSN2_READ_SP
169 #define WR_SP	INSN2_WRITE_SP
170 #define MOD_SP	(RD_SP|WR_SP)
171 #define RD_31	INSN2_READ_GPR_31
172 #define RD_PC	INSN2_READ_PC
173 #define UBR	INSN2_UNCOND_BRANCH
174 #define CBR	INSN2_COND_BRANCH
175 
176 #define I1	INSN_ISA1
177 #define I3	INSN_ISA3
178 #define I32	INSN_ISA32
179 #define I64	INSN_ISA64
180 #define T3	INSN_3900
181 
182 const struct mips_opcode mips16_opcodes[] =
183 {
184 /* name,    args,	match,	mask,		pinfo,	         	pinfo2, membership */
185 {"nop",	    "",		0x6500, 0xffff,		0,			RD_16,		I1,	0,	0 }, /* move $0,$Z */
186 {"la",	    "x,A",	0x0800, 0xf800,		WR_1,			RD_PC,		I1,	0,	0 },
187 {"abs",	    "x,w",	0, (int) M_ABS,		INSN_MACRO,		0,		I1,	0,	0 },
188 {"addiu",   "y,x,4",	0x4000, 0xf810,		WR_1|RD_2,		0,		I1,	0,	0 },
189 {"addiu",   "x,k",	0x4800, 0xf800,		MOD_1,			0,		I1,	0,	0 },
190 {"addiu",   "S,K",	0x6300, 0xff00,		0,			MOD_SP,		I1,	0,	0 },
191 {"addiu",   "S,S,K",	0x6300, 0xff00,		0,			MOD_SP,		I1,	0,	0 },
192 {"addiu",   "x,P,V",	0x0800, 0xf800,		WR_1,			RD_PC,		I1,	0,	0 },
193 {"addiu",   "x,S,V",	0x0000, 0xf800,		WR_1,			RD_SP,		I1,	0,	0 },
194 {"addu",    "z,v,y",	0xe001, 0xf803,		WR_1|RD_2|RD_3,		0,		I1,	0,	0 },
195 {"addu",    "y,x,4",	0x4000, 0xf810,		WR_1|RD_2,		0,		I1,	0,	0 },
196 {"addu",    "x,k",	0x4800, 0xf800,		MOD_1,			0,		I1,	0,	0 },
197 {"addu",    "S,K",	0x6300, 0xff00,		0,			MOD_SP,		I1,	0,	0 },
198 {"addu",    "S,S,K",	0x6300, 0xff00,		0,			MOD_SP,		I1,	0,	0 },
199 {"addu",    "x,P,V",	0x0800, 0xf800,		WR_1,			RD_PC,		I1,	0,	0 },
200 {"addu",    "x,S,V",	0x0000, 0xf800,		WR_1,			RD_SP,		I1,	0,	0 },
201 {"and",	    "x,y",	0xe80c, 0xf81f,		MOD_1|RD_2,		0,		I1,	0,	0 },
202 {"b",	    "q",	0x1000, 0xf800,		0,			UBR,		I1,	0,	0 },
203 {"beq",	    "x,y,p",	0, (int) M_BEQ,		INSN_MACRO,		0,		I1,	0,	0 },
204 {"beq",     "x,I,p",	0, (int) M_BEQ_I,	INSN_MACRO,		0,		I1,	0,	0 },
205 {"beqz",    "x,p",	0x2000, 0xf800,		RD_1,			CBR,		I1,	0,	0 },
206 {"bge",	    "x,y,p",	0, (int) M_BGE,		INSN_MACRO,		0,		I1,	0,	0 },
207 {"bge",     "x,I,p",	0, (int) M_BGE_I,	INSN_MACRO,		0,		I1,	0,	0 },
208 {"bgeu",    "x,y,p",	0, (int) M_BGEU,	INSN_MACRO,		0,		I1,	0,	0 },
209 {"bgeu",    "x,I,p",	0, (int) M_BGEU_I,	INSN_MACRO,		0,		I1,	0,	0 },
210 {"bgt",	    "x,y,p",	0, (int) M_BGT,		INSN_MACRO,		0,		I1,	0,	0 },
211 {"bgt",     "x,I,p",	0, (int) M_BGT_I,	INSN_MACRO,		0,		I1,	0,	0 },
212 {"bgtu",    "x,y,p",	0, (int) M_BGTU,	INSN_MACRO,		0,		I1,	0,	0 },
213 {"bgtu",    "x,I,p",	0, (int) M_BGTU_I,	INSN_MACRO,		0,		I1,	0,	0 },
214 {"ble",	    "x,y,p",	0, (int) M_BLE,		INSN_MACRO,		0,		I1,	0,	0 },
215 {"ble",     "x,I,p",	0, (int) M_BLE_I,	INSN_MACRO,		0,		I1,	0,	0 },
216 {"bleu",    "x,y,p",	0, (int) M_BLEU,	INSN_MACRO,		0,		I1,	0,	0 },
217 {"bleu",    "x,I,p",	0, (int) M_BLEU_I,	INSN_MACRO,		0,		I1,	0,	0 },
218 {"blt",	    "x,y,p",	0, (int) M_BLT,		INSN_MACRO,		0,		I1,	0,	0 },
219 {"blt",     "x,I,p",	0, (int) M_BLT_I,	INSN_MACRO,		0,		I1,	0,	0 },
220 {"bltu",    "x,y,p",	0, (int) M_BLTU,	INSN_MACRO,		0,		I1,	0,	0 },
221 {"bltu",    "x,I,p",	0, (int) M_BLTU_I,	INSN_MACRO,		0,		I1,	0,	0 },
222 {"bne",	    "x,y,p",	0, (int) M_BNE,		INSN_MACRO,		0,		I1,	0,	0 },
223 {"bne",     "x,I,p",	0, (int) M_BNE_I,	INSN_MACRO,		0,		I1,	0,	0 },
224 {"bnez",    "x,p",	0x2800, 0xf800,		RD_1,			CBR,		I1,	0,	0 },
225 {"break",   "6",	0xe805, 0xf81f,		TRAP,			0,		I1,	0,	0 },
226 {"bteqz",   "p",	0x6000, 0xff00,		RD_T,			CBR,		I1,	0,	0 },
227 {"btnez",   "p",	0x6100, 0xff00,		RD_T,			CBR,		I1,	0,	0 },
228 {"cmpi",    "x,U",	0x7000, 0xf800,		RD_1|WR_T,		0,		I1,	0,	0 },
229 {"cmp",	    "x,y",	0xe80a, 0xf81f,		RD_1|RD_2|WR_T,		0,		I1,	0,	0 },
230 {"cmp",     "x,U",	0x7000, 0xf800,		RD_1|WR_T,		0,		I1,	0,	0 },
231 {"dla",	    "y,E",	0xfe00, 0xff00,		WR_1, 			RD_PC,		I3,	0,	0 },
232 {"daddiu",  "y,x,4",	0x4010, 0xf810,		WR_1|RD_2, 		0,		I3,	0,	0 },
233 {"daddiu",  "y,j",	0xfd00, 0xff00,		MOD_1,			0,		I3,	0,	0 },
234 {"daddiu",  "S,K",	0xfb00, 0xff00,		0,	 		MOD_SP,		I3,	0,	0 },
235 {"daddiu",  "S,S,K",	0xfb00, 0xff00,		0,	 		MOD_SP,		I3,	0,	0 },
236 {"daddiu",  "y,P,W",	0xfe00, 0xff00,		WR_1,	 		RD_PC,		I3,	0,	0 },
237 {"daddiu",  "y,S,W",	0xff00, 0xff00,		WR_1,			RD_SP,		I3,	0,	0 },
238 {"daddu",   "z,v,y",	0xe000, 0xf803,		WR_1|RD_2|RD_3, 	0,		I3,	0,	0 },
239 {"daddu",   "y,x,4",	0x4010, 0xf810,		WR_1|RD_2, 		0,		I3,	0,	0 },
240 {"daddu",   "y,j",	0xfd00, 0xff00,		MOD_1,			0,		I3,	0,	0 },
241 {"daddu",   "S,K",	0xfb00, 0xff00,		0,	 		MOD_SP,		I3,	0,	0 },
242 {"daddu",   "S,S,K",	0xfb00, 0xff00,		0,	 		MOD_SP,		I3,	0,	0 },
243 {"daddu",   "y,P,W",	0xfe00, 0xff00,		WR_1,	 		RD_PC,		I3,	0,	0 },
244 {"daddu",   "y,S,W",	0xff00, 0xff00,		WR_1,			RD_SP,		I3,	0,	0 },
245 {"ddiv",    "0,x,y",	0xe81e, 0xf81f,		RD_2|RD_3|WR_HI|WR_LO,	0,		I3,	0,	0 },
246 {"ddiv",    "z,v,y",	0, (int) M_DDIV_3,	INSN_MACRO,		0,		I1,	0,	0 },
247 {"ddivu",   "0,x,y",	0xe81f, 0xf81f,		RD_2|RD_3|WR_HI|WR_LO, 	0,		I3,	0,	0 },
248 {"ddivu",   "z,v,y",	0, (int) M_DDIVU_3,	INSN_MACRO,		0,		I1,	0,	0 },
249 {"div",     "0,x,y",	0xe81a, 0xf81f,		RD_2|RD_3|WR_HI|WR_LO,	0,		I1,	0,	0 },
250 {"div",     "z,v,y",	0, (int) M_DIV_3,	INSN_MACRO,		0,		I1,	0,	0 },
251 {"divu",    "0,x,y",	0xe81b, 0xf81f,		RD_2|RD_3|WR_HI|WR_LO,	0,		I1,	0,	0 },
252 {"divu",    "z,v,y",	0, (int) M_DIVU_3,	INSN_MACRO,		0,		I1,	0,	0 },
253 {"dmul",    "z,v,y",	0, (int) M_DMUL,	INSN_MACRO, 		0,		I3,	0,	0 },
254 {"dmult",   "x,y",	0xe81c, 0xf81f, 	RD_1|RD_2|WR_HI|WR_LO, 	0,		I3,	0,	0 },
255 {"dmultu",  "x,y",	0xe81d, 0xf81f, 	RD_1|RD_2|WR_HI|WR_LO, 	0,		I3,	0,	0 },
256 {"drem",    "0,x,y",	0xe81e, 0xf81f, 	RD_2|RD_3|WR_HI|WR_LO, 	0,		I3,	0,	0 },
257 {"drem",    "z,v,y",	0, (int) M_DREM_3,	INSN_MACRO,		0,		I1,	0,	0 },
258 {"dremu",   "0,x,y",	0xe81f, 0xf81f,		RD_2|RD_3|WR_HI|WR_LO, 	0,		I3,	0,	0 },
259 {"dremu",   "z,v,y",	0, (int) M_DREMU_3,	INSN_MACRO,		0,		I1,	0,	0 },
260 {"dsllv",   "y,x",	0xe814, 0xf81f,		MOD_1|RD_2, 	0,		I3,	0,	0 },
261 {"dsll",    "x,w,[",	0x3001, 0xf803,		WR_1|RD_2, 		0,		I3,	0,	0 },
262 {"dsll",    "y,x",	0xe814, 0xf81f,		MOD_1|RD_2, 	0,		I3,	0,	0 },
263 {"dsrav",   "y,x",	0xe817, 0xf81f,		MOD_1|RD_2, 	0,		I3,	0,	0 },
264 {"dsra",    "y,]",	0xe813, 0xf81f,		MOD_1,			0,		I3,	0,	0 },
265 {"dsra",    "y,x",	0xe817, 0xf81f,		MOD_1|RD_2, 	0,		I3,	0,	0 },
266 {"dsrlv",   "y,x",	0xe816, 0xf81f,		MOD_1|RD_2, 	0,		I3,	0,	0 },
267 {"dsrl",    "y,]",	0xe808, 0xf81f,		MOD_1,			0,		I3,	0,	0 },
268 {"dsrl",    "y,x",	0xe816, 0xf81f,		MOD_1|RD_2, 	0,		I3,	0,	0 },
269 {"dsubu",   "z,v,y",	0xe002, 0xf803,		WR_1|RD_2|RD_3, 	0,		I3,	0,	0 },
270 {"dsubu",   "y,x,I",	0, (int) M_DSUBU_I,	INSN_MACRO,		0,		I1,	0,	0 },
271 {"dsubu",   "y,I",	0, (int) M_DSUBU_I_2,	INSN_MACRO, 		0,		I1,	0,	0 },
272 {"exit",    "L",	0xed09, 0xff1f,		TRAP,			0,		I1,	0,	0 },
273 {"exit",    "L",	0xee09, 0xff1f,		TRAP,			0,		I1,	0,	0 },
274 {"exit",    "",		0xef09, 0xffff,		TRAP,			0,		I1,	0,	0 },
275 {"exit",    "L",	0xef09, 0xff1f,		TRAP,			0,		I1,	0,	0 },
276 {"entry",   "",		0xe809, 0xffff,		TRAP,			0,		I1,	0,	0 },
277 {"entry",   "l",	0xe809, 0xf81f,		TRAP,			0,		I1,	0,	0 },
278 {"extend",  "e",	0xf000, 0xf800,		0,			0,		I1,	0,	0 },
279 {"jalr",    "x",	0xe840, 0xf8ff,		RD_1|WR_31|UBD,		0,		I1,	0,	0 },
280 {"jalr",    "R,x",	0xe840, 0xf8ff,		RD_2|WR_31|UBD,		0,		I1,	0,	0 },
281 {"jal",     "x",	0xe840, 0xf8ff,		RD_1|WR_31|UBD,		0,		I1,	0,	0 },
282 {"jal",     "R,x",	0xe840, 0xf8ff,		RD_2|WR_31|UBD,		0,		I1,	0,	0 },
283 {"jal",	    "a",	0x1800, 0xfc00,		WR_31|UBD,		0,		I1,	0,	0 },
284 {"jalx",    "i",	0x1c00, 0xfc00,		WR_31|UBD,		0,		I1,	0,	0 },
285 {"jr",	    "x",	0xe800, 0xf8ff,		RD_1|UBD,		0,		I1,	0,	0 },
286 {"jr",	    "R",	0xe820, 0xffff,		UBD,			RD_31,		I1,	0,	0 },
287 {"j",	    "x",	0xe800, 0xf8ff,		RD_1|UBD,		0,		I1,	0,	0 },
288 {"j",	    "R",	0xe820, 0xffff,		UBD,			RD_31,		I1,	0,	0 },
289 /* MIPS16e compact branches.  We keep them near the ordinary branches
290    so that we easily find them when converting a normal branch to a
291    compact one.  */
292 {"jalrc",   "x",	0xe8c0, 0xf8ff,		RD_1|WR_31|NODS,	UBR,		I32,	0,	0 },
293 {"jalrc",   "R,x",	0xe8c0, 0xf8ff,		RD_2|WR_31|NODS,	UBR,		I32,	0,	0 },
294 {"jrc",	    "x",	0xe880, 0xf8ff,		RD_1|NODS,		UBR,		I32,	0,	0 },
295 {"jrc",	    "R",	0xe8a0, 0xffff,		NODS,			RD_31|UBR,	I32,	0,	0 },
296 {"lb",	    "y,5(x)",	0x8000, 0xf800,		WR_1|RD_3,		0,		I1,	0,	0 },
297 {"lbu",	    "y,5(x)",	0xa000, 0xf800,		WR_1|RD_3,		0,		I1,	0,	0 },
298 {"ld",	    "y,D(x)",	0x3800, 0xf800,		WR_1|RD_3, 		0,		I3,	0,	0 },
299 {"ld",	    "y,B",	0xfc00, 0xff00,		WR_1,	 		RD_PC,		I3,	0,	0 },
300 {"ld",	    "y,D(P)",	0xfc00, 0xff00,		WR_1,	 		RD_PC,		I3,	0,	0 },
301 {"ld",	    "y,D(S)",	0xf800, 0xff00,		WR_1,			RD_SP,		I3,	0,	0 },
302 {"lh",	    "y,H(x)",	0x8800, 0xf800,		WR_1|RD_3,		0,		I1,	0,	0 },
303 {"lhu",	    "y,H(x)",	0xa800, 0xf800,		WR_1|RD_3,		0,		I1,	0,	0 },
304 {"li",	    "x,U",	0x6800, 0xf800,		WR_1,			0,		I1,	0,	0 },
305 {"lw",	    "y,W(x)",	0x9800, 0xf800,		WR_1|RD_3,		0,		I1,	0,	0 },
306 {"lw",	    "x,A",	0xb000, 0xf800,		WR_1,			RD_PC,		I1,	0,	0 },
307 {"lw",	    "x,V(P)",	0xb000, 0xf800,		WR_1,			RD_PC,		I1,	0,	0 },
308 {"lw",	    "x,V(S)",	0x9000, 0xf800,		WR_1,			RD_SP,		I1,	0,	0 },
309 {"lwu",     "y,W(x)",	0xb800, 0xf800,		WR_1|RD_3, 		0,		I3,	0,	0 },
310 {"mfhi",    "x",	0xe810, 0xf8ff,		WR_1|RD_HI,		0,		I1,	0,	0 },
311 {"mflo",    "x",	0xe812, 0xf8ff,		WR_1|RD_LO,		0,		I1,	0,	0 },
312 {"move",    "y,X",	0x6700, 0xff00,		WR_1|RD_2, 		0,		I1,	0,	0 },
313 {"move",    "Y,Z",	0x6500, 0xff00,		WR_1|RD_2,		0,		I1,	0,	0 },
314 {"mul",     "z,v,y",	0, (int) M_MUL, 	INSN_MACRO,		0,		I1,	0,	0 },
315 {"mult",    "x,y",	0xe818, 0xf81f,		RD_1|RD_2|WR_HI|WR_LO,	0,		I1,	0,	0 },
316 {"multu",   "x,y",	0xe819, 0xf81f,		RD_1|RD_2|WR_HI|WR_LO,	0,		I1,	0,	0 },
317 {"neg",	    "x,w",	0xe80b, 0xf81f,		WR_1|RD_2,		0,		I1,	0,	0 },
318 {"not",	    "x,w",	0xe80f, 0xf81f,		WR_1|RD_2,		0,		I1,	0,	0 },
319 {"or",	    "x,y",	0xe80d, 0xf81f,		MOD_1|RD_2,		0,		I1,	0,	0 },
320 {"rem",     "0,x,y",	0xe81a, 0xf81f,		RD_2|RD_3|WR_HI|WR_LO,	0,		I1,	0,	0 },
321 {"rem",     "z,v,y",	0, (int) M_REM_3,	INSN_MACRO,		0,		I1,	0,	0 },
322 {"remu",    "0,x,y",	0xe81b, 0xf81f,		RD_2|RD_3|WR_HI|WR_LO,	0,		I1,	0,	0 },
323 {"remu",    "z,v,y",	0, (int) M_REMU_3,	INSN_MACRO,		0,		I1,	0,	0 },
324 {"sb",	    "y,5(x)",	0xc000, 0xf800,		RD_1|RD_3,		0,		I1,	0,	0 },
325 {"sd",	    "y,D(x)",	0x7800, 0xf800,		RD_1|RD_3, 		0,		I3,	0,	0 },
326 {"sd",	    "y,D(S)",	0xf900, 0xff00,		RD_1, 			RD_PC,		I3,	0,	0 },
327 {"sd",	    "R,C(S)",	0xfa00, 0xff00,		0,			RD_31|RD_PC,	I1,	0,	0 },
328 {"sh",	    "y,H(x)",	0xc800, 0xf800,		RD_1|RD_3,		0,		I1,	0,	0 },
329 {"sllv",    "y,x",	0xe804, 0xf81f,		MOD_1|RD_2, 	0,		I1,	0,	0 },
330 {"sll",	    "x,w,<",	0x3000, 0xf803,		WR_1|RD_2,		0,		I1,	0,	0 },
331 {"sll",     "y,x",	0xe804, 0xf81f,		MOD_1|RD_2,		0,		I1,	0,	0 },
332 {"slti",    "x,8",	0x5000, 0xf800,		RD_1|WR_T,		0,		I1,	0,	0 },
333 {"slt",	    "x,y",	0xe802, 0xf81f,		RD_1|RD_2|WR_T,		0,		I1,	0,	0 },
334 {"slt",     "x,8",	0x5000, 0xf800,		RD_1|WR_T,		0,		I1,	0,	0 },
335 {"sltiu",   "x,8",	0x5800, 0xf800,		RD_1|WR_T,		0,		I1,	0,	0 },
336 {"sltu",    "x,y",	0xe803, 0xf81f,		RD_1|RD_2|WR_T,		0,		I1,	0,	0 },
337 {"sltu",    "x,8",	0x5800, 0xf800,		RD_1|WR_T,		0,		I1,	0,	0 },
338 {"srav",    "y,x",	0xe807, 0xf81f,		MOD_1|RD_2,		0,		I1,	0,	0 },
339 {"sra",	    "x,w,<",	0x3003, 0xf803,		WR_1|RD_2,		0,		I1,	0,	0 },
340 {"sra",     "y,x",	0xe807, 0xf81f,		MOD_1|RD_2,		0,		I1,	0,	0 },
341 {"srlv",    "y,x",	0xe806, 0xf81f,		MOD_1|RD_2,		0,		I1,	0,	0 },
342 {"srl",	    "x,w,<",	0x3002, 0xf803,		WR_1|RD_2,		0,		I1,	0,	0 },
343 {"srl",     "y,x",	0xe806, 0xf81f,		MOD_1|RD_2,		0,		I1,	0,	0 },
344 {"subu",    "z,v,y",	0xe003, 0xf803,		WR_1|RD_2|RD_3,		0,		I1,	0,	0 },
345 {"subu",    "y,x,I",	0, (int) M_SUBU_I,	INSN_MACRO,		0,		I1,	0,	0 },
346 {"subu",    "x,I",	0, (int) M_SUBU_I_2,	INSN_MACRO,		0,		I1,	0,	0 },
347 {"sw",	    "y,W(x)",	0xd800, 0xf800,		RD_1|RD_3,		0,		I1,	0,	0 },
348 {"sw",	    "x,V(S)",	0xd000, 0xf800,		RD_1,			RD_SP,		I1,	0,	0 },
349 {"sw",	    "R,V(S)",	0x6200, 0xff00,		0,			RD_31|RD_SP,	I1,	0,	0 },
350 {"xor",	    "x,y",	0xe80e, 0xf81f,		MOD_1|RD_2, 	0,		I1,	0,	0 },
351   /* MIPS16e additions */
352 {"restore", "M",	0x6400, 0xff80,		WR_31|NODS,		MOD_SP,		I32,	0,	0 },
353 {"save",    "m",	0x6480, 0xff80,		NODS,			RD_31|MOD_SP,	I32,	0,	0 },
354 {"sdbbp",   "6",	0xe801, 0xf81f,		TRAP,			0,		I32,	0,	0 },
355 {"seb",	    "x",	0xe891, 0xf8ff,		MOD_1,			0,		I32,	0,	0 },
356 {"seh",	    "x",	0xe8b1, 0xf8ff,		MOD_1,			0,		I32,	0,	0 },
357 {"sew",	    "x",	0xe8d1, 0xf8ff,		MOD_1,			0,		I64,	0,	0 },
358 {"zeb",	    "x",	0xe811, 0xf8ff,		MOD_1,			0,		I32,	0,	0 },
359 {"zeh",	    "x",	0xe831, 0xf8ff,		MOD_1,			0,		I32,	0,	0 },
360 {"zew",	    "x",	0xe851, 0xf8ff,		MOD_1,			0,		I64,	0,	0 },
361 };
362 
363 const int bfd_mips16_num_opcodes =
364   ((sizeof mips16_opcodes) / (sizeof (mips16_opcodes[0])));
365