/dports/emulators/ppsspp-qt5/ppsspp-1.12.3/ext/armips/Archs/MIPS/ |
H A D | MipsOpcodes.cpp | 67 { "lq", "t,(s)", MIPS_OP(0x1E), MA_PS2, MO_DELAYRT|MO_IGNORERTD }, 69 { "sq", "t,(s)", MIPS_OP(0x1F), MA_PS2, MO_DELAYRT|MO_IGNORERTD }, 71 { "lb", "t,(s)", MIPS_OP(0x20), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD }, 84 { "lwu", "t,i16(s)", MIPS_OP(0x27), MA_MIPS3, MO_64BIT|MO_DELAYRT }, 85 { "lwu", "t,(s)", MIPS_OP(0x27), MA_MIPS3, MO_64BIT|MO_DELAYRT }, 113 { "lld", "t,(s)", MIPS_OP(0x34), MA_MIPS3, MO_64BIT|MO_DELAYRT }, 126 { "lqc2", "Vt,i16(s)", MIPS_OP(0x36), MA_PS2, MO_DELAYRT }, 128 { "ld", "t,(s)", MIPS_OP(0x37), MA_MIPS3, MO_64BIT|MO_DELAYRT }, 140 { "scd", "t,(s)", MIPS_OP(0x3C), MA_MIPS3, MO_64BIT|MO_DELAYRT }, 155 { "sqc2", "Vt,i16(s)", MIPS_OP(0x3E), MA_PS2, MO_DELAYRT }, [all …]
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H A D | MipsOpcodes.h | 26 #define MO_DELAYRT 0x00000080 // rt won't be available for one instruction macro
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H A D | CMipsInstruction.cpp | 246 Mips.SetLoadDelay(opcodeData.opcode.flags & MO_DELAYRT ? true : false,registerData.grt.num); in Validate()
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/dports/emulators/ppsspp/ppsspp-1.12.3/ext/armips/Archs/MIPS/ |
H A D | MipsOpcodes.cpp | 67 { "lq", "t,(s)", MIPS_OP(0x1E), MA_PS2, MO_DELAYRT|MO_IGNORERTD }, 69 { "sq", "t,(s)", MIPS_OP(0x1F), MA_PS2, MO_DELAYRT|MO_IGNORERTD }, 71 { "lb", "t,(s)", MIPS_OP(0x20), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD }, 84 { "lwu", "t,i16(s)", MIPS_OP(0x27), MA_MIPS3, MO_64BIT|MO_DELAYRT }, 85 { "lwu", "t,(s)", MIPS_OP(0x27), MA_MIPS3, MO_64BIT|MO_DELAYRT }, 113 { "lld", "t,(s)", MIPS_OP(0x34), MA_MIPS3, MO_64BIT|MO_DELAYRT }, 126 { "lqc2", "Vt,i16(s)", MIPS_OP(0x36), MA_PS2, MO_DELAYRT }, 128 { "ld", "t,(s)", MIPS_OP(0x37), MA_MIPS3, MO_64BIT|MO_DELAYRT }, 140 { "scd", "t,(s)", MIPS_OP(0x3C), MA_MIPS3, MO_64BIT|MO_DELAYRT }, 155 { "sqc2", "Vt,i16(s)", MIPS_OP(0x3E), MA_PS2, MO_DELAYRT }, [all …]
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H A D | MipsOpcodes.h | 26 #define MO_DELAYRT 0x00000080 // rt won't be available for one instruction macro
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H A D | CMipsInstruction.cpp | 246 Mips.SetLoadDelay(opcodeData.opcode.flags & MO_DELAYRT ? true : false,registerData.grt.num); in Validate()
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/dports/emulators/libretro-ppsspp/ppsspp-1.12.3/ext/armips/Archs/MIPS/ |
H A D | MipsOpcodes.cpp | 67 { "lq", "t,(s)", MIPS_OP(0x1E), MA_PS2, MO_DELAYRT|MO_IGNORERTD }, 69 { "sq", "t,(s)", MIPS_OP(0x1F), MA_PS2, MO_DELAYRT|MO_IGNORERTD }, 71 { "lb", "t,(s)", MIPS_OP(0x20), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD }, 84 { "lwu", "t,i16(s)", MIPS_OP(0x27), MA_MIPS3, MO_64BIT|MO_DELAYRT }, 85 { "lwu", "t,(s)", MIPS_OP(0x27), MA_MIPS3, MO_64BIT|MO_DELAYRT }, 113 { "lld", "t,(s)", MIPS_OP(0x34), MA_MIPS3, MO_64BIT|MO_DELAYRT }, 126 { "lqc2", "Vt,i16(s)", MIPS_OP(0x36), MA_PS2, MO_DELAYRT }, 128 { "ld", "t,(s)", MIPS_OP(0x37), MA_MIPS3, MO_64BIT|MO_DELAYRT }, 140 { "scd", "t,(s)", MIPS_OP(0x3C), MA_MIPS3, MO_64BIT|MO_DELAYRT }, 155 { "sqc2", "Vt,i16(s)", MIPS_OP(0x3E), MA_PS2, MO_DELAYRT }, [all …]
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H A D | MipsOpcodes.h | 26 #define MO_DELAYRT 0x00000080 // rt won't be available for one instruction macro
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H A D | CMipsInstruction.cpp | 246 Mips.SetLoadDelay(opcodeData.opcode.flags & MO_DELAYRT ? true : false,registerData.grt.num); in Validate()
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