Searched refs:MTIMECMP_REG (Results 1 – 6 of 6) sorted by relevance
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/riscv/lib/ |
| H A D | sifive_clint.c | 20 #define MTIMECMP_REG(base, hart) ((ulong)(base) + 0x4000 + (hart) * 8) macro
51 writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart)); in riscv_set_timecmp()
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| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/riscv/lib/ |
| H A D | sifive_clint.c | 20 #define MTIMECMP_REG(base, hart) ((ulong)(base) + 0x4000 + (hart) * 8) macro
51 writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart)); in riscv_set_timecmp()
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| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/riscv/lib/ |
| H A D | sifive_clint.c | 20 #define MTIMECMP_REG(base, hart) ((ulong)(base) + 0x4000 + (hart) * 8) macro
51 writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart)); in riscv_set_timecmp()
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| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/riscv/lib/ |
| H A D | sifive_clint.c | 20 #define MTIMECMP_REG(base, hart) ((ulong)(base) + 0x4000 + (hart) * 8) macro
51 writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart)); in riscv_set_timecmp()
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| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/arch/riscv/lib/ |
| H A D | sifive_clint.c | 20 #define MTIMECMP_REG(base, hart) ((ulong)(base) + 0x4000 + (hart) * 8) macro
51 writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart)); in riscv_set_timecmp()
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| /dports/sysutils/u-boot-tools/u-boot-2020.07/arch/riscv/lib/ |
| H A D | sifive_clint.c | 21 #define MTIMECMP_REG(base, hart) ((ulong)(base) + 0x4000 + (hart) * 8) macro
52 writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart)); in riscv_set_timecmp()
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