1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
4  *
5  * U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT).
6  * The CLINT block holds memory-mapped control and status registers
7  * associated with software and timer interrupts.
8  */
9 
10 #include <common.h>
11 #include <dm.h>
12 #include <regmap.h>
13 #include <syscon.h>
14 #include <asm/io.h>
15 #include <asm/syscon.h>
16 #include <linux/err.h>
17 
18 /* MSIP registers */
19 #define MSIP_REG(base, hart)		((ulong)(base) + (hart) * 4)
20 /* mtime compare register */
21 #define MTIMECMP_REG(base, hart)	((ulong)(base) + 0x4000 + (hart) * 8)
22 /* mtime register */
23 #define MTIME_REG(base)			((ulong)(base) + 0xbff8)
24 
25 DECLARE_GLOBAL_DATA_PTR;
26 
27 #define CLINT_BASE_GET(void)						\
28 	do {								\
29 		long *ret;						\
30 									\
31 		if (!gd->arch.clint) {					\
32 			ret = syscon_get_first_range(RISCV_SYSCON_CLINT); \
33 			if (IS_ERR(ret))				\
34 				return PTR_ERR(ret);			\
35 			gd->arch.clint = ret;				\
36 		}							\
37 	} while (0)
38 
riscv_get_time(u64 * time)39 int riscv_get_time(u64 *time)
40 {
41 	CLINT_BASE_GET();
42 
43 	*time = readq((void __iomem *)MTIME_REG(gd->arch.clint));
44 
45 	return 0;
46 }
47 
riscv_set_timecmp(int hart,u64 cmp)48 int riscv_set_timecmp(int hart, u64 cmp)
49 {
50 	CLINT_BASE_GET();
51 
52 	writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart));
53 
54 	return 0;
55 }
56 
riscv_send_ipi(int hart)57 int riscv_send_ipi(int hart)
58 {
59 	CLINT_BASE_GET();
60 
61 	writel(1, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
62 
63 	return 0;
64 }
65 
riscv_clear_ipi(int hart)66 int riscv_clear_ipi(int hart)
67 {
68 	CLINT_BASE_GET();
69 
70 	writel(0, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
71 
72 	return 0;
73 }
74 
riscv_get_ipi(int hart,int * pending)75 int riscv_get_ipi(int hart, int *pending)
76 {
77 	CLINT_BASE_GET();
78 
79 	*pending = readl((void __iomem *)MSIP_REG(gd->arch.clint, hart));
80 
81 	return 0;
82 }
83 
84 static const struct udevice_id sifive_clint_ids[] = {
85 	{ .compatible = "riscv,clint0", .data = RISCV_SYSCON_CLINT },
86 	{ }
87 };
88 
89 U_BOOT_DRIVER(sifive_clint) = {
90 	.name		= "sifive_clint",
91 	.id		= UCLASS_SYSCON,
92 	.of_match	= sifive_clint_ids,
93 	.flags		= DM_FLAG_PRE_RELOC,
94 };
95