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Searched refs:NR_BYTES (Results 1 – 25 of 34) sorted by relevance

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/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/ppc/
H A Didecode_expression.h302 #define MEM(SIGN, EA, NR_BYTES) \ argument
303 ((SIGN##_##NR_BYTES) vm_data_map_read_##NR_BYTES(cpu_data_map(processor), EA, \
306 #define STORE(EA, NR_BYTES, VAL) \ argument
308 vm_data_map_write_##NR_BYTES(cpu_data_map(processor), EA, VAL, \
/dports/devel/avr-gdb/gdb-7.3.1/sim/ppc/
H A Didecode_expression.h302 #define MEM(SIGN, EA, NR_BYTES) \ argument
303 ((SIGN##_##NR_BYTES) vm_data_map_read_##NR_BYTES(cpu_data_map(processor), EA, \
306 #define STORE(EA, NR_BYTES, VAL) \ argument
308 vm_data_map_write_##NR_BYTES(cpu_data_map(processor), EA, VAL, \
/dports/devel/gdb761/gdb-7.6.1/sim/ppc/
H A Didecode_expression.h301 #define MEM(SIGN, EA, NR_BYTES) \ argument
302 ((SIGN##_##NR_BYTES) vm_data_map_read_##NR_BYTES(cpu_data_map(processor), EA, \
305 #define STORE(EA, NR_BYTES, VAL) \ argument
307 vm_data_map_write_##NR_BYTES(cpu_data_map(processor), EA, VAL, \
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/ppc/
H A Didecode_expression.h302 #define MEM(SIGN, EA, NR_BYTES) \ argument
303 ((SIGN##_##NR_BYTES) vm_data_map_read_##NR_BYTES(cpu_data_map(processor), EA, \
306 #define STORE(EA, NR_BYTES, VAL) \ argument
308 vm_data_map_write_##NR_BYTES(cpu_data_map(processor), EA, VAL, \
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/i960/
H A Dsim-main.h62 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ argument
63 i960_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
/dports/devel/avr-gdb/gdb-7.3.1/sim/sh64/
H A Dsim-main.h68 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ argument
69 sh64_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
/dports/devel/gdb761/gdb-7.6.1/sim/sh64/
H A Dsim-main.h68 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ argument
69 sh64_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/i960/
H A Dsim-main.h62 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ argument
63 i960_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
/dports/devel/avr-gdb/gdb-7.3.1/sim/lm32/
H A Dsim-main.h98 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ argument
99 lm32_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
/dports/devel/gdb761/gdb-7.6.1/sim/lm32/
H A Dsim-main.h98 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ argument
99 lm32_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
/dports/devel/avr-gdb/gdb-7.3.1/sim/iq2000/
H A Dsim-main.h72 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ argument
73 iq2000_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
/dports/devel/gdb761/gdb-7.6.1/sim/iq2000/
H A Dsim-main.h72 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ argument
73 iq2000_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/mn10300/
H A Dsim-main.h55 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ argument
56 mn10300_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/m32r/
H A Dsim-main.h83 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ argument
84 m32r_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
/dports/devel/avr-gdb/gdb-7.3.1/sim/m32r/
H A Dsim-main.h83 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ argument
84 m32r_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
/dports/devel/avr-gdb/gdb-7.3.1/sim/mn10300/
H A Dsim-main.h54 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ argument
55 mn10300_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
/dports/devel/gdb761/gdb-7.6.1/sim/mn10300/
H A Dsim-main.h54 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ argument
55 mn10300_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
/dports/devel/gdb761/gdb-7.6.1/sim/m32r/
H A Dsim-main.h83 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ argument
84 m32r_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/m32r/
H A Dsim-main.h83 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ argument
84 m32r_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/mn10300/
H A Dsim-main.h55 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ argument
56 mn10300_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
/dports/devel/avr-gdb/gdb-7.3.1/sim/frv/
H A Dsim-main.h134 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ argument
135 frv_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
/dports/devel/gdb761/gdb-7.6.1/sim/frv/
H A Dsim-main.h133 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ argument
134 frv_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/frv/
H A Dsim-main.h134 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ argument
135 frv_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/frv/
H A Dsim-main.h134 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ argument
135 frv_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
/dports/devel/avr-gdb/gdb-7.3.1/sim/cris/
H A Dsim-main.h241 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ argument
242 cris_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \

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