| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/clk/at91/ |
| H A D | clk-master.c | 29 #define PMC_MCR 0x30 macro
176 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_parent()
188 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_enable()
199 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_disable()
200 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_disable()
227 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_set_rate()
228 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_rate()
246 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_get_rate()
247 pmc_read(master->base, PMC_MCR, &val); in clk_sama7g5_master_get_rate()
291 pmc_write(master->base, PMC_MCR, master->id); in at91_clk_sama7g5_register_master()
[all …]
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| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/clk/at91/ |
| H A D | clk-master.c | 29 #define PMC_MCR 0x30 macro
176 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_parent()
188 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_enable()
199 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_disable()
200 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_disable()
227 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_set_rate()
228 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_rate()
246 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_get_rate()
247 pmc_read(master->base, PMC_MCR, &val); in clk_sama7g5_master_get_rate()
291 pmc_write(master->base, PMC_MCR, master->id); in at91_clk_sama7g5_register_master()
[all …]
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| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/clk/at91/ |
| H A D | clk-master.c | 29 #define PMC_MCR 0x30 macro
176 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_parent()
188 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_enable()
199 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_disable()
200 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_disable()
227 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_set_rate()
228 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_rate()
246 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_get_rate()
247 pmc_read(master->base, PMC_MCR, &val); in clk_sama7g5_master_get_rate()
291 pmc_write(master->base, PMC_MCR, master->id); in at91_clk_sama7g5_register_master()
[all …]
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| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/clk/at91/ |
| H A D | clk-master.c | 29 #define PMC_MCR 0x30 macro
176 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_parent()
188 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_enable()
199 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_disable()
200 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_disable()
227 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_set_rate()
228 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_rate()
246 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_get_rate()
247 pmc_read(master->base, PMC_MCR, &val); in clk_sama7g5_master_get_rate()
291 pmc_write(master->base, PMC_MCR, master->id); in at91_clk_sama7g5_register_master()
[all …]
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| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/clk/at91/ |
| H A D | clk-master.c | 29 #define PMC_MCR 0x30 macro
176 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_parent()
188 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_enable()
199 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_disable()
200 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_disable()
227 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_set_rate()
228 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_rate()
246 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_get_rate()
247 pmc_read(master->base, PMC_MCR, &val); in clk_sama7g5_master_get_rate()
291 pmc_write(master->base, PMC_MCR, master->id); in at91_clk_sama7g5_register_master()
[all …]
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| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/clk/at91/ |
| H A D | clk-master.c | 29 #define PMC_MCR 0x30 macro
176 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_parent()
188 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_enable()
199 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_disable()
200 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_disable()
227 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_set_rate()
228 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_rate()
246 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_get_rate()
247 pmc_read(master->base, PMC_MCR, &val); in clk_sama7g5_master_get_rate()
291 pmc_write(master->base, PMC_MCR, master->id); in at91_clk_sama7g5_register_master()
[all …]
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| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/clk/at91/ |
| H A D | clk-master.c | 29 #define PMC_MCR 0x30 macro
176 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_parent()
188 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_enable()
199 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_disable()
200 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_disable()
227 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_set_rate()
228 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_rate()
246 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_get_rate()
247 pmc_read(master->base, PMC_MCR, &val); in clk_sama7g5_master_get_rate()
291 pmc_write(master->base, PMC_MCR, master->id); in at91_clk_sama7g5_register_master()
[all …]
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| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/clk/at91/ |
| H A D | clk-master.c | 29 #define PMC_MCR 0x30 macro
176 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_parent()
188 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_enable()
199 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_disable()
200 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_disable()
227 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_set_rate()
228 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_rate()
246 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_get_rate()
247 pmc_read(master->base, PMC_MCR, &val); in clk_sama7g5_master_get_rate()
291 pmc_write(master->base, PMC_MCR, master->id); in at91_clk_sama7g5_register_master()
[all …]
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| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/clk/at91/ |
| H A D | clk-master.c | 29 #define PMC_MCR 0x30 macro
176 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_parent()
188 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_enable()
199 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_disable()
200 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_disable()
227 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_set_rate()
228 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_rate()
246 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_get_rate()
247 pmc_read(master->base, PMC_MCR, &val); in clk_sama7g5_master_get_rate()
291 pmc_write(master->base, PMC_MCR, master->id); in at91_clk_sama7g5_register_master()
[all …]
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| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/clk/at91/ |
| H A D | clk-master.c | 29 #define PMC_MCR 0x30 macro
176 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_parent()
188 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_enable()
199 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_disable()
200 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_disable()
227 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_set_rate()
228 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_rate()
246 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_get_rate()
247 pmc_read(master->base, PMC_MCR, &val); in clk_sama7g5_master_get_rate()
291 pmc_write(master->base, PMC_MCR, master->id); in at91_clk_sama7g5_register_master()
[all …]
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| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/clk/at91/ |
| H A D | clk-master.c | 29 #define PMC_MCR 0x30 macro
176 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_parent()
188 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_enable()
199 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_disable()
200 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_disable()
227 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_set_rate()
228 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_rate()
246 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_get_rate()
247 pmc_read(master->base, PMC_MCR, &val); in clk_sama7g5_master_get_rate()
291 pmc_write(master->base, PMC_MCR, master->id); in at91_clk_sama7g5_register_master()
[all …]
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| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/clk/at91/ |
| H A D | clk-master.c | 29 #define PMC_MCR 0x30 macro
176 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_parent()
188 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_enable()
199 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_disable()
200 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_disable()
227 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_set_rate()
228 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_rate()
246 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_get_rate()
247 pmc_read(master->base, PMC_MCR, &val); in clk_sama7g5_master_get_rate()
291 pmc_write(master->base, PMC_MCR, master->id); in at91_clk_sama7g5_register_master()
[all …]
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| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/clk/at91/ |
| H A D | clk-master.c | 29 #define PMC_MCR 0x30 macro
176 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_parent()
188 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_enable()
199 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_disable()
200 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_disable()
227 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_set_rate()
228 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_rate()
246 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_get_rate()
247 pmc_read(master->base, PMC_MCR, &val); in clk_sama7g5_master_get_rate()
291 pmc_write(master->base, PMC_MCR, master->id); in at91_clk_sama7g5_register_master()
[all …]
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| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/clk/at91/ |
| H A D | clk-master.c | 29 #define PMC_MCR 0x30 macro
176 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_parent()
188 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_enable()
199 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_disable()
200 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_disable()
227 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_set_rate()
228 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_rate()
246 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_get_rate()
247 pmc_read(master->base, PMC_MCR, &val); in clk_sama7g5_master_get_rate()
291 pmc_write(master->base, PMC_MCR, master->id); in at91_clk_sama7g5_register_master()
[all …]
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| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/clk/at91/ |
| H A D | clk-master.c | 29 #define PMC_MCR 0x30 macro
176 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_parent()
188 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_enable()
199 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_disable()
200 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_disable()
227 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_set_rate()
228 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_rate()
246 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_get_rate()
247 pmc_read(master->base, PMC_MCR, &val); in clk_sama7g5_master_get_rate()
291 pmc_write(master->base, PMC_MCR, master->id); in at91_clk_sama7g5_register_master()
[all …]
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| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/clk/at91/ |
| H A D | clk-master.c | 29 #define PMC_MCR 0x30 macro
176 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_parent()
188 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_enable()
199 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_disable()
200 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_disable()
227 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_set_rate()
228 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_rate()
246 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_get_rate()
247 pmc_read(master->base, PMC_MCR, &val); in clk_sama7g5_master_get_rate()
291 pmc_write(master->base, PMC_MCR, master->id); in at91_clk_sama7g5_register_master()
[all …]
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| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/clk/at91/ |
| H A D | clk-master.c | 29 #define PMC_MCR 0x30 macro
176 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_parent()
188 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_enable()
199 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_disable()
200 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_disable()
227 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_set_rate()
228 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_rate()
246 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_get_rate()
247 pmc_read(master->base, PMC_MCR, &val); in clk_sama7g5_master_get_rate()
291 pmc_write(master->base, PMC_MCR, master->id); in at91_clk_sama7g5_register_master()
[all …]
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| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/clk/at91/ |
| H A D | clk-master.c | 29 #define PMC_MCR 0x30 macro
176 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_parent()
188 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_enable()
199 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_disable()
200 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_disable()
227 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_set_rate()
228 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_rate()
246 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_get_rate()
247 pmc_read(master->base, PMC_MCR, &val); in clk_sama7g5_master_get_rate()
291 pmc_write(master->base, PMC_MCR, master->id); in at91_clk_sama7g5_register_master()
[all …]
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| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/clk/at91/ |
| H A D | clk-master.c | 29 #define PMC_MCR 0x30 macro
176 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_parent()
188 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_enable()
199 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_disable()
200 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_disable()
227 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_set_rate()
228 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_rate()
246 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_get_rate()
247 pmc_read(master->base, PMC_MCR, &val); in clk_sama7g5_master_get_rate()
291 pmc_write(master->base, PMC_MCR, master->id); in at91_clk_sama7g5_register_master()
[all …]
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| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/clk/at91/ |
| H A D | clk-master.c | 29 #define PMC_MCR 0x30 macro
176 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_parent()
188 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_enable()
199 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_disable()
200 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_disable()
227 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_set_rate()
228 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_rate()
246 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_get_rate()
247 pmc_read(master->base, PMC_MCR, &val); in clk_sama7g5_master_get_rate()
291 pmc_write(master->base, PMC_MCR, master->id); in at91_clk_sama7g5_register_master()
[all …]
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| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/clk/at91/ |
| H A D | clk-master.c | 29 #define PMC_MCR 0x30 macro
176 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_parent()
188 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_enable()
199 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_disable()
200 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_disable()
227 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_set_rate()
228 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_rate()
246 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_get_rate()
247 pmc_read(master->base, PMC_MCR, &val); in clk_sama7g5_master_get_rate()
291 pmc_write(master->base, PMC_MCR, master->id); in at91_clk_sama7g5_register_master()
[all …]
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| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/clk/at91/ |
| H A D | clk-master.c | 29 #define PMC_MCR 0x30 macro
176 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_parent()
188 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_enable()
199 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_disable()
200 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_disable()
227 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_set_rate()
228 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_rate()
246 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_get_rate()
247 pmc_read(master->base, PMC_MCR, &val); in clk_sama7g5_master_get_rate()
291 pmc_write(master->base, PMC_MCR, master->id); in at91_clk_sama7g5_register_master()
[all …]
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| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/clk/at91/ |
| H A D | clk-master.c | 29 #define PMC_MCR 0x30 macro
176 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_parent()
188 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_enable()
199 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_disable()
200 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_disable()
227 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_set_rate()
228 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_rate()
246 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_get_rate()
247 pmc_read(master->base, PMC_MCR, &val); in clk_sama7g5_master_get_rate()
291 pmc_write(master->base, PMC_MCR, master->id); in at91_clk_sama7g5_register_master()
[all …]
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| /dports/sysutils/u-boot-pine64/u-boot-2021.07/drivers/clk/at91/ |
| H A D | clk-master.c | 29 #define PMC_MCR 0x30 macro
176 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_parent()
188 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_enable()
199 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_disable()
200 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_disable()
227 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_set_rate()
228 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_rate()
246 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_get_rate()
247 pmc_read(master->base, PMC_MCR, &val); in clk_sama7g5_master_get_rate()
291 pmc_write(master->base, PMC_MCR, master->id); in at91_clk_sama7g5_register_master()
[all …]
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| /dports/sysutils/u-boot-pine-h64/u-boot-2021.07/drivers/clk/at91/ |
| H A D | clk-master.c | 29 #define PMC_MCR 0x30 macro
176 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_parent()
188 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_enable()
199 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_disable()
200 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_disable()
227 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_set_rate()
228 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_rate()
246 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_get_rate()
247 pmc_read(master->base, PMC_MCR, &val); in clk_sama7g5_master_get_rate()
291 pmc_write(master->base, PMC_MCR, master->id); in at91_clk_sama7g5_register_master()
[all …]
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