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Searched refs:POST_CALL_TMP_REG (Results 1 – 25 of 54) sorted by relevance

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/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/config/mips/
H A Dmips.h2396 #define POST_CALL_TMP_REG \ macro
H A Dmips.c3109 rtx post_call_tmp_reg = gen_rtx_REG (word_mode, POST_CALL_TMP_REG); in mips_emit_call_insn()
7808 POST_CALL_TMP_REG)); in mips_split_call()
/dports/lang/gcc9/gcc-9.4.0/gcc/config/mips/
H A Dmips.h2452 #define POST_CALL_TMP_REG \ macro
H A Dmips.c3138 rtx post_call_tmp_reg = gen_rtx_REG (word_mode, POST_CALL_TMP_REG); in mips_emit_call_insn()
7864 POST_CALL_TMP_REG)); in mips_split_call()
/dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/config/mips/
H A Dmips.h2396 #define POST_CALL_TMP_REG \ macro
H A Dmips.c3109 rtx post_call_tmp_reg = gen_rtx_REG (word_mode, POST_CALL_TMP_REG); in mips_emit_call_insn()
7808 POST_CALL_TMP_REG)); in mips_split_call()
/dports/devel/avr-gcc/gcc-10.2.0/gcc/config/mips/
H A Dmips.h2429 #define POST_CALL_TMP_REG \ macro
H A Dmips.c3139 rtx post_call_tmp_reg = gen_rtx_REG (word_mode, POST_CALL_TMP_REG); in mips_emit_call_insn()
7860 POST_CALL_TMP_REG)); in mips_split_call()
/dports/lang/gnat_util/gcc-6-20180516/gcc/config/mips/
H A Dmips.h2388 #define POST_CALL_TMP_REG \ macro
H A Dmips.c2900 rtx post_call_tmp_reg = gen_rtx_REG (word_mode, POST_CALL_TMP_REG); in mips_emit_call_insn()
7345 POST_CALL_TMP_REG)); in mips_split_call()
/dports/lang/gcc11-devel/gcc-11-20211009/gcc/config/mips/
H A Dmips.h2430 #define POST_CALL_TMP_REG \ macro
H A Dmips.c3139 rtx post_call_tmp_reg = gen_rtx_REG (word_mode, POST_CALL_TMP_REG); in mips_emit_call_insn()
7860 POST_CALL_TMP_REG)); in mips_split_call()
/dports/lang/gcc10-devel/gcc-10-20211008/gcc/config/mips/
H A Dmips.h2429 #define POST_CALL_TMP_REG \ macro
/dports/lang/gcc12-devel/gcc-12-20211205/gcc/config/mips/
H A Dmips.h2448 #define POST_CALL_TMP_REG \ macro
/dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/config/mips/
H A Dmips.h2396 #define POST_CALL_TMP_REG \ macro
/dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/config/mips/
H A Dmips.h2396 #define POST_CALL_TMP_REG \ macro
/dports/devel/riscv64-gcc/gcc-8.3.0/gcc/config/mips/
H A Dmips.h2396 #define POST_CALL_TMP_REG \ macro
/dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/config/mips/
H A Dmips.h2430 #define POST_CALL_TMP_REG \ macro
/dports/lang/gcc9-aux/gcc-9.1.0/gcc/config/mips/
H A Dmips.h2452 #define POST_CALL_TMP_REG \ macro
/dports/lang/gcc10/gcc-10.3.0/gcc/config/mips/
H A Dmips.h2429 #define POST_CALL_TMP_REG \ macro
/dports/lang/gcc8/gcc-8.5.0/gcc/config/mips/
H A Dmips.h2396 #define POST_CALL_TMP_REG \ macro
/dports/lang/gcc11/gcc-11.2.0/gcc/config/mips/
H A Dmips.h2430 #define POST_CALL_TMP_REG \ macro
/dports/lang/gcc9-devel/gcc-9-20211007/gcc/config/mips/
H A Dmips.h2452 #define POST_CALL_TMP_REG \ macro
/dports/lang/gcc6-aux/gcc-6-20180516/gcc/config/mips/
H A Dmips.h2388 #define POST_CALL_TMP_REG \ macro
H A Dmips.c2900 rtx post_call_tmp_reg = gen_rtx_REG (word_mode, POST_CALL_TMP_REG); in mips_emit_call_insn()
7345 POST_CALL_TMP_REG)); in mips_split_call()

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