Searched refs:PrAcc (Results 1 – 6 of 6) sorted by relevance
75 #define PrAcc 18 /* R/W0 */ macro178 ejctrl->in->data[PrAcc] = 1; in ejtag_run_pracc()192 if (!ejctrl->out->data[PrAcc]) in ejtag_run_pracc()261 ejctrl->in->data[PrAcc] = 0; in ejtag_run_pracc()378 ejctrl->in->data[PrAcc] = 1; // 18----||| in ejtag_bus_init()426 ejctrl->in->data[PrAcc] = 1; // 18----|| in ejtag_bus_init()477 ejctrl->in->data[PrAcc] = 1; // 18 in ejtag_bus_init()493 ejctrl->in->data[PrAcc] = 1; // 18 in ejtag_bus_init()508 ejctrl->in->data[PrAcc] = 1; // 18----|| in ejtag_bus_init()527 ejctrl->in->data[PrAcc] = 1; in ejtag_bus_init()[all …]
66 #define PrAcc 18 macro206 ejctrl->in->data[PrAcc] = 1; // Processor access in ejtag_dma_write()222 ejctrl->in->data[PrAcc] = 1; in ejtag_dma_write()235 ejctrl->in->data[PrAcc] = 1; in ejtag_dma_write()278 ejctrl->in->data[PrAcc] = 1; // Processor access in ejtag_dma_read()295 ejctrl->in->data[PrAcc] = 1; in ejtag_dma_read()323 ejctrl->in->data[PrAcc] = 1; in ejtag_dma_read()467 ejctrl->in->data[PrAcc] = 1; in ejtag_dma_bus_init()
496 msgid "EJTAG compatible bus driver via PrAcc (JTAG part No. %d)\n"515 msgid "PrAcc bad alignment: addr=0x%08lx"520 msgid "%s(%d) PrAcc write: addr=0x%08lx data=0x%08lx\n"537 msgid "EJTAG compatible bus driver via PrAcc"
549 msgid "EJTAG compatible bus driver via PrAcc (JTAG part No. %d)\n"568 msgid "PrAcc bad alignment: addr=0x%08lx"573 msgid "%s(%d) PrAcc write: addr=0x%08lx data=0x%08lx\n"591 msgid "EJTAG compatible bus driver via PrAcc"
540 msgid "EJTAG compatible bus driver via PrAcc (JTAG part No. %d)\n"560 msgid "PrAcc bad alignment: addr=0x%08lx"565 msgid "%s(%d) PrAcc write: addr=0x%08lx data=0x%08lx\n"583 msgid "EJTAG compatible bus driver via PrAcc"
26711 …t word order loaded into memory. The EJTAG processor access data register (PrAcc) is little endian