1 /*
2 * EJTAG compatible bus driver via PrAcc
3 * Copyright (C) 2005, Marek Michalkiewicz
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
18 * 02111-1307, USA.
19 *
20 * Written by Marek Michalkiewicz <marekm@amelek.gda.pl>, 2005.
21 *
22 * Documentation:
23 * [1] MIPS Licensees, "MIPS EJTAG Debug Solution", 980818 Rev. 2.0.0
24 * [2] MIPS Technologies, Inc. "EJTAG Specification", 2001-02-15, Rev. 2.60
25 *
26 */
27
28 #include <sysdep.h>
29
30 #include <stdlib.h>
31 #include <stdint.h>
32 #include <string.h>
33
34 #include <urjtag/part.h>
35 #include <urjtag/bus.h>
36 #include <urjtag/chain.h>
37 #include <urjtag/bssignal.h>
38 #include <urjtag/tap_state.h>
39 #include <urjtag/tap_register.h>
40 #include <urjtag/data_register.h>
41
42 #include "buses.h"
43 #include "generic_bus.h"
44
45 typedef struct
46 {
47 uint32_t impcode; /* EJTAG Implementation Register */
48 uint16_t adr_hi; /* cached high bits of $3 */
49 } bus_params_t;
50
51 #define BP ((bus_params_t *) bus->params)
52
53 #define EJTAG_VER ((BP->impcode >> 29) & 7)
54
55 #define EJTAG_20 0
56 #define EJTAG_25 1
57 #define EJTAG_26 2
58 #define EJTAG_31 3
59
60 /* EJTAG 3.1 Control Register Bits */
61 #define VPED 23 /* R */
62 /* EJTAG 2.6 Control Register Bits */
63 #define Rocc 31 /* R/W0 */
64 #define Psz1 30 /* R */
65 #define Psz0 29 /* R */
66 #define Doze 22 /* R */
67 #define ProbTrap 14 /* R/W */
68 #define DebugMode 3 /* R */
69 /* EJTAG 1.5.3 Control Register Bits */
70 #define Dnm 28 /* */
71 #define Sync 23 /* R/W */
72 #define Run 21 /* R */
73 #define PerRst 20 /* R/W */
74 #define PRnW 19 /* R 0 = Read, 1 = Write */
75 #define PrAcc 18 /* R/W0 */
76 #define DmaAcc 17 /* R/W */
77 #define PrRst 16 /* R/W */
78 #define ProbEn 15 /* R/W */
79 #define SetDev 14 /* R */
80 #define JtagBrk 12 /* R/W1 */
81 #define DStrt 11 /* R/W1 */
82 #define DeRR 10 /* R */
83 #define DrWn 9 /* R/W */
84 #define Dsz1 8 /* R/W */
85 #define Dsz0 7 /* R/W */
86 #define DLock 5 /* R/W */
87 #define BrkSt 3 /* R */
88 #define TIF 2 /* W0/R */
89 #define TOF 1 /* W0/R */
90 #define ClkEn 0 /* R/W */
91
92 /* EJTAG 3.1 Debug Control Register at drseg 0xFF300000 */
93 #define PCS 9 /* R */
94 #define PCR2 8 /* R/W */
95 #define PCR1 7 /* R/W */
96 #define PCR0 6 /* R/W */
97 /* EJTAG 2.X Debug Control Register at drseg 0xFF300000 */
98 #define DataBrk 17 /* R */
99 #define InstBrk 16 /* R */
100 #define NMIPend 2 /* R */
101 #define SRstE 1 /* R/W */
102 #define DCRProbeEn 0 /* R */
103 /* EJTAG 1.5.3 Debug Control Register at drseg 0xFF300000*/
104 #define HIS 30 /* R */
105 #define ENM 29 /* R 0=Little End,1=Big Endian */
106 #define MIntE 4 /* R/W */
107 #define MNmiE 3 /* R/W */
108 #define MemProt 2 /* R/W 0=WriteOK,1=Protected */
109 #define MRst 1 /* R/W */
110 #define TraceMode 0 /* R/W */
111
112 /**
113 * bus->driver->(*new_bus)
114 *
115 */
116 static urj_bus_t *
ejtag_bus_new(urj_chain_t * chain,const urj_bus_driver_t * driver,const urj_param_t * cmd_params[])117 ejtag_bus_new (urj_chain_t *chain, const urj_bus_driver_t *driver,
118 const urj_param_t *cmd_params[])
119 {
120 return urj_bus_generic_new (chain, driver, sizeof (bus_params_t));
121 }
122
123 /**
124 * bus->driver->(*printinfo)
125 *
126 */
127 static void
ejtag_bus_printinfo(urj_log_level_t ll,urj_bus_t * bus)128 ejtag_bus_printinfo (urj_log_level_t ll, urj_bus_t *bus)
129 {
130 int i;
131
132 for (i = 0; i < bus->chain->parts->len; i++)
133 if (bus->part == bus->chain->parts->parts[i])
134 break;
135 urj_log (ll, _("EJTAG compatible bus driver via PrAcc (JTAG part No. %d)\n"),
136 i);
137 }
138
139 static uint32_t
reg_value(urj_tap_register_t * reg)140 reg_value (urj_tap_register_t *reg)
141 {
142 uint32_t retval = 0;
143 int i;
144
145 for (i = 0; i < reg->len; i++)
146 {
147 if (reg->data[i])
148 retval |= (1 << i);
149 }
150 return retval;
151 }
152
153 static uint32_t
ejtag_run_pracc(urj_bus_t * bus,const uint32_t * code,unsigned int len)154 ejtag_run_pracc (urj_bus_t *bus, const uint32_t *code, unsigned int len)
155 {
156 urj_data_register_t *ejaddr, *ejdata, *ejctrl;
157 int i, pass;
158 uint32_t addr, data, retval;
159
160 ejaddr = urj_part_find_data_register (bus->part, "EJADDRESS");
161 ejdata = urj_part_find_data_register (bus->part, "EJDATA");
162 ejctrl = urj_part_find_data_register (bus->part, "EJCONTROL");
163 if (!(ejaddr && ejdata && ejctrl))
164 {
165 urj_error_set (URJ_ERROR_NOTFOUND,
166 _("EJADDRESS, EJDATA or EJCONTROL register not found"));
167 return 0;
168 }
169
170 urj_part_set_instruction (bus->part, "EJTAG_CONTROL");
171 urj_tap_chain_shift_instructions (bus->chain);
172
173 pass = 0;
174 retval = 0;
175
176 for (;;)
177 {
178 ejctrl->in->data[PrAcc] = 1;
179 urj_tap_chain_shift_data_registers (bus->chain, 0);
180 urj_tap_chain_shift_data_registers (bus->chain, 1);
181
182 urj_log (URJ_LOG_LEVEL_ALL, "ctrl=%s\n",
183 urj_tap_register_get_string (ejctrl->out));
184
185 if (ejctrl->out->data[Rocc])
186 {
187 urj_error_set (URJ_ERROR_BUS, _("Reset occurred, ctrl=%s"),
188 urj_tap_register_get_string (ejctrl->out));
189 bus->initialized = 0;
190 break;
191 }
192 if (!ejctrl->out->data[PrAcc])
193 {
194 urj_error_set (URJ_ERROR_BUS, _("No processor access, ctrl=%s"),
195 urj_tap_register_get_string (ejctrl->out));
196 bus->initialized = 0;
197 break;
198 }
199
200 urj_part_set_instruction (bus->part, "EJTAG_ADDRESS");
201 urj_tap_chain_shift_instructions (bus->chain);
202
203 urj_tap_chain_shift_data_registers (bus->chain, 1);
204 addr = reg_value (ejaddr->out);
205 if (addr & 3)
206 {
207 urj_error_set (URJ_ERROR_BUS,
208 _("PrAcc bad alignment: addr=0x%08lx"),
209 (long unsigned) addr);
210 addr &= ~3;
211 }
212
213 urj_part_set_instruction (bus->part, "EJTAG_DATA");
214 urj_tap_chain_shift_instructions (bus->chain);
215
216 urj_tap_register_fill (ejdata->in, 0);
217
218 if (ejctrl->out->data[PRnW])
219 {
220 urj_tap_chain_shift_data_registers (bus->chain, 1);
221 data = reg_value (ejdata->out);
222 urj_log (URJ_LOG_LEVEL_ALL,
223 _("%s(%d) PrAcc write: addr=0x%08lx data=0x%08lx\n"),
224 __FILE__, __LINE__,
225 (long unsigned) addr, (long unsigned) data);
226 if (addr == UINT32_C (0xff200000))
227 {
228 /* Return value from the target CPU. */
229 retval = data;
230 }
231 else
232 {
233 urj_error_set (URJ_ERROR_BUS,
234 _("Unknown write addr=0x%08lx data=0x%08lx"),
235 (long unsigned) addr, (long unsigned) data);
236 }
237 }
238 else
239 {
240 if (addr == UINT32_C (0xff200200) && pass++)
241 break;
242
243 data = 0;
244 if (addr >= 0xff200200 && addr < 0xff200200 + (len << 2))
245 {
246 data = code[(addr - 0xff200200) >> 2];
247
248 for (i = 0; i < 32; i++)
249 ejdata->in->data[i] = (data >> i) & 1;
250 }
251 urj_log (URJ_LOG_LEVEL_ALL,
252 "%s(%d) PrAcc read: addr=0x%08lx data=0x%08lx\n",
253 __FILE__, __LINE__,
254 (long unsigned) addr, (long unsigned) data);
255 urj_tap_chain_shift_data_registers (bus->chain, 0);
256 }
257
258 urj_part_set_instruction (bus->part, "EJTAG_CONTROL");
259 urj_tap_chain_shift_instructions (bus->chain);
260
261 ejctrl->in->data[PrAcc] = 0;
262 urj_tap_chain_shift_data_registers (bus->chain, 0);
263 }
264 return retval;
265 }
266
267 static int
ejtag_bus_init(urj_bus_t * bus)268 ejtag_bus_init (urj_bus_t *bus)
269 {
270 urj_data_register_t *ejctrl, *ejimpl, *ejaddr, *ejdata;
271 uint32_t code[4] = {
272 0x3c04ff20, // lui $4,0xff20
273 0x349f0200, // ori $31,$4,0x0200
274 0x03e00008, // jr $31
275 0x3c030000 // lui $3,0
276 };
277
278 if (urj_tap_state (bus->chain) != URJ_TAP_STATE_RUN_TEST_IDLE)
279 {
280 /* silently skip initialization if TAP isn't in RUNTEST/IDLE state
281 this is required to avoid interfering with detect when initbus
282 is contained in the part description file
283 URJ_BUS_INIT() will be called latest by URJ_BUS_PREPARE() */
284 return URJ_STATUS_OK;
285 }
286
287 ejctrl = urj_part_find_data_register (bus->part, "EJCONTROL");
288 ejimpl = urj_part_find_data_register (bus->part, "EJIMPCODE");
289 ejaddr = urj_part_find_data_register (bus->part, "EJADDRESS");
290 ejdata = urj_part_find_data_register (bus->part, "EJDATA");
291 if (!(ejctrl && ejimpl))
292 {
293 urj_error_set (URJ_ERROR_NOTFOUND,
294 _("EJCONTROL or EJIMPCODE register not found"));
295 return URJ_STATUS_FAIL;
296 }
297
298 urj_part_set_instruction (bus->part, "EJTAG_IMPCODE");
299 urj_tap_chain_shift_instructions (bus->chain);
300 urj_tap_chain_shift_data_registers (bus->chain, 0); //Write
301 urj_tap_chain_shift_data_registers (bus->chain, 1); //Read
302 urj_log (URJ_LOG_LEVEL_NORMAL, "ImpCode=%s %08lX\n",
303 urj_tap_register_get_string (ejimpl->out),
304 (long unsigned) reg_value (ejimpl->out));
305 BP->impcode = reg_value (ejimpl->out);
306
307 switch (EJTAG_VER)
308 {
309 case EJTAG_20:
310 urj_log (URJ_LOG_LEVEL_NORMAL, "EJTAG version: <= 2.0\n");
311 break;
312 case EJTAG_25:
313 urj_log (URJ_LOG_LEVEL_NORMAL, "EJTAG version: 2.5\n");
314 break;
315 case EJTAG_26:
316 urj_log (URJ_LOG_LEVEL_NORMAL, "EJTAG version: 2.6\n");
317 break;
318 case EJTAG_31:
319 urj_log (URJ_LOG_LEVEL_NORMAL, "EJTAG version: 3.1\n");
320 break;
321 default:
322 urj_log (URJ_LOG_LEVEL_NORMAL, "EJTAG version: unknown (%lu)\n",
323 (long unsigned) EJTAG_VER);
324 }
325 urj_log (URJ_LOG_LEVEL_NORMAL,
326 "EJTAG Implementation flags:%s%s%s%s%s%s%s\n",
327 (BP->impcode & (1 << 28)) ? " R3k" : " R4k",
328 (BP->impcode & (1 << 24)) ? " DINTsup" : "",
329 (BP->impcode & (1 << 22)) ? " ASID_8" : "",
330 (BP->impcode & (1 << 21)) ? " ASID_6" : "",
331 (BP->impcode & (1 << 16)) ? " MIPS16" : "",
332 (BP->impcode & (1 << 14)) ? " NoDMA" : " DMA",
333 (BP->impcode & (1)) ? " MIPS64" : " MIPS32");
334
335 if (EJTAG_VER >= EJTAG_25)
336 {
337 urj_part_set_instruction (bus->part, "EJTAGBOOT");
338 urj_tap_chain_shift_instructions (bus->chain);
339 }
340 urj_part_set_instruction (bus->part, "EJTAG_CONTROL");
341 urj_tap_chain_shift_instructions (bus->chain);
342 //Reset
343 urj_tap_register_fill (ejctrl->in, 0);
344 ejctrl->in->data[PrRst] = 1;
345 ejctrl->in->data[PerRst] = 1;
346 urj_tap_chain_shift_data_registers (bus->chain, 0); //Write
347 ejctrl->in->data[PrRst] = 0;
348 ejctrl->in->data[PerRst] = 0;
349 urj_tap_chain_shift_data_registers (bus->chain, 0); //Write
350 //
351 if (EJTAG_VER == EJTAG_20)
352 {
353 if (!(ejaddr && ejdata))
354 {
355 urj_error_set (URJ_ERROR_NOTFOUND,
356 _("EJADDRESS or EJDATA register not found"));
357 return URJ_STATUS_FAIL;
358 }
359 // Try enabling memory write on EJTAG_20 (BCM6348)
360 // Badly Copied from HairyDairyMaid V4.8
361 //ejtag_dma_write(0xff300000, (ejtag_dma_read(0xff300000) & ~(1<<2)) );
362 urj_log (URJ_LOG_LEVEL_ALL, "Set Address to READ from\n");
363 urj_log (URJ_LOG_LEVEL_ALL, "Select EJTAG ADDRESS Register\n");
364 urj_part_set_instruction (bus->part, "EJTAG_ADDRESS");
365 urj_tap_chain_shift_instructions (bus->chain);
366 //Set to Debug Control Register Address, 0xFF300000
367 urj_tap_register_init (ejaddr->in,
368 "11111111001100000000000000000000");
369 urj_log (URJ_LOG_LEVEL_ALL, "Write to ejaddr->in =%s %08lX\n",
370 urj_tap_register_get_string (ejaddr->in),
371 (unsigned long) reg_value (ejaddr->in));
372 urj_tap_chain_shift_data_registers (bus->chain, 0); //Write
373 urj_log (URJ_LOG_LEVEL_ALL, "Select EJTAG CONTROL Register\n");
374 urj_part_set_instruction (bus->part, "EJTAG_CONTROL");
375 urj_tap_chain_shift_instructions (bus->chain);
376 //Set some bits in CONTROL Register 0x00068B00
377 urj_tap_register_fill (ejctrl->in, 0); // Clear Register
378 ejctrl->in->data[PrAcc] = 1; // 18----|||
379 ejctrl->in->data[DmaAcc] = 1; // 17----|||
380 ejctrl->in->data[ProbEn] = 1; // 15-----||
381 ejctrl->in->data[DStrt] = 1; // 11------|
382 ejctrl->in->data[DrWn] = 1; // 9-------|
383 ejctrl->in->data[Dsz1] = 1; // 8-------| DMA_WORD = 0x00000100 = Bit8
384 urj_tap_chain_shift_data_registers (bus->chain, 1); //WriteRead
385 urj_log (URJ_LOG_LEVEL_ALL, "Write To ejctrl->in =%s %08lX\n",
386 urj_tap_register_get_string (ejctrl->in),
387 (unsigned long) reg_value (ejctrl->in));
388 urj_log (URJ_LOG_LEVEL_ALL, "Read From ejctrl->out =%s %08lX\n",
389 urj_tap_register_get_string (ejctrl->out),
390 (unsigned long) reg_value (ejctrl->out));
391 do
392 {
393 urj_log (URJ_LOG_LEVEL_ALL, "Wait for DStrt to clear\n");
394 urj_part_set_instruction (bus->part, "EJTAG_CONTROL");
395 urj_tap_chain_shift_instructions (bus->chain);
396 urj_tap_register_fill (ejctrl->in, 0);
397 //Set some bits in CONTROL Register 0x00068000
398 ejctrl->in->data[PrAcc] = 1; // 18----||
399 ejctrl->in->data[DmaAcc] = 1; // 17----||
400 ejctrl->in->data[ProbEn] = 1; // 15-----|
401 urj_tap_chain_shift_data_registers (bus->chain, 1); //WriteRead
402 urj_log (URJ_LOG_LEVEL_ALL, "Write To ejctrl->in =%s %08lX\n",
403 urj_tap_register_get_string (ejctrl->in),
404 (unsigned long) reg_value (ejctrl->in));
405 urj_log (URJ_LOG_LEVEL_ALL, "Read From ejctrl->out =%s %08lX\n",
406 urj_tap_register_get_string( ejctrl->out),
407 (unsigned long) reg_value (ejctrl->out));
408 }
409 while (ejctrl->out->data[DStrt] == 1);
410 urj_log (URJ_LOG_LEVEL_ALL, "Select EJTAG DATA Register\n");
411 urj_part_set_instruction (bus->part, "EJTAG_DATA");
412 urj_tap_chain_shift_instructions (bus->chain);
413 urj_tap_register_fill (ejdata->in, 0); // Clear Register
414 urj_tap_chain_shift_data_registers (bus->chain, 1); //WriteRead
415 urj_log (URJ_LOG_LEVEL_ALL, "Write To ejdata->in =%s %08lX\n",
416 urj_tap_register_get_string (ejdata->in),
417 (unsigned long) reg_value (ejdata->in));
418 urj_log (URJ_LOG_LEVEL_ALL, "Read From ejdata->out =%s %08lX\n",
419 urj_tap_register_get_string (ejdata->out),
420 (unsigned long) reg_value (ejdata->out));
421 urj_log (URJ_LOG_LEVEL_ALL, "Select EJTAG CONTROL Register\n");
422 urj_part_set_instruction (bus->part, "EJTAG_CONTROL");
423 urj_tap_chain_shift_instructions (bus->chain);
424 urj_tap_register_fill (ejctrl->in, 0);
425 //Set some bits in CONTROL Register 0x00048000
426 ejctrl->in->data[PrAcc] = 1; // 18----||
427 ejctrl->in->data[ProbEn] = 1; // 15-----|
428 urj_tap_chain_shift_data_registers (bus->chain, 1); //WriteRead
429 urj_log (URJ_LOG_LEVEL_ALL, "Write To ejctrl->in =%s %08lX\n",
430 urj_tap_register_get_string (ejctrl->in),
431 (unsigned long) reg_value (ejctrl->in));
432 urj_log (URJ_LOG_LEVEL_ALL, "Read From ejctrl->out =%s %08lX\n",
433 urj_tap_register_get_string (ejctrl->out),
434 (unsigned long) reg_value (ejctrl->out));
435 if (ejctrl->out->data[DeRR] == 1)
436 {
437 urj_error_set (URJ_ERROR_BUS_DMA, "DMA READ ERROR");
438 }
439 //Now have data from DCR, need to reset the MP Bit (2) and write it back out
440 urj_tap_register_init (ejdata->in,
441 urj_tap_register_get_string (ejdata->out));
442 ejdata->in->data[MemProt] = 0;
443 urj_log (URJ_LOG_LEVEL_ALL, "Need to Write ejdata-> =%s %08lX\n",
444 urj_tap_register_get_string (ejdata->in),
445 (unsigned long) reg_value (ejdata->in));
446
447 // Now the Write
448 urj_log (URJ_LOG_LEVEL_ALL, "Set Address To Write To\n");
449 urj_log (URJ_LOG_LEVEL_ALL, "Select EJTAG ADDRESS Register\n");
450 urj_part_set_instruction (bus->part, "EJTAG_ADDRESS");
451 urj_tap_chain_shift_instructions (bus->chain);
452 urj_tap_register_init (ejaddr->in,
453 "11111111001100000000000000000000");
454 urj_log (URJ_LOG_LEVEL_ALL, "Write to ejaddr->in =%s %08lX\n",
455 urj_tap_register_get_string (ejaddr->in),
456 (unsigned long) reg_value (ejaddr->in));
457 //This appears to be a write with NO Read
458 urj_tap_chain_shift_data_registers (bus->chain, 0); //Write
459 urj_log (URJ_LOG_LEVEL_ALL, "Select EJTAG DATA Register\n");
460 urj_part_set_instruction (bus->part, "EJTAG_DATA");
461 urj_tap_chain_shift_instructions (bus->chain);
462 //The value is already in ejdata->in, so write it
463 urj_log (URJ_LOG_LEVEL_ALL, "Write To ejdata->in =%s %08lX\n",
464 urj_tap_register_get_string (ejdata->in),
465 (unsigned long) reg_value (ejdata->in));
466 urj_tap_chain_shift_data_registers (bus->chain, 0); //Write
467 urj_log (URJ_LOG_LEVEL_ALL, "Select EJTAG CONTROL Register\n");
468 urj_part_set_instruction (bus->part, "EJTAG_CONTROL");
469 urj_tap_chain_shift_instructions (bus->chain);
470
471 //Set some bits in CONTROL Register
472 urj_tap_register_fill (ejctrl->in, 0); // Clear Register
473 ejctrl->in->data[DmaAcc] = 1; // 17
474 ejctrl->in->data[Dsz1] = 1; // DMA_WORD = 0x00000100 = Bit8
475 ejctrl->in->data[DStrt] = 1; // 11
476 ejctrl->in->data[ProbEn] = 1; // 15
477 ejctrl->in->data[PrAcc] = 1; // 18
478 urj_tap_chain_shift_data_registers (bus->chain, 1); //Write/Read
479 urj_log (URJ_LOG_LEVEL_ALL, "Write to ejctrl->in =%s %08lX\n",
480 urj_tap_register_get_string (ejctrl->in),
481 (unsigned long) reg_value (ejctrl->in));
482 urj_log (URJ_LOG_LEVEL_ALL, "Read from ejctrl->out =%s %08lX\n",
483 urj_tap_register_get_string (ejctrl->out),
484 (unsigned long) reg_value (ejctrl->out));
485 do
486 {
487 urj_log (URJ_LOG_LEVEL_ALL, "Wait for DStrt to clear\n");
488 //Might not need these 2 lines
489 urj_part_set_instruction (bus->part, "EJTAG_CONTROL");
490 urj_tap_chain_shift_instructions (bus->chain);
491 ejctrl->in->data[DmaAcc] = 1; // 17
492 ejctrl->in->data[ProbEn] = 1; // 15
493 ejctrl->in->data[PrAcc] = 1; // 18
494 urj_tap_chain_shift_data_registers (bus->chain, 1); //Write/Read
495 urj_log (URJ_LOG_LEVEL_ALL, "Write to ejctrl->in =%s %08lX\n",
496 urj_tap_register_get_string (ejctrl->in),
497 (unsigned long) reg_value (ejctrl->in));
498 urj_log (URJ_LOG_LEVEL_ALL, "Read from ejctrl->out =%s %08lX\n",
499 urj_tap_register_get_string (ejctrl->out),
500 (unsigned long) reg_value (ejctrl->out));
501 }
502 while (ejctrl->out->data[DStrt] == 1);
503 urj_log (URJ_LOG_LEVEL_ALL, "Select EJTAG CONTROL Register\n");
504 urj_part_set_instruction (bus->part, "EJTAG_CONTROL");
505 urj_tap_chain_shift_instructions (bus->chain);
506 urj_tap_register_fill (ejctrl->in, 0);
507 //Set some bits in CONTROL Register 0x00048000
508 ejctrl->in->data[PrAcc] = 1; // 18----||
509 ejctrl->in->data[ProbEn] = 1; // 15-----|
510 urj_tap_chain_shift_data_registers (bus->chain, 1); //Write/Read
511 urj_log (URJ_LOG_LEVEL_ALL, "Write To ejctrl->in =%s %08lX\n",
512 urj_tap_register_get_string (ejctrl->in),
513 (unsigned long) reg_value (ejctrl->in));
514 urj_log (URJ_LOG_LEVEL_ALL, "Read From ejctrl->out =%s %08lX\n",
515 urj_tap_register_get_string (ejctrl->out),
516 (unsigned long) reg_value (ejctrl->out));
517 if (ejctrl->out->data[DeRR] == 1)
518 {
519 urj_error_set (URJ_ERROR_BUS_DMA, "DMA WRITE ERROR");
520 }
521 }
522
523 urj_part_set_instruction (bus->part, "EJTAG_CONTROL");
524 urj_tap_chain_shift_instructions (bus->chain);
525
526 urj_tap_register_fill (ejctrl->in, 0);
527 ejctrl->in->data[PrAcc] = 1;
528 ejctrl->in->data[ProbEn] = 1;
529 if (EJTAG_VER >= EJTAG_25)
530 {
531 ejctrl->in->data[ProbTrap] = 1;
532 ejctrl->in->data[Rocc] = 1;
533 }
534 urj_tap_chain_shift_data_registers (bus->chain, 0);
535
536 ejctrl->in->data[PrAcc] = 1;
537 ejctrl->in->data[ProbEn] = 1;
538 ejctrl->in->data[ProbTrap] = 1;
539 ejctrl->in->data[JtagBrk] = 1;
540
541 urj_tap_chain_shift_data_registers (bus->chain, 0);
542
543 ejctrl->in->data[JtagBrk] = 0;
544 urj_tap_chain_shift_data_registers (bus->chain, 1);
545
546 if (!ejctrl->out->data[BrkSt])
547 {
548 urj_error_set (URJ_ERROR_ILLEGAL_STATE,
549 _("Failed to enter debug mode, ctrl=%s"),
550 urj_tap_register_get_string (ejctrl->out));
551 return URJ_STATUS_FAIL;
552 }
553 else
554 {
555 urj_log (URJ_LOG_LEVEL_NORMAL, "Processor entered Debug Mode.\n");
556 }
557 if (ejctrl->out->data[Rocc])
558 {
559 ejctrl->in->data[Rocc] = 0;
560 urj_tap_chain_shift_data_registers (bus->chain, 0);
561 ejctrl->in->data[Rocc] = 1;
562 urj_tap_chain_shift_data_registers (bus->chain, 1);
563 }
564
565 //HDM now Clears Watchdog
566
567
568 ejtag_run_pracc (bus, code, 4);
569 BP->adr_hi = 0;
570 bus->initialized = 1;
571 return URJ_STATUS_OK;
572 }
573
574 /**
575 * bus->driver->(*prepare)
576 *
577 */
578 static void
ejtag_bus_prepare(urj_bus_t * bus)579 ejtag_bus_prepare (urj_bus_t *bus)
580 {
581 if (!bus->initialized)
582 URJ_BUS_INIT (bus);
583 }
584
585 /**
586 * bus->driver->(*area)
587 *
588 */
589 static int
ejtag_bus_area(urj_bus_t * bus,uint32_t adr,urj_bus_area_t * area)590 ejtag_bus_area (urj_bus_t *bus, uint32_t adr, urj_bus_area_t *area)
591 {
592 if (adr < UINT32_C (0x20000000))
593 {
594 area->description = NULL;
595 area->start = UINT32_C (0x00000000);
596 area->length = UINT64_C (0x20000000);
597 area->width = 8;
598 }
599 else if (adr < UINT32_C (0x40000000))
600 {
601 area->description = NULL;
602 area->start = UINT32_C (0x20000000);
603 area->length = UINT64_C (0x20000000);
604 area->width = 16;
605 }
606 else if (adr < UINT32_C (0x60000000))
607 {
608 area->description = NULL;
609 area->start = UINT32_C (0x40000000);
610 area->length = UINT64_C (0x20000000);
611 area->width = 32;
612 }
613 else
614 {
615 area->description = NULL;
616 area->start = UINT32_C (0x60000000);
617 area->length = UINT64_C (0xa0000000);
618 area->width = 0;
619 }
620 return URJ_STATUS_OK;
621 }
622
623 static int
ejtag_gen_read(urj_bus_t * bus,uint32_t * code,uint32_t adr)624 ejtag_gen_read (urj_bus_t *bus, uint32_t *code, uint32_t adr)
625 {
626 uint16_t adr_hi, adr_lo;
627 uint32_t *p = code;
628
629 /* 16-bit signed offset, phys -> kseg1 */
630 adr_lo = adr & 0xffff;
631 adr_hi = ((adr >> 16) & 0x1fff);
632 /* Increment adr_hi if adr_lo < 0 */
633 adr_hi += (adr_lo >> 15);
634 /* Bypass cache */
635 adr_hi += 0xa000;
636
637 if (BP->adr_hi != adr_hi)
638 {
639 BP->adr_hi = adr_hi;
640 *p++ = 0x3c030000 | adr_hi; // lui $3,adr_hi
641 }
642 switch (adr >> 29)
643 {
644 case 0:
645 *p++ = 0x90620000 | adr_lo; // lbu $2,adr_lo($3)
646 break;
647 case 1:
648 *p++ = 0x94620000 | (adr_lo & ~1); // lhu $2,adr_lo($3)
649 break;
650 case 2:
651 *p++ = 0x8c620000 | (adr_lo & ~3); // lw $2,adr_lo($3)
652 break;
653 default: /* unknown bus width */
654 *p++ = 0x00001025; // move $2,$0
655 break;
656 }
657 *p++ = 0x03e00008; // jr $31
658 return p - code;
659 }
660
661 /**
662 * bus->driver->(*read_start)
663 *
664 */
665 static int
ejtag_bus_read_start(urj_bus_t * bus,uint32_t adr)666 ejtag_bus_read_start (urj_bus_t *bus, uint32_t adr)
667 {
668 uint32_t code[3];
669
670 ejtag_run_pracc (bus, code, ejtag_gen_read (bus, code, adr));
671 urj_log (URJ_LOG_LEVEL_COMM, "URJ_BUS_READ_START: adr=0x%08lx\n",
672 (long unsigned) adr);
673
674 return URJ_STATUS_OK;
675 }
676
677 /**
678 * bus->driver->(*read_next)
679 *
680 */
681 static uint32_t
ejtag_bus_read_next(urj_bus_t * bus,uint32_t adr)682 ejtag_bus_read_next (urj_bus_t *bus, uint32_t adr)
683 {
684 uint32_t d;
685 uint32_t code[4], *p = code;
686
687 *p++ = 0xac820000; // sw $2,0($4)
688 p += ejtag_gen_read (bus, p, adr);
689
690 d = ejtag_run_pracc (bus, code, p - code);
691
692 urj_log (URJ_LOG_LEVEL_COMM,
693 "URJ_BUS_READ_NEXT: adr=0x%08lx data=0x%08lx\n",
694 (long unsigned) adr, (long unsigned) d);
695 return d;
696 }
697
698 /**
699 * bus->driver->(*read_end)
700 *
701 */
702 static uint32_t
ejtag_bus_read_end(urj_bus_t * bus)703 ejtag_bus_read_end (urj_bus_t *bus)
704 {
705 uint32_t d;
706 static const uint32_t code[2] = {
707 0xac820000, // sw $2,0($4)
708 0x03e00008 // jr $31
709 };
710
711 d = ejtag_run_pracc (bus, code, 2);
712
713 urj_log (URJ_LOG_LEVEL_COMM, "URJ_BUS_READ_END: data=0x%08lx\n",
714 (long unsigned) d);
715 return d;
716 }
717
718 /**
719 * bus->driver->(*write)
720 *
721 */
722 static void
ejtag_bus_write(urj_bus_t * bus,uint32_t adr,uint32_t data)723 ejtag_bus_write (urj_bus_t *bus, uint32_t adr, uint32_t data)
724 {
725 uint16_t adr_hi, adr_lo;
726 uint32_t code[5], *p = code;
727
728 /* 16-bit signed offset, phys -> kseg1 */
729 adr_lo = adr & 0xffff;
730 adr_hi = ((adr >> 16) & 0x1fff) + (adr_lo >> 15) + 0xa000;
731
732 if (BP->adr_hi != adr_hi)
733 {
734 BP->adr_hi = adr_hi;
735 *p++ = 0x3c030000 | adr_hi; // lui $3,adr_hi
736 }
737 switch (adr >> 29)
738 {
739 case 0:
740 *p++ = 0x34020000 | (data & 0xff); // li $2,data
741 *p++ = 0xa0620000 | adr_lo; // sb $2,adr_lo($3)
742 break;
743 case 1:
744 *p++ = 0x34020000 | (data & 0xffff); // li $2,data
745 *p++ = 0xa4620000 | (adr_lo & ~1); // sh $2,adr_lo($3)
746 break;
747 case 2:
748 *p++ = 0x3c020000 | (data >> 16); // lui $2,data_hi
749 *p++ = 0x34420000 | (data & 0xffff); // ori $2,data_lo
750 *p++ = 0xac620000 | (adr_lo & ~3); // sw $2,adr_lo($3)
751 break;
752 }
753 *p++ = 0x03e00008; // jr $31
754
755 ejtag_run_pracc (bus, code, p - code);
756
757 urj_log (URJ_LOG_LEVEL_COMM,
758 "URJ_BUS_WRITE: adr=0x%08lx data=0x%08lx\n",
759 (long unsigned) adr, (long unsigned) data);
760 }
761
762 const urj_bus_driver_t urj_bus_ejtag_bus = {
763 "ejtag",
764 N_("EJTAG compatible bus driver via PrAcc"),
765 ejtag_bus_new,
766 urj_bus_generic_free,
767 ejtag_bus_printinfo,
768 ejtag_bus_prepare,
769 ejtag_bus_area,
770 ejtag_bus_read_start,
771 ejtag_bus_read_next,
772 ejtag_bus_read_end,
773 urj_bus_generic_read,
774 urj_bus_generic_write_start,
775 ejtag_bus_write,
776 ejtag_bus_init,
777 urj_bus_generic_no_enable,
778 urj_bus_generic_no_disable,
779 URJ_BUS_TYPE_PARALLEL,
780 };
781