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Searched refs:REG_AWIDTH (Results 1 – 23 of 23) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/xport_sv/
H A Deth_regs.vh16 localparam [REG_AWIDTH-1:0] REG_MAC_LSB = BASE + 'h0000;
17 localparam [REG_AWIDTH-1:0] REG_MAC_MSB = BASE + 'h0004;
20 localparam [REG_AWIDTH-1:0] REG_IP = BASE + 'h1000;
22 localparam [REG_AWIDTH-1:0] REG_UDP = BASE + 'h1004;
25 localparam [REG_AWIDTH-1:0] REG_BRIDGE_MAC_LSB = BASE + 'h1010;
26 localparam [REG_AWIDTH-1:0] REG_BRIDGE_MAC_MSB = BASE + 'h1014;
27 localparam [REG_AWIDTH-1:0] REG_BRIDGE_IP = BASE + 'h1018;
28 localparam [REG_AWIDTH-1:0] REG_BRIDGE_UDP = BASE + 'h101c;
29 localparam [REG_AWIDTH-1:0] REG_BRIDGE_ENABLE = BASE + 'h1020;
31 localparam [REG_AWIDTH-1:0] REG_CHDR_DROPPED = BASE + 'h1030;
[all …]
H A Deth_ipv4_interface.sv34 int REG_AWIDTH = 14, constant
51 input logic [REG_AWIDTH-1:0] reg_wr_addr,
56 input logic [REG_AWIDTH-1:0] reg_rd_addr,
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/xport/
H A Deth_interface.v13 parameter REG_AWIDTH = 14, constant
22 input [REG_AWIDTH-1:0] reg_wr_addr,
27 input [REG_AWIDTH-1:0] reg_rd_addr,
80 localparam [REG_AWIDTH-1:0] REG_MAC_LSB = BASE + 'h0000;
81 localparam [REG_AWIDTH-1:0] REG_MAC_MSB = BASE + 'h0004;
84 localparam [REG_AWIDTH-1:0] REG_IP = BASE + 'h1000;
86 localparam [REG_AWIDTH-1:0] REG_UDP = BASE + 'h1004;
89 localparam [REG_AWIDTH-1:0] REG_BRIDGE_MAC_LSB = BASE + 'h1010;
90 localparam [REG_AWIDTH-1:0] REG_BRIDGE_MAC_MSB = BASE + 'h1014;
91 localparam [REG_AWIDTH-1:0] REG_BRIDGE_IP = BASE + 'h1018;
[all …]
H A Deth_internal.v280 .REG_AWIDTH (AWIDTH),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/
H A Dn3xx_mgt_wrapper.v18 parameter REG_AWIDTH = 14, constant
39 input wire [REG_AWIDTH-1:0] reg_wr_addr,
42 input wire [REG_AWIDTH-1:0] reg_rd_addr,
147 localparam [REG_AWIDTH-1:0] REG_BASE_MGT_IO = {REG_AWIDTH{1'b0}} + REG_BASE;
148 localparam [REG_AWIDTH-1:0] REG_BASE_ETH_SWITCH = {REG_AWIDTH{1'b0}} + 16'h1000 + REG_BASE;
175 .REG_AWIDTH (REG_AWIDTH), // Width of the address bus
406 .REG_AWIDTH (REG_AWIDTH),
H A Dn3xx_mgt_io_core.v18 parameter REG_AWIDTH = 14, constant
57 input [REG_AWIDTH-1:0] reg_wr_addr,
60 input [REG_AWIDTH-1:0] reg_rd_addr,
85 localparam [REG_AWIDTH-1:0] REG_PORT_INFO = REG_BASE + 'h0;
86 localparam [REG_AWIDTH-1:0] REG_MAC_CTRL_STATUS = REG_BASE + 'h4;
87 localparam [REG_AWIDTH-1:0] REG_PHY_CTRL_STATUS = REG_BASE + 'h8;
88 localparam [REG_AWIDTH-1:0] REG_MAC_LED_CTL = REG_BASE + 'hC;
91 localparam [REG_AWIDTH-1:0] REG_ETH_MDIO_BASE = REG_BASE + 'h10;
93 localparam [REG_AWIDTH-1:0] REG_AURORA_OVERRUNS = REG_BASE + 'h20;
94 localparam [REG_AWIDTH-1:0] REG_CHECKSUM_ERRORS = REG_BASE + 'h24;
[all …]
H A Dn3xx_mgt_channel_wrapper.v23 parameter REG_AWIDTH = 14, // Width of regport data bus constant
41 input wire [REG_AWIDTH-1:0] s_axi_awaddr,
54 input wire [REG_AWIDTH-1:0] s_axi_araddr,
193 wire [REG_AWIDTH-1:0] reg_wr_addr;
196 wire [REG_AWIDTH-1:0] reg_rd_addr;
202 .AWIDTH (REG_AWIDTH), // Width of the address bus
268 .REG_AWIDTH (REG_AWIDTH), // Width of the address bus
H A Dn3xx_core.v19 parameter REG_AWIDTH = 32, // Width of the address bus constant
54 input [REG_AWIDTH-1:0] s_axi_awaddr,
67 input [REG_AWIDTH-1:0] s_axi_araddr,
187 output [REG_AWIDTH-1:0] reg_wr_addr_npio,
190 output [REG_AWIDTH-1:0] reg_rd_addr_npio,
306 .AXI_AWIDTH (REG_AWIDTH),
437 .REG_AWIDTH (REG_AWIDTH),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/
H A Ddemo_one_gig_pcs_pma_mdio.v219 parameter REG_AWIDTH = 14; constant
222 reg [REG_AWIDTH-1:0] reg_wr_addr;
225 reg [REG_AWIDTH-1:0] reg_rd_addr;
269 .REG_AWIDTH (REG_AWIDTH),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/control/
H A Dctrlport_to_regport.v28 parameter REG_AWIDTH = 20, constant
42 output reg [REG_AWIDTH-1:0] reg_wr_addr = 'bX,
45 output reg [REG_AWIDTH-1:0] reg_rd_addr = 'bX,
H A Daxi_crossbar_regport.v20 parameter REG_AWIDTH = 14 // Width of the address bus constant
27 input [REG_AWIDTH-1:0] reg_wr_addr,
31 input [REG_AWIDTH-1:0] reg_rd_addr,
135 .AWIDTH(REG_AWIDTH),
H A Dmdio_master.v9 parameter REG_AWIDTH = 32, constant
23 input [REG_AWIDTH-1:0] reg_wr_addr,
26 input [REG_AWIDTH-1:0] reg_rd_addr,
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/xport_sv/eth_interface_tb/
H A Deth_ifc_synth_test.sv27 parameter REG_AWIDTH = 14, constant
39 input logic [REG_AWIDTH-1:0] reg_wr_addr,
44 input logic [REG_AWIDTH-1:0] reg_rd_addr,
150 .REG_AWIDTH(REG_AWIDTH), .RT_TBL_SIZE(RT_TBL_SIZE),
H A Deth_ifc_tb.sv35 localparam REG_AWIDTH = 14; constant
102 reg [REG_AWIDTH-1:0] reg_wr_addr = 0;
106 reg [REG_AWIDTH-1:0] reg_rd_addr = 0;
130 .REG_AWIDTH(REG_AWIDTH),
211 .REG_AWIDTH(REG_AWIDTH), .RT_TBL_SIZE(RT_TBL_SIZE),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/
H A Dn3xx_mgt_io_core.v18 parameter REG_AWIDTH = 14, constant
54 input [REG_AWIDTH-1:0] reg_wr_addr,
57 input [REG_AWIDTH-1:0] reg_rd_addr,
239 .REG_AWIDTH (REG_AWIDTH),
H A De320.v196 localparam REG_AWIDTH = 14; // log2(0x4000) constant
1068 .AWIDTH(REG_AWIDTH), // Width of the address bus
1104 .s_axi_awaddr(m_axi_net_awaddr[REG_AWIDTH-1:0]),
1117 .s_axi_araddr(m_axi_net_araddr[REG_AWIDTH-1:0]),
1314 .AWIDTH(REG_AWIDTH),
1687 .REG_AWIDTH(REG_AWIDTH),
H A Dn3xx_sfp_wrapper.v240 .REG_AWIDTH (AWIDTH), // Width of the address bus
435 .REG_AWIDTH (AWIDTH),
H A De320_core.v20 parameter REG_AWIDTH = 32, // Width of the address bus constant
42 input wire [REG_AWIDTH-1:0] s_axi_awaddr,
55 input wire [REG_AWIDTH-1:0] s_axi_araddr,
280 .AXI_AWIDTH (REG_AWIDTH),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/mg/
H A Dn3xx.v319 localparam REG_AWIDTH = 14; // log2(0x4000) constant
900 wire [REG_AWIDTH-1:0] reg_wr_addr_npio;
903 wire [REG_AWIDTH-1:0] reg_rd_addr_npio;
1166 .REG_AWIDTH (QSFP_REG_AWIDTH)
1363 .REG_AWIDTH (REG_AWIDTH), // Width of the address bus
1420 .REG_AWIDTH (REG_AWIDTH), // Width of the address bus
1681 .REG_AWIDTH(REG_AWIDTH), // Width of the address bus
1718 .s_axi_awaddr(M_AXI_NET0_AWADDR[REG_AWIDTH-1:0]),
1852 .REG_AWIDTH(REG_AWIDTH), // Width of the address bus
2563 .AWIDTH(REG_AWIDTH),
[all …]
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/rh/
H A Dn3xx.v311 localparam REG_AWIDTH = 14; // log2(0x4000) constant
889 wire [REG_AWIDTH-1:0] reg_wr_addr_npio;
892 wire [REG_AWIDTH-1:0] reg_rd_addr_npio;
1156 .REG_AWIDTH (QSFP_REG_AWIDTH)
1353 .REG_AWIDTH (REG_AWIDTH), // Width of the address bus
1410 .REG_AWIDTH (REG_AWIDTH), // Width of the address bus
1671 .REG_AWIDTH(REG_AWIDTH), // Width of the address bus
1709 .s_axi_awaddr(M_AXI_NET0_AWADDR[REG_AWIDTH-1:0]),
1842 .REG_AWIDTH(REG_AWIDTH), // Width of the address bus
2554 .AWIDTH(REG_AWIDTH),
[all …]
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e31x/
H A De31x_core.v19 parameter REG_AWIDTH = 32, // Width of the address bus constant
42 input wire [REG_AWIDTH-1:0] s_axi_awaddr,
55 input wire [REG_AWIDTH-1:0] s_axi_araddr,
214 .AXI_AWIDTH (REG_AWIDTH),
H A De31x.v138 localparam REG_AWIDTH = 14; // log2(0x4000) constant
401 .AWIDTH(REG_AWIDTH),
835 .REG_AWIDTH(REG_AWIDTH),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/sim/aurora_loopback/
H A Daurora_loopback_tb.sv200 .REG_AWIDTH(14) // Width of regport data bus