1///////////////////////////////////////////////////////////////////// 2// 3// Copyright 2017-2019 Ettus Research, A National Instruments Brand 4// 5// SPDX-License-Identifier: LGPL-3.0-or-later 6// 7// Module: n3xx_core 8// Description: 9// - Motherboard Registers 10// - Crossbar 11// - Noc Block Radios 12// - Noc Block Dram fifo 13// - Radio Front End control 14// 15///////////////////////////////////////////////////////////////////// 16 17module n3xx_core #( 18 parameter REG_DWIDTH = 32, // Width of the AXI4-Lite data bus (must be 32 or 64) 19 parameter REG_AWIDTH = 32, // Width of the address bus 20 parameter BUS_CLK_RATE = 200000000, // BUS_CLK rate 21 parameter CHANNEL_WIDTH = 32, 22 parameter NUM_CHANNELS_PER_RADIO = 1, 23 parameter NUM_CHANNELS = 4, 24 parameter NUM_DBOARDS = 2, 25 parameter NUM_SPI_PER_DBOARD = 8, 26 parameter USE_CORRECTION = 0, 27 parameter USE_REPLAY = 0, // 1 for Replay block instead of DMA FIFO 28 parameter FP_GPIO_WIDTH = 12, // Front panel GPIO width 29 parameter RFNOC_PROTOVER = {8'd1, 8'd0}, 30 parameter CHDR_WIDTH = 16'd64 31)( 32 // Clocks and resets 33 input radio_clk, 34 input radio_rst, 35 input bus_clk, 36 input bus_rst, 37 input ddr3_dma_clk, 38 input clk40, 39 40 // Clocking and PPS Controls/Indicators 41 input pps, 42 output reg[3:0] pps_select = 4'h1, 43 output reg pps_out_enb, 44 output reg[1:0] pps_select_sfp = 2'b0, 45 output reg ref_clk_reset, 46 output reg meas_clk_reset, 47 input ref_clk_locked, 48 input meas_clk_locked, 49 output reg enable_ref_clk_async, 50 51 // Motherboard Registers: AXI lite interface 52 input s_axi_aclk, 53 input s_axi_aresetn, 54 input [REG_AWIDTH-1:0] s_axi_awaddr, 55 input s_axi_awvalid, 56 output s_axi_awready, 57 58 input [REG_DWIDTH-1:0] s_axi_wdata, 59 input [REG_DWIDTH/8-1:0] s_axi_wstrb, 60 input s_axi_wvalid, 61 output s_axi_wready, 62 63 output [1:0] s_axi_bresp, 64 output s_axi_bvalid, 65 input s_axi_bready, 66 67 input [REG_AWIDTH-1:0] s_axi_araddr, 68 input s_axi_arvalid, 69 output s_axi_arready, 70 71 output [REG_DWIDTH-1:0] s_axi_rdata, 72 output [1:0] s_axi_rresp, 73 output s_axi_rvalid, 74 input s_axi_rready, 75 76 // PS GPIO source 77 input [FP_GPIO_WIDTH-1:0] ps_gpio_out, 78 input [FP_GPIO_WIDTH-1:0] ps_gpio_tri, 79 output [FP_GPIO_WIDTH-1:0] ps_gpio_in, 80 81 // Front Panel GPIO 82 inout [FP_GPIO_WIDTH-1:0] fp_gpio_inout, 83 84 // Radio GPIO control for DSA 85 output [16*NUM_CHANNELS-1:0] db_gpio_out_flat, 86 output [16*NUM_CHANNELS-1:0] db_gpio_ddr_flat, 87 input [16*NUM_CHANNELS-1:0] db_gpio_in_flat, 88 input [16*NUM_CHANNELS-1:0] db_gpio_fab_flat, 89 90 // Radio ATR 91 output [NUM_CHANNELS-1:0] rx_atr, 92 output [NUM_CHANNELS-1:0] tx_atr, 93 94 // Radio Data 95 input [NUM_CHANNELS-1:0] rx_stb, 96 input [NUM_CHANNELS-1:0] tx_stb, 97 input [CHANNEL_WIDTH*NUM_CHANNELS-1:0] rx, 98 output [CHANNEL_WIDTH*NUM_CHANNELS-1:0] tx, 99 100 // CPLD 101 output [NUM_SPI_PER_DBOARD*NUM_DBOARDS-1:0] sen_flat, 102 output [NUM_DBOARDS-1:0] sclk_flat, 103 output [NUM_DBOARDS-1:0] mosi_flat, 104 input [NUM_DBOARDS-1:0] miso_flat, 105 106 // DMA xport adapter to PS 107 input wire [63:0] s_dma_tdata, 108 input wire s_dma_tlast, 109 output wire s_dma_tready, 110 input wire s_dma_tvalid, 111 112 output wire [63:0] m_dma_tdata, 113 output wire m_dma_tlast, 114 input wire m_dma_tready, 115 output wire m_dma_tvalid, 116 117 // AXI4 (256b@200MHz) interface to DDR3 controller 118 input ddr3_axi_clk, 119 input ddr3_axi_rst, 120 input ddr3_running, 121 // Write Address Ports 122 output [3:0] ddr3_axi_awid, 123 output [31:0] ddr3_axi_awaddr, 124 output [7:0] ddr3_axi_awlen, 125 output [2:0] ddr3_axi_awsize, 126 output [1:0] ddr3_axi_awburst, 127 output [0:0] ddr3_axi_awlock, 128 output [3:0] ddr3_axi_awcache, 129 output [2:0] ddr3_axi_awprot, 130 output [3:0] ddr3_axi_awqos, 131 output ddr3_axi_awvalid, 132 input ddr3_axi_awready, 133 // Write Data Ports 134 output [255:0] ddr3_axi_wdata, 135 output [31:0] ddr3_axi_wstrb, 136 output ddr3_axi_wlast, 137 output ddr3_axi_wvalid, 138 input ddr3_axi_wready, 139 // Write Response Ports 140 output ddr3_axi_bready, 141 input [3:0] ddr3_axi_bid, 142 input [1:0] ddr3_axi_bresp, 143 input ddr3_axi_bvalid, 144 // Read Address Ports 145 output [3:0] ddr3_axi_arid, 146 output [31:0] ddr3_axi_araddr, 147 output [7:0] ddr3_axi_arlen, 148 output [2:0] ddr3_axi_arsize, 149 output [1:0] ddr3_axi_arburst, 150 output [0:0] ddr3_axi_arlock, 151 output [3:0] ddr3_axi_arcache, 152 output [2:0] ddr3_axi_arprot, 153 output [3:0] ddr3_axi_arqos, 154 output ddr3_axi_arvalid, 155 input ddr3_axi_arready, 156 // Read Data Ports 157 output ddr3_axi_rready, 158 input [3:0] ddr3_axi_rid, 159 input [255:0] ddr3_axi_rdata, 160 input [1:0] ddr3_axi_rresp, 161 input ddr3_axi_rlast, 162 input ddr3_axi_rvalid, 163 164 // v2e (vita to ethernet) and e2v (eth to vita) 165 output [63:0] v2e0_tdata, 166 output v2e0_tvalid, 167 output v2e0_tlast, 168 input v2e0_tready, 169 170 output [63:0] v2e1_tdata, 171 output v2e1_tlast, 172 output v2e1_tvalid, 173 input v2e1_tready, 174 175 input [63:0] e2v0_tdata, 176 input e2v0_tlast, 177 input e2v0_tvalid, 178 output e2v0_tready, 179 180 input [63:0] e2v1_tdata, 181 input e2v1_tlast, 182 input e2v1_tvalid, 183 output e2v1_tready, 184 185 // RegPort interface to NPIO 186 output reg_wr_req_npio, 187 output [REG_AWIDTH-1:0] reg_wr_addr_npio, 188 output [REG_DWIDTH-1:0] reg_wr_data_npio, 189 output reg_rd_req_npio, 190 output [REG_AWIDTH-1:0] reg_rd_addr_npio, 191 input reg_rd_resp_npio, 192 input [REG_DWIDTH-1:0] reg_rd_data_npio, 193 194 // Misc 195 input [31:0] build_datestamp, 196 input [31:0] xadc_readback, 197 input [63:0] sfp_ports_info, 198 output reg [15:0] device_id 199); 200 `include "../../lib/rfnoc/core/ctrlport.vh" 201 202 ///////////////////////////////////////////////////////////////////////////////// 203 // 204 // FPGA Compatibility Number 205 // Rules for modifying compat number: 206 // - Major is updated when the FPGA is changed and requires a software 207 // change as a result. 208 // - Minor is updated when a new feature is added to the FPGA that does not 209 // break software compatibility. 210 // 211 ///////////////////////////////////////////////////////////////////////////////// 212 213 localparam [15:0] COMPAT_MAJOR = 16'd8; 214 localparam [15:0] COMPAT_MINOR = 16'd0; 215 ///////////////////////////////////////////////////////////////////////////////// 216 217 ///////////////////////////////////////////////////////////////////////////////// 218 // Motherboard Registers 219 ///////////////////////////////////////////////////////////////////////////////// 220 221 // Register base 222 localparam [CTRLPORT_ADDR_W-1:0] REG_BASE_MISC = 20'h0; 223 localparam [CTRLPORT_ADDR_W-1:0] REG_BASE_NPIO = 20'h200; 224 localparam [CTRLPORT_ADDR_W-1:0] REG_BASE_TIMEKEEPER = 20'h1000; 225 226 // Register region sizes. Give each register region a 256-byte window. 227 localparam REG_GLOB_ADDR_W = 8; 228 localparam REG_NPIO_ADDR_W = 8; 229 localparam REG_TIMEKEEPER_ADDR_W = 8; 230 231 // Misc Motherboard Registers 232 localparam REG_COMPAT_NUM = REG_BASE_MISC + 14'h00; 233 localparam REG_DATESTAMP = REG_BASE_MISC + 14'h04; 234 localparam REG_GIT_HASH = REG_BASE_MISC + 14'h08; 235 localparam REG_SCRATCH = REG_BASE_MISC + 14'h0C; 236 localparam REG_DEVICE_ID = REG_BASE_MISC + 14'h10; 237 localparam REG_RFNOC_INFO = REG_BASE_MISC + 14'h14; 238 localparam REG_CLOCK_CTRL = REG_BASE_MISC + 14'h18; 239 localparam REG_XADC_READBACK = REG_BASE_MISC + 14'h1C; 240 localparam REG_BUS_CLK_RATE = REG_BASE_MISC + 14'h20; 241 localparam REG_BUS_CLK_COUNT = REG_BASE_MISC + 14'h24; 242 localparam REG_SFP_PORT0_INFO = REG_BASE_MISC + 14'h28; 243 localparam REG_SFP_PORT1_INFO = REG_BASE_MISC + 14'h2C; 244 localparam REG_FP_GPIO_MASTER = REG_BASE_MISC + 14'h30; 245 localparam REG_FP_GPIO_RADIO_SRC = REG_BASE_MISC + 14'h34; 246 localparam REG_NUM_TIMEKEEPERS = REG_BASE_MISC + 14'h48; 247 248 localparam NUM_TIMEKEEPERS = 1; 249 250 wire m_ctrlport_req_wr_radio0; 251 wire m_ctrlport_req_rd_radio0; 252 wire [19:0] m_ctrlport_req_addr_radio0; 253 wire [31:0] m_ctrlport_req_data_radio0; 254 wire [3:0] m_ctrlport_req_byte_en_radio0; 255 wire m_ctrlport_req_has_time_radio0; 256 wire [63:0] m_ctrlport_req_time_radio0; 257 wire m_ctrlport_resp_ack_radio0; 258 wire [1:0] m_ctrlport_resp_status_radio0; 259 wire [31:0] m_ctrlport_resp_data_radio0; 260 `ifndef N300 261 wire m_ctrlport_req_wr_radio1; 262 wire m_ctrlport_req_rd_radio1; 263 wire [19:0] m_ctrlport_req_addr_radio1; 264 wire [31:0] m_ctrlport_req_data_radio1; 265 wire [3:0] m_ctrlport_req_byte_en_radio1; 266 wire m_ctrlport_req_has_time_radio1; 267 wire [63:0] m_ctrlport_req_time_radio1; 268 wire m_ctrlport_resp_ack_radio1; 269 wire [1:0] m_ctrlport_resp_status_radio1; 270 wire [31:0] m_ctrlport_resp_data_radio1; 271 `endif 272 273 reg [31:0] scratch_reg = 32'b0; 274 reg [31:0] bus_counter = 32'h0; 275 reg [31:0] fp_gpio_master_reg = 32'h0; 276 reg [31:0] fp_gpio_src_reg = 32'h0; 277 278 always @(posedge bus_clk) begin 279 if (bus_rst) 280 bus_counter <= 32'd0; 281 else 282 bus_counter <= bus_counter + 32'd1; 283 end 284 285 286 ///////////////////////////////////////////////////////////////////////////// 287 // 288 // Bus Bridge 289 // 290 ///////////////////////////////////////////////////////////////////////////// 291 292 // Specify timeout for CtrlPort transactions that don't complete. 293 localparam CTRLPORT_TIMEOUT = 20; 294 295 wire cp_req_wr_aclk; 296 wire cp_req_rd_aclk; 297 wire [CTRLPORT_ADDR_W-1:0] cp_req_addr_aclk; 298 wire [CTRLPORT_DATA_W-1:0] cp_req_data_aclk; 299 wire cp_resp_ack_aclk; 300 wire [ CTRLPORT_STS_W-1:0] cp_resp_status_aclk; 301 wire [CTRLPORT_DATA_W-1:0] cp_resp_data_aclk; 302 303 // Convert the AXI4-Lite transactions to CtrlPort 304 axil_ctrlport_master #( 305 .TIMEOUT (CTRLPORT_TIMEOUT), 306 .AXI_AWIDTH (REG_AWIDTH), 307 .CTRLPORT_AWIDTH (CTRLPORT_ADDR_W) 308 ) axil_ctrlport_master_i ( 309 .s_axi_aclk (s_axi_aclk), 310 .s_axi_aresetn (s_axi_aresetn), 311 .s_axi_awaddr (s_axi_awaddr), 312 .s_axi_awvalid (s_axi_awvalid), 313 .s_axi_awready (s_axi_awready), 314 .s_axi_wdata (s_axi_wdata), 315 .s_axi_wstrb (s_axi_wstrb), 316 .s_axi_wvalid (s_axi_wvalid), 317 .s_axi_wready (s_axi_wready), 318 .s_axi_bresp (s_axi_bresp), 319 .s_axi_bvalid (s_axi_bvalid), 320 .s_axi_bready (s_axi_bready), 321 .s_axi_araddr (s_axi_araddr), 322 .s_axi_arvalid (s_axi_arvalid), 323 .s_axi_arready (s_axi_arready), 324 .s_axi_rdata (s_axi_rdata), 325 .s_axi_rresp (s_axi_rresp), 326 .s_axi_rvalid (s_axi_rvalid), 327 .s_axi_rready (s_axi_rready), 328 .m_ctrlport_req_wr (cp_req_wr_aclk), 329 .m_ctrlport_req_rd (cp_req_rd_aclk), 330 .m_ctrlport_req_addr (cp_req_addr_aclk), 331 .m_ctrlport_req_portid (), 332 .m_ctrlport_req_rem_epid (), 333 .m_ctrlport_req_rem_portid (), 334 .m_ctrlport_req_data (cp_req_data_aclk), 335 .m_ctrlport_req_byte_en (), 336 .m_ctrlport_req_has_time (), 337 .m_ctrlport_req_time (), 338 .m_ctrlport_resp_ack (cp_resp_ack_aclk), 339 .m_ctrlport_resp_status (cp_resp_status_aclk), 340 .m_ctrlport_resp_data (cp_resp_data_aclk) 341 ); 342 343 wire cp_req_wr; 344 wire cp_req_rd; 345 wire [CTRLPORT_ADDR_W-1:0] cp_req_addr; 346 wire [CTRLPORT_DATA_W-1:0] cp_req_data; 347 wire cp_resp_ack; 348 wire [ CTRLPORT_STS_W-1:0] cp_resp_status; 349 wire [CTRLPORT_DATA_W-1:0] cp_resp_data; 350 351 // Cross transactions from s_axi_clk to bus_clk domain 352 ctrlport_clk_cross ctrlport_clk_cross_i ( 353 .rst (~s_axi_aresetn), 354 .s_ctrlport_clk (s_axi_aclk), 355 .s_ctrlport_req_wr (cp_req_wr_aclk), 356 .s_ctrlport_req_rd (cp_req_rd_aclk), 357 .s_ctrlport_req_addr (cp_req_addr_aclk), 358 .s_ctrlport_req_portid ({CTRLPORT_PORTID_W{1'b0}}), 359 .s_ctrlport_req_rem_epid ({CTRLPORT_REM_EPID_W{1'b0}}), 360 .s_ctrlport_req_rem_portid ({CTRLPORT_PORTID_W{1'b0}}), 361 .s_ctrlport_req_data (cp_req_data_aclk), 362 .s_ctrlport_req_byte_en ({CTRLPORT_BYTE_EN_W{1'b1}}), 363 .s_ctrlport_req_has_time (1'b0), 364 .s_ctrlport_req_time ({CTRLPORT_TIME_W{1'b0}}), 365 .s_ctrlport_resp_ack (cp_resp_ack_aclk), 366 .s_ctrlport_resp_status (cp_resp_status_aclk), 367 .s_ctrlport_resp_data (cp_resp_data_aclk), 368 .m_ctrlport_clk (bus_clk), 369 .m_ctrlport_req_wr (cp_req_wr), 370 .m_ctrlport_req_rd (cp_req_rd), 371 .m_ctrlport_req_addr (cp_req_addr), 372 .m_ctrlport_req_portid (), 373 .m_ctrlport_req_rem_epid (), 374 .m_ctrlport_req_rem_portid (), 375 .m_ctrlport_req_data (cp_req_data), 376 .m_ctrlport_req_byte_en (), 377 .m_ctrlport_req_has_time (), 378 .m_ctrlport_req_time (), 379 .m_ctrlport_resp_ack (cp_resp_ack), 380 .m_ctrlport_resp_status (cp_resp_status), 381 .m_ctrlport_resp_data (cp_resp_data) 382 ); 383 384 wire cp_glob_req_wr; 385 wire cp_glob_req_rd; 386 wire [CTRLPORT_ADDR_W-1:0] cp_glob_req_addr; 387 wire [CTRLPORT_DATA_W-1:0] cp_glob_req_data; 388 reg cp_glob_resp_ack = 1'b0; 389 reg [CTRLPORT_DATA_W-1:0] cp_glob_resp_data = 1'bX; 390 391 wire cp_npio_req_wr; 392 wire cp_npio_req_rd; 393 wire [CTRLPORT_ADDR_W-1:0] cp_npio_req_addr; 394 wire [CTRLPORT_DATA_W-1:0] cp_npio_req_data; 395 wire cp_npio_resp_ack; 396 wire [CTRLPORT_DATA_W-1:0] cp_npio_resp_data; 397 398 wire cp_tk_req_wr; 399 wire cp_tk_req_rd; 400 wire [CTRLPORT_ADDR_W-1:0] cp_tk_req_addr; 401 wire [CTRLPORT_DATA_W-1:0] cp_tk_req_data; 402 wire cp_tk_resp_ack; 403 wire [CTRLPORT_DATA_W-1:0] cp_tk_resp_data; 404 405 // Split the CtrlPort for the global registers and the timekeeper registers 406 ctrlport_decoder_param #( 407 .NUM_SLAVES (3), 408 .PORT_BASE ({ REG_BASE_TIMEKEEPER, REG_BASE_NPIO, REG_BASE_MISC }), 409 .PORT_ADDR_W ({ REG_TIMEKEEPER_ADDR_W, REG_NPIO_ADDR_W, REG_GLOB_ADDR_W }) 410 ) ctrlport_decoder_param_i ( 411 .ctrlport_clk (bus_clk), 412 .ctrlport_rst (bus_rst), 413 .s_ctrlport_req_wr (cp_req_wr), 414 .s_ctrlport_req_rd (cp_req_rd), 415 .s_ctrlport_req_addr (cp_req_addr), 416 .s_ctrlport_req_data (cp_req_data), 417 .s_ctrlport_req_byte_en ({CTRLPORT_BYTE_EN_W{1'b1}}), 418 .s_ctrlport_req_has_time (1'b0), 419 .s_ctrlport_req_time ({CTRLPORT_TIME_W{1'b0}}), 420 .s_ctrlport_resp_ack (cp_resp_ack), 421 .s_ctrlport_resp_status (cp_resp_status), 422 .s_ctrlport_resp_data (cp_resp_data), 423 .m_ctrlport_req_wr ({ cp_tk_req_wr, cp_npio_req_wr, cp_glob_req_wr }), 424 .m_ctrlport_req_rd ({ cp_tk_req_rd, cp_npio_req_rd, cp_glob_req_rd }), 425 .m_ctrlport_req_addr ({ cp_tk_req_addr, cp_npio_req_addr, cp_glob_req_addr }), 426 .m_ctrlport_req_data ({ cp_tk_req_data, cp_npio_req_data, cp_glob_req_data }), 427 .m_ctrlport_req_byte_en (), 428 .m_ctrlport_req_has_time (), 429 .m_ctrlport_req_time (), 430 .m_ctrlport_resp_ack ({ cp_tk_resp_ack, cp_npio_resp_ack, cp_glob_resp_ack }), 431 .m_ctrlport_resp_status ({2{CTRL_STS_OKAY}}), 432 .m_ctrlport_resp_data ({ cp_tk_resp_data, cp_npio_resp_data, cp_glob_resp_data }) 433 ); 434 435 // Convert NPIO from CtrlPort to RegPort 436 ctrlport_to_regport #( 437 .REG_AWIDTH (REG_AWIDTH), 438 .REG_DWIDTH (REG_DWIDTH) 439 ) ctrlport_to_regport_i ( 440 .clk (bus_clk), 441 .rst (bus_rst), 442 .s_ctrlport_req_wr (cp_npio_req_wr), 443 .s_ctrlport_req_rd (cp_npio_req_rd), 444 .s_ctrlport_req_addr (cp_npio_req_addr), 445 .s_ctrlport_req_data (cp_npio_req_data), 446 .s_ctrlport_resp_ack (cp_npio_resp_ack), 447 .s_ctrlport_resp_data (cp_npio_resp_data), 448 .reg_wr_req (reg_wr_req_npio), 449 .reg_wr_addr (reg_wr_addr_npio), 450 .reg_wr_data (reg_wr_data_npio), 451 .reg_rd_req (reg_rd_req_npio), 452 .reg_rd_addr (reg_rd_addr_npio), 453 .reg_rd_resp (reg_rd_resp_npio), 454 .reg_rd_data (reg_rd_data_npio) 455 ); 456 457 458 ///////////////////////////////////////////////////////////////////////////// 459 // 460 // Global Registers 461 // 462 ///////////////////////////////////////////////////////////////////////////// 463 464 reg b_ref_clk_locked_ms; 465 reg b_ref_clk_locked; 466 reg b_meas_clk_locked_ms; 467 reg b_meas_clk_locked; 468 469 always @ (posedge bus_clk) begin 470 if (bus_rst) begin 471 cp_glob_resp_ack <= 1'b0; 472 cp_glob_resp_data <= 'bX; 473 scratch_reg <= 32'h0; 474 fp_gpio_master_reg <= 32'h0; 475 fp_gpio_src_reg <= 32'h0; 476 pps_select <= 4'h1; 477 pps_select_sfp <= 2'h0; 478 pps_out_enb <= 1'b0; 479 ref_clk_reset <= 1'b0; 480 meas_clk_reset <= 1'b0; 481 enable_ref_clk_async <= 1'b1; 482 device_id <= 16'h0; 483 b_ref_clk_locked_ms <= 1'b0; 484 b_ref_clk_locked <= 1'b0; 485 b_meas_clk_locked_ms <= 1'b0; 486 b_meas_clk_locked <= 1'b0; 487 end else begin 488 cp_glob_resp_ack <= 1'b0; 489 490 if (cp_glob_req_wr) begin 491 cp_glob_resp_ack <= 1'b1; 492 493 case (cp_glob_req_addr[REG_GLOB_ADDR_W-1:0]) 494 REG_DEVICE_ID: 495 device_id <= cp_glob_req_data[15:0]; 496 497 REG_FP_GPIO_MASTER: 498 fp_gpio_master_reg <= cp_glob_req_data; 499 500 REG_FP_GPIO_RADIO_SRC: 501 fp_gpio_src_reg <= cp_glob_req_data; 502 503 REG_SCRATCH: 504 scratch_reg <= cp_glob_req_data; 505 506 REG_CLOCK_CTRL: begin 507 pps_select <= cp_glob_req_data[3:0]; 508 pps_out_enb <= cp_glob_req_data[4]; 509 pps_select_sfp <= cp_glob_req_data[6:5]; 510 ref_clk_reset <= cp_glob_req_data[8]; 511 meas_clk_reset <= cp_glob_req_data[12]; 512 // This bit is defined as "to disable, write '1' to bit 16" for backwards 513 // compatibility. 514 enable_ref_clk_async <= ~cp_glob_req_data[16]; 515 end 516 default: begin 517 // Don't acknowledge if the address doesn't match 518 cp_glob_resp_ack <= 1'b0; 519 end 520 endcase 521 end 522 523 // double-sync the locked bits into the bus_clk domain before using them 524 b_ref_clk_locked_ms <= ref_clk_locked; 525 b_ref_clk_locked <= b_ref_clk_locked_ms; 526 b_meas_clk_locked_ms <= meas_clk_locked; 527 b_meas_clk_locked <= b_meas_clk_locked_ms; 528 529 if (cp_glob_req_rd) begin 530 cp_glob_resp_data <= 0; // Unused bits will read 0 531 cp_glob_resp_ack <= 1'b1; 532 533 case (cp_glob_req_addr[REG_GLOB_ADDR_W-1:0]) 534 REG_DEVICE_ID: 535 cp_glob_resp_data <= {16'd0, device_id}; 536 537 REG_RFNOC_INFO: 538 cp_glob_resp_data <= {CHDR_WIDTH[15:0], RFNOC_PROTOVER[15:0]}; 539 540 REG_COMPAT_NUM: 541 cp_glob_resp_data <= {COMPAT_MAJOR, COMPAT_MINOR}; 542 543 REG_DATESTAMP: 544 cp_glob_resp_data <= build_datestamp; 545 546 REG_GIT_HASH: 547 `ifndef GIT_HASH 548 `define GIT_HASH 32'h0BADC0DE 549 `endif 550 cp_glob_resp_data <= `GIT_HASH; 551 552 REG_FP_GPIO_MASTER: 553 cp_glob_resp_data <= fp_gpio_master_reg; 554 555 REG_FP_GPIO_RADIO_SRC: 556 cp_glob_resp_data <= fp_gpio_src_reg; 557 558 REG_SCRATCH: 559 cp_glob_resp_data <= scratch_reg; 560 561 REG_CLOCK_CTRL: begin 562 cp_glob_resp_data <= 32'b0; 563 cp_glob_resp_data[3:0] <= pps_select; 564 cp_glob_resp_data[4] <= pps_out_enb; 565 cp_glob_resp_data[6:5] <= pps_select_sfp; 566 cp_glob_resp_data[8] <= ref_clk_reset; 567 cp_glob_resp_data[9] <= b_ref_clk_locked; 568 cp_glob_resp_data[12] <= meas_clk_reset; 569 cp_glob_resp_data[13] <= b_meas_clk_locked; 570 cp_glob_resp_data[16] <= ~enable_ref_clk_async; 571 end 572 573 REG_XADC_READBACK: 574 cp_glob_resp_data <= xadc_readback; 575 576 REG_BUS_CLK_RATE: 577 cp_glob_resp_data <= BUS_CLK_RATE; 578 579 REG_BUS_CLK_COUNT: 580 cp_glob_resp_data <= bus_counter; 581 582 REG_SFP_PORT0_INFO: 583 cp_glob_resp_data <= sfp_ports_info[31:0]; 584 585 REG_SFP_PORT1_INFO: 586 cp_glob_resp_data <= sfp_ports_info[63:32]; 587 588 REG_NUM_TIMEKEEPERS: 589 cp_glob_resp_data <= NUM_TIMEKEEPERS; 590 591 default: begin 592 // Don't acknowledge if the address doesn't match 593 cp_glob_resp_ack <= 1'b0; 594 end 595 endcase 596 end 597 end 598 end 599 600 601 ///////////////////////////////////////////////////////////////////// 602 // 603 // AXI Interconnect 604 // 605 ///////////////////////////////////////////////////////////////////// 606 607 localparam NUM_DRAM_FIFOS = 4; 608 localparam DRAM_FIFO_INPUT_BUFF_SIZE = 8'd13; 609 610 wire ddr3_dma_rst; 611 synchronizer #( 612 .INITIAL_VAL(1'b1) 613 ) ddr3_dma_rst_sync_i ( 614 .clk(ddr3_dma_clk), .rst(1'b0), .in(ddr3_axi_rst), .out(ddr3_dma_rst) 615 ); 616 617 // AXI4 MM buses 618 wire [0:0] dram_axi_awid [0:NUM_DRAM_FIFOS-1]; 619 wire [30:0] dram_axi_awaddr [0:NUM_DRAM_FIFOS-1]; 620 wire [7:0] dram_axi_awlen [0:NUM_DRAM_FIFOS-1]; 621 wire [2:0] dram_axi_awsize [0:NUM_DRAM_FIFOS-1]; 622 wire [1:0] dram_axi_awburst [0:NUM_DRAM_FIFOS-1]; 623 wire [0:0] dram_axi_awlock [0:NUM_DRAM_FIFOS-1]; 624 wire [3:0] dram_axi_awcache [0:NUM_DRAM_FIFOS-1]; 625 wire [2:0] dram_axi_awprot [0:NUM_DRAM_FIFOS-1]; 626 wire [3:0] dram_axi_awqos [0:NUM_DRAM_FIFOS-1]; 627 wire [3:0] dram_axi_awregion [0:NUM_DRAM_FIFOS-1]; 628 wire [0:0] dram_axi_awuser [0:NUM_DRAM_FIFOS-1]; 629 wire dram_axi_awvalid [0:NUM_DRAM_FIFOS-1]; 630 wire dram_axi_awready [0:NUM_DRAM_FIFOS-1]; 631 wire [63:0] dram_axi_wdata [0:NUM_DRAM_FIFOS-1]; 632 wire [7:0] dram_axi_wstrb [0:NUM_DRAM_FIFOS-1]; 633 wire dram_axi_wlast [0:NUM_DRAM_FIFOS-1]; 634 wire [0:0] dram_axi_wuser [0:NUM_DRAM_FIFOS-1]; 635 wire dram_axi_wvalid [0:NUM_DRAM_FIFOS-1]; 636 wire dram_axi_wready [0:NUM_DRAM_FIFOS-1]; 637 wire [0:0] dram_axi_bid [0:NUM_DRAM_FIFOS-1]; 638 wire [1:0] dram_axi_bresp [0:NUM_DRAM_FIFOS-1]; 639 wire [0:0] dram_axi_buser [0:NUM_DRAM_FIFOS-1]; 640 wire dram_axi_bvalid [0:NUM_DRAM_FIFOS-1]; 641 wire dram_axi_bready [0:NUM_DRAM_FIFOS-1]; 642 wire [0:0] dram_axi_arid [0:NUM_DRAM_FIFOS-1]; 643 wire [30:0] dram_axi_araddr [0:NUM_DRAM_FIFOS-1]; 644 wire [7:0] dram_axi_arlen [0:NUM_DRAM_FIFOS-1]; 645 wire [2:0] dram_axi_arsize [0:NUM_DRAM_FIFOS-1]; 646 wire [1:0] dram_axi_arburst [0:NUM_DRAM_FIFOS-1]; 647 wire [0:0] dram_axi_arlock [0:NUM_DRAM_FIFOS-1]; 648 wire [3:0] dram_axi_arcache [0:NUM_DRAM_FIFOS-1]; 649 wire [2:0] dram_axi_arprot [0:NUM_DRAM_FIFOS-1]; 650 wire [3:0] dram_axi_arqos [0:NUM_DRAM_FIFOS-1]; 651 wire [3:0] dram_axi_arregion [0:NUM_DRAM_FIFOS-1]; 652 wire [0:0] dram_axi_aruser [0:NUM_DRAM_FIFOS-1]; 653 wire dram_axi_arvalid [0:NUM_DRAM_FIFOS-1]; 654 wire dram_axi_arready [0:NUM_DRAM_FIFOS-1]; 655 wire [0:0] dram_axi_rid [0:NUM_DRAM_FIFOS-1]; 656 wire [63:0] dram_axi_rdata [0:NUM_DRAM_FIFOS-1]; 657 wire [1:0] dram_axi_rresp [0:NUM_DRAM_FIFOS-1]; 658 wire dram_axi_rlast [0:NUM_DRAM_FIFOS-1]; 659 wire [0:0] dram_axi_ruser [0:NUM_DRAM_FIFOS-1]; 660 wire dram_axi_rvalid [0:NUM_DRAM_FIFOS-1]; 661 wire dram_axi_rready [0:NUM_DRAM_FIFOS-1]; 662 663 axi_intercon_4x64_256_bd_wrapper axi_intercon_2x64_256_bd_i ( 664 .S00_AXI_ACLK (ddr3_dma_clk ), 665 .S00_AXI_ARESETN (~ddr3_dma_rst ), 666 .S00_AXI_AWID (dram_axi_awid [0]), 667 .S00_AXI_AWADDR ({1,b0, dram_axi_awaddr[0]}), 668 .S00_AXI_AWLEN (dram_axi_awlen [0]), 669 .S00_AXI_AWSIZE (dram_axi_awsize [0]), 670 .S00_AXI_AWBURST (dram_axi_awburst [0]), 671 .S00_AXI_AWLOCK (dram_axi_awlock [0]), 672 .S00_AXI_AWCACHE (dram_axi_awcache [0]), 673 .S00_AXI_AWPROT (dram_axi_awprot [0]), 674 .S00_AXI_AWQOS (dram_axi_awqos [0]), 675 .S00_AXI_AWREGION (dram_axi_awregion[0]), 676 .S00_AXI_AWVALID (dram_axi_awvalid [0]), 677 .S00_AXI_AWREADY (dram_axi_awready [0]), 678 .S00_AXI_WDATA (dram_axi_wdata [0]), 679 .S00_AXI_WSTRB (dram_axi_wstrb [0]), 680 .S00_AXI_WLAST (dram_axi_wlast [0]), 681 .S00_AXI_WVALID (dram_axi_wvalid [0]), 682 .S00_AXI_WREADY (dram_axi_wready [0]), 683 .S00_AXI_BID (dram_axi_bid [0]), 684 .S00_AXI_BRESP (dram_axi_bresp [0]), 685 .S00_AXI_BVALID (dram_axi_bvalid [0]), 686 .S00_AXI_BREADY (dram_axi_bready [0]), 687 .S00_AXI_ARID (dram_axi_arid [0]), 688 .S00_AXI_ARADDR ({1,b0, dram_axi_araddr[0]}), 689 .S00_AXI_ARLEN (dram_axi_arlen [0]), 690 .S00_AXI_ARSIZE (dram_axi_arsize [0]), 691 .S00_AXI_ARBURST (dram_axi_arburst [0]), 692 .S00_AXI_ARLOCK (dram_axi_arlock [0]), 693 .S00_AXI_ARCACHE (dram_axi_arcache [0]), 694 .S00_AXI_ARPROT (dram_axi_arprot [0]), 695 .S00_AXI_ARQOS (dram_axi_arqos [0]), 696 .S00_AXI_ARREGION (dram_axi_arregion[0]), 697 .S00_AXI_ARVALID (dram_axi_arvalid [0]), 698 .S00_AXI_ARREADY (dram_axi_arready [0]), 699 .S00_AXI_RID (dram_axi_rid [0]), 700 .S00_AXI_RDATA (dram_axi_rdata [0]), 701 .S00_AXI_RRESP (dram_axi_rresp [0]), 702 .S00_AXI_RLAST (dram_axi_rlast [0]), 703 .S00_AXI_RVALID (dram_axi_rvalid [0]), 704 .S00_AXI_RREADY (dram_axi_rready [0]), 705 // 706 .S01_AXI_ACLK (ddr3_dma_clk ), 707 .S01_AXI_ARESETN (~ddr3_dma_rst ), 708 .S01_AXI_AWID (dram_axi_awid [1]), 709 .S01_AXI_AWADDR ({1,b0, dram_axi_awaddr[1]}), 710 .S01_AXI_AWLEN (dram_axi_awlen [1]), 711 .S01_AXI_AWSIZE (dram_axi_awsize [1]), 712 .S01_AXI_AWBURST (dram_axi_awburst [1]), 713 .S01_AXI_AWLOCK (dram_axi_awlock [1]), 714 .S01_AXI_AWCACHE (dram_axi_awcache [1]), 715 .S01_AXI_AWPROT (dram_axi_awprot [1]), 716 .S01_AXI_AWQOS (dram_axi_awqos [1]), 717 .S01_AXI_AWREGION (dram_axi_awregion[1]), 718 .S01_AXI_AWVALID (dram_axi_awvalid [1]), 719 .S01_AXI_AWREADY (dram_axi_awready [1]), 720 .S01_AXI_WDATA (dram_axi_wdata [1]), 721 .S01_AXI_WSTRB (dram_axi_wstrb [1]), 722 .S01_AXI_WLAST (dram_axi_wlast [1]), 723 .S01_AXI_WVALID (dram_axi_wvalid [1]), 724 .S01_AXI_WREADY (dram_axi_wready [1]), 725 .S01_AXI_BID (dram_axi_bid [1]), 726 .S01_AXI_BRESP (dram_axi_bresp [1]), 727 .S01_AXI_BVALID (dram_axi_bvalid [1]), 728 .S01_AXI_BREADY (dram_axi_bready [1]), 729 .S01_AXI_ARID (dram_axi_arid [1]), 730 .S01_AXI_ARADDR ({1,b0, dram_axi_araddr[1]}), 731 .S01_AXI_ARLEN (dram_axi_arlen [1]), 732 .S01_AXI_ARSIZE (dram_axi_arsize [1]), 733 .S01_AXI_ARBURST (dram_axi_arburst [1]), 734 .S01_AXI_ARLOCK (dram_axi_arlock [1]), 735 .S01_AXI_ARCACHE (dram_axi_arcache [1]), 736 .S01_AXI_ARPROT (dram_axi_arprot [1]), 737 .S01_AXI_ARQOS (dram_axi_arqos [1]), 738 .S01_AXI_ARREGION (dram_axi_arregion[1]), 739 .S01_AXI_ARVALID (dram_axi_arvalid [1]), 740 .S01_AXI_ARREADY (dram_axi_arready [1]), 741 .S01_AXI_RID (dram_axi_rid [1]), 742 .S01_AXI_RDATA (dram_axi_rdata [1]), 743 .S01_AXI_RRESP (dram_axi_rresp [1]), 744 .S01_AXI_RLAST (dram_axi_rlast [1]), 745 .S01_AXI_RVALID (dram_axi_rvalid [1]), 746 .S01_AXI_RREADY (dram_axi_rready [1]), 747 // 748 .S02_AXI_ACLK (ddr3_dma_clk ), 749 .S02_AXI_ARESETN (~ddr3_dma_rst ), 750 .S02_AXI_AWID (dram_axi_awid [2]), 751 .S02_AXI_AWADDR ({1,b0, dram_axi_awaddr[2]}), 752 .S02_AXI_AWLEN (dram_axi_awlen [2]), 753 .S02_AXI_AWSIZE (dram_axi_awsize [2]), 754 .S02_AXI_AWBURST (dram_axi_awburst [2]), 755 .S02_AXI_AWLOCK (dram_axi_awlock [2]), 756 .S02_AXI_AWCACHE (dram_axi_awcache [2]), 757 .S02_AXI_AWPROT (dram_axi_awprot [2]), 758 .S02_AXI_AWQOS (dram_axi_awqos [2]), 759 .S02_AXI_AWREGION (dram_axi_awregion[2]), 760 .S02_AXI_AWVALID (dram_axi_awvalid [2]), 761 .S02_AXI_AWREADY (dram_axi_awready [2]), 762 .S02_AXI_WDATA (dram_axi_wdata [2]), 763 .S02_AXI_WSTRB (dram_axi_wstrb [2]), 764 .S02_AXI_WLAST (dram_axi_wlast [2]), 765 .S02_AXI_WVALID (dram_axi_wvalid [2]), 766 .S02_AXI_WREADY (dram_axi_wready [2]), 767 .S02_AXI_BID (dram_axi_bid [2]), 768 .S02_AXI_BRESP (dram_axi_bresp [2]), 769 .S02_AXI_BVALID (dram_axi_bvalid [2]), 770 .S02_AXI_BREADY (dram_axi_bready [2]), 771 .S02_AXI_ARID (dram_axi_arid [2]), 772 .S02_AXI_ARADDR ({1,b0, dram_axi_araddr[2]}), 773 .S02_AXI_ARLEN (dram_axi_arlen [2]), 774 .S02_AXI_ARSIZE (dram_axi_arsize [2]), 775 .S02_AXI_ARBURST (dram_axi_arburst [2]), 776 .S02_AXI_ARLOCK (dram_axi_arlock [2]), 777 .S02_AXI_ARCACHE (dram_axi_arcache [2]), 778 .S02_AXI_ARPROT (dram_axi_arprot [2]), 779 .S02_AXI_ARQOS (dram_axi_arqos [2]), 780 .S02_AXI_ARREGION (dram_axi_arregion[2]), 781 .S02_AXI_ARVALID (dram_axi_arvalid [2]), 782 .S02_AXI_ARREADY (dram_axi_arready [2]), 783 .S02_AXI_RID (dram_axi_rid [2]), 784 .S02_AXI_RDATA (dram_axi_rdata [2]), 785 .S02_AXI_RRESP (dram_axi_rresp [2]), 786 .S02_AXI_RLAST (dram_axi_rlast [2]), 787 .S02_AXI_RVALID (dram_axi_rvalid [2]), 788 .S02_AXI_RREADY (dram_axi_rready [2]), 789 // 790 .S03_AXI_ACLK (ddr3_dma_clk ), 791 .S03_AXI_ARESETN (~ddr3_dma_rst ), 792 .S03_AXI_AWID (dram_axi_awid [3]), 793 .S03_AXI_AWADDR ({1,b0, dram_axi_awaddr[3]}), 794 .S03_AXI_AWLEN (dram_axi_awlen [3]), 795 .S03_AXI_AWSIZE (dram_axi_awsize [3]), 796 .S03_AXI_AWBURST (dram_axi_awburst [3]), 797 .S03_AXI_AWLOCK (dram_axi_awlock [3]), 798 .S03_AXI_AWCACHE (dram_axi_awcache [3]), 799 .S03_AXI_AWPROT (dram_axi_awprot [3]), 800 .S03_AXI_AWQOS (dram_axi_awqos [3]), 801 .S03_AXI_AWREGION (dram_axi_awregion[3]), 802 .S03_AXI_AWVALID (dram_axi_awvalid [3]), 803 .S03_AXI_AWREADY (dram_axi_awready [3]), 804 .S03_AXI_WDATA (dram_axi_wdata [3]), 805 .S03_AXI_WSTRB (dram_axi_wstrb [3]), 806 .S03_AXI_WLAST (dram_axi_wlast [3]), 807 .S03_AXI_WVALID (dram_axi_wvalid [3]), 808 .S03_AXI_WREADY (dram_axi_wready [3]), 809 .S03_AXI_BID (dram_axi_bid [3]), 810 .S03_AXI_BRESP (dram_axi_bresp [3]), 811 .S03_AXI_BVALID (dram_axi_bvalid [3]), 812 .S03_AXI_BREADY (dram_axi_bready [3]), 813 .S03_AXI_ARID (dram_axi_arid [3]), 814 .S03_AXI_ARADDR ({1,b0, dram_axi_araddr[3]}), 815 .S03_AXI_ARLEN (dram_axi_arlen [3]), 816 .S03_AXI_ARSIZE (dram_axi_arsize [3]), 817 .S03_AXI_ARBURST (dram_axi_arburst [3]), 818 .S03_AXI_ARLOCK (dram_axi_arlock [3]), 819 .S03_AXI_ARCACHE (dram_axi_arcache [3]), 820 .S03_AXI_ARPROT (dram_axi_arprot [3]), 821 .S03_AXI_ARQOS (dram_axi_arqos [3]), 822 .S03_AXI_ARREGION (dram_axi_arregion[3]), 823 .S03_AXI_ARVALID (dram_axi_arvalid [3]), 824 .S03_AXI_ARREADY (dram_axi_arready [3]), 825 .S03_AXI_RID (dram_axi_rid [3]), 826 .S03_AXI_RDATA (dram_axi_rdata [3]), 827 .S03_AXI_RRESP (dram_axi_rresp [3]), 828 .S03_AXI_RLAST (dram_axi_rlast [3]), 829 .S03_AXI_RVALID (dram_axi_rvalid [3]), 830 .S03_AXI_RREADY (dram_axi_rready [3]), 831 // 832 .M00_AXI_ACLK (ddr3_axi_clk ), 833 .M00_AXI_ARESETN (~ddr3_axi_rst ), 834 .M00_AXI_AWID (ddr3_axi_awid ), 835 .M00_AXI_AWADDR (ddr3_axi_awaddr ), 836 .M00_AXI_AWLEN (ddr3_axi_awlen ), 837 .M00_AXI_AWSIZE (ddr3_axi_awsize ), 838 .M00_AXI_AWBURST (ddr3_axi_awburst ), 839 .M00_AXI_AWLOCK (ddr3_axi_awlock ), 840 .M00_AXI_AWCACHE (ddr3_axi_awcache ), 841 .M00_AXI_AWPROT (ddr3_axi_awprot ), 842 .M00_AXI_AWQOS (ddr3_axi_awqos ), 843 .M00_AXI_AWREGION ( ), 844 .M00_AXI_AWVALID (ddr3_axi_awvalid ), 845 .M00_AXI_AWREADY (ddr3_axi_awready ), 846 .M00_AXI_WDATA (ddr3_axi_wdata ), 847 .M00_AXI_WSTRB (ddr3_axi_wstrb ), 848 .M00_AXI_WLAST (ddr3_axi_wlast ), 849 .M00_AXI_WVALID (ddr3_axi_wvalid ), 850 .M00_AXI_WREADY (ddr3_axi_wready ), 851 .M00_AXI_BID (ddr3_axi_bid ), 852 .M00_AXI_BRESP (ddr3_axi_bresp ), 853 .M00_AXI_BVALID (ddr3_axi_bvalid ), 854 .M00_AXI_BREADY (ddr3_axi_bready ), 855 .M00_AXI_ARID (ddr3_axi_arid ), 856 .M00_AXI_ARADDR (ddr3_axi_araddr ), 857 .M00_AXI_ARLEN (ddr3_axi_arlen ), 858 .M00_AXI_ARSIZE (ddr3_axi_arsize ), 859 .M00_AXI_ARBURST (ddr3_axi_arburst ), 860 .M00_AXI_ARLOCK (ddr3_axi_arlock ), 861 .M00_AXI_ARCACHE (ddr3_axi_arcache ), 862 .M00_AXI_ARPROT (ddr3_axi_arprot ), 863 .M00_AXI_ARQOS (ddr3_axi_arqos ), 864 .M00_AXI_ARREGION ( ), 865 .M00_AXI_ARVALID (ddr3_axi_arvalid ), 866 .M00_AXI_ARREADY (ddr3_axi_arready ), 867 .M00_AXI_RID (ddr3_axi_rid ), 868 .M00_AXI_RDATA (ddr3_axi_rdata ), 869 .M00_AXI_RRESP (ddr3_axi_rresp ), 870 .M00_AXI_RLAST (ddr3_axi_rlast ), 871 .M00_AXI_RVALID (ddr3_axi_rvalid ), 872 .M00_AXI_RREADY (ddr3_axi_rready ) 873 ); 874 875 876 ///////////////////////////////////////////////////////////////////////////// 877 // 878 // Radios 879 // 880 ///////////////////////////////////////////////////////////////////////////// 881 882 883 wire [NUM_SPI_PER_DBOARD-1:0] sen[0:NUM_CHANNELS-1]; 884 wire sclk[0:NUM_CHANNELS-1], mosi[0:NUM_CHANNELS-1], miso[0:NUM_CHANNELS-1]; 885 // Data 886 wire [CHANNEL_WIDTH-1:0] rx_int[0:NUM_CHANNELS-1], tx_int[0:NUM_CHANNELS-1]; 887 wire [CHANNEL_WIDTH-1:0] rx_data[0:NUM_CHANNELS-1], tx_data[0:NUM_CHANNELS-1]; 888 wire db_fe_set_stb[0:NUM_CHANNELS-1]; 889 wire [7:0] db_fe_set_addr[0:NUM_CHANNELS-1]; 890 wire [31:0] db_fe_set_data[0:NUM_CHANNELS-1]; 891 wire db_fe_rb_stb[0:NUM_CHANNELS-1]; 892 wire [7:0] db_fe_rb_addr[0:NUM_CHANNELS-1]; 893 wire [63:0] db_fe_rb_data[0:NUM_CHANNELS-1]; 894 wire rx_running[0:NUM_CHANNELS-1], tx_running[0:NUM_CHANNELS-1]; 895 896 genvar i; 897 generate 898 for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: gen_gpio_control 899 assign rx_atr[i] = rx_running[i]; 900 assign tx_atr[i] = tx_running[i]; 901 end 902 endgenerate 903 904 905 ///////////////////////////////////////////////////////////////////////////////// 906 // 907 // TX/RX FrontEnd 908 // 909 ///////////////////////////////////////////////////////////////////////////////// 910 911 wire [15:0] db_gpio_in[0:NUM_CHANNELS-1]; 912 wire [15:0] db_gpio_out[0:NUM_CHANNELS-1]; 913 wire [15:0] db_gpio_ddr[0:NUM_CHANNELS-1]; 914 wire [15:0] db_gpio_fab[0:NUM_CHANNELS-1]; 915 916 wire [31:0] radio_gpio_out[0:NUM_CHANNELS-1]; 917 wire [31:0] radio_gpio_ddr[0:NUM_CHANNELS-1]; 918 wire [31:0] radio_gpio_in[0:NUM_CHANNELS-1]; 919 wire [FP_GPIO_WIDTH-1:0] radio_gpio_src_out; 920 reg [FP_GPIO_WIDTH-1:0] radio_gpio_src_out_reg; 921 wire [FP_GPIO_WIDTH-1:0] radio_gpio_src_ddr; 922 reg [FP_GPIO_WIDTH-1:0] radio_gpio_src_ddr_reg; 923 reg [FP_GPIO_WIDTH-1:0] radio_gpio_src_in; 924 wire [FP_GPIO_WIDTH-1:0] radio_gpio_sync; 925 wire [FP_GPIO_WIDTH-1:0] fp_gpio_in_int; 926 wire [FP_GPIO_WIDTH-1:0] fp_gpio_out_int; 927 wire [FP_GPIO_WIDTH-1:0] fp_gpio_ddr_int; 928 929 generate 930 for (i = 0; i < NUM_CHANNELS; i = i + 1) begin 931 // Radio Data 932 assign rx_int[i] = rx[CHANNEL_WIDTH*i +: CHANNEL_WIDTH]; 933 assign tx[CHANNEL_WIDTH*i +: CHANNEL_WIDTH] = tx_int[i]; 934 // GPIO 935 assign db_gpio_out_flat[16*i+15:16*i] = db_gpio_out[i]; 936 assign db_gpio_ddr_flat[16*i+15:16*i] = db_gpio_ddr[i]; 937 assign db_gpio_in[i] = db_gpio_in_flat[16*i+15:16*i]; 938 assign db_gpio_fab[i] = db_gpio_fab_flat[16*i+15:16*i]; 939 end 940 endgenerate 941 942 generate if (NUM_CHANNELS_PER_RADIO == 1) 943 begin 944 for (i = 0; i < NUM_DBOARDS; i = i + 1) begin 945 // SPI 946 assign miso[i] = miso_flat[i]; 947 assign sclk_flat[i] = sclk[i]; 948 assign sen_flat[NUM_SPI_PER_DBOARD*i +: NUM_SPI_PER_DBOARD] = sen[i]; 949 assign mosi_flat[i] = mosi[i]; 950 end 951 end else if (NUM_CHANNELS_PER_RADIO == 2) 952 begin 953 for (i = 0; i < NUM_DBOARDS; i = i + 1) begin 954 // SPI 955 assign miso[2*i] = miso_flat[i]; 956 assign sclk_flat[i] = sclk[2*i]; 957 assign sen_flat[NUM_SPI_PER_DBOARD*i +: NUM_SPI_PER_DBOARD] = sen[2*i]; 958 assign mosi_flat[i] = mosi[2*i]; 959 end 960 end 961 endgenerate 962 963 generate 964 for (i = 0; i < NUM_CHANNELS; i = i + 1) begin 965 n3xx_db_fe_core #( 966 .USE_CORRECTION(USE_CORRECTION), 967 .NUM_SPI_SEN(NUM_SPI_PER_DBOARD), 968 .WIDTH(CHANNEL_WIDTH) 969 ) db_fe_core_i ( 970 .clk(radio_clk), 971 .reset(radio_rst), 972 .set_stb(db_fe_set_stb[i]), 973 .set_addr(db_fe_set_addr[i]), 974 .set_data(db_fe_set_data[i]), 975 .rb_stb(db_fe_rb_stb[i]), 976 .rb_addr(db_fe_rb_addr[i]), 977 .rb_data(db_fe_rb_data[i]), 978 .tx_stb(tx_stb[i]), 979 .tx_data_in(tx_data[i]), 980 .tx_data_out(tx_int[i]), 981 .tx_running(tx_running[i]), 982 .rx_stb(rx_stb[i]), 983 .rx_data_in(rx_int[i]), 984 .rx_data_out(rx_data[i]), 985 .rx_running(rx_running[i]), 986 .misc_ins(32'h0), 987 .misc_outs(), 988 .fp_gpio_in(radio_gpio_in[i]), 989 .fp_gpio_out(radio_gpio_out[i]), 990 .fp_gpio_ddr(radio_gpio_ddr[i]), 991 .fp_gpio_fab(32'h0), 992 .db_gpio_in(db_gpio_in[i]), 993 .db_gpio_out(db_gpio_out[i]), 994 .db_gpio_ddr(db_gpio_ddr[i]), 995 .db_gpio_fab(db_gpio_fab[i]), 996 .leds(), 997 .spi_clk(radio_clk), 998 .spi_rst(radio_rst), 999 .sen(sen[i]), 1000 .sclk(sclk[i]), 1001 .mosi(mosi[i]), 1002 .miso(miso[i]) 1003 ); 1004 end 1005 endgenerate 1006 1007 // Front panel GPIOs logic 1008 // Double-sync for the GPIO inputs to the PS and to the Radio blocks. 1009 synchronizer #( 1010 .INITIAL_VAL(1'b0), .WIDTH(FP_GPIO_WIDTH) 1011 ) ps_gpio_in_sync_i ( 1012 .clk(bus_clk), .rst(1'b0), .in(fp_gpio_in_int), .out(ps_gpio_in) 1013 ); 1014 synchronizer #( 1015 .INITIAL_VAL(1'b0), .WIDTH(FP_GPIO_WIDTH) 1016 ) radio_gpio_in_sync_i ( 1017 .clk(radio_clk), .rst(1'b0), .in(fp_gpio_in_int), .out(radio_gpio_sync) 1018 ); 1019 1020 generate 1021 for (i=0; i<NUM_CHANNELS; i=i+1) begin: gen_fp_gpio_in_sync 1022 assign radio_gpio_in[i][FP_GPIO_WIDTH-1:0] = radio_gpio_sync; 1023 end 1024 endgenerate 1025 1026 // For each of the FP GPIO bits, implement four control muxes, then the IO buffer. 1027 generate 1028 for (i=0; i<FP_GPIO_WIDTH; i=i+1) begin: gpio_muxing_gen 1029 1030 // 1) Select which radio drives the output 1031 assign radio_gpio_src_out[i] = radio_gpio_out[fp_gpio_src_reg[2*i+1:2*i]][i]; 1032 always @ (posedge radio_clk) begin 1033 if (radio_rst) begin 1034 radio_gpio_src_out_reg <= 'b0; 1035 end else begin 1036 radio_gpio_src_out_reg <= radio_gpio_src_out; 1037 end 1038 end 1039 1040 // 2) Select which radio drives the direction 1041 assign radio_gpio_src_ddr[i] = radio_gpio_ddr[fp_gpio_src_reg[2*i+1:2*i]][i]; 1042 always @ (posedge radio_clk) begin 1043 if (radio_rst) begin 1044 radio_gpio_src_ddr_reg <= 'b0; 1045 end else begin 1046 radio_gpio_src_ddr_reg <= radio_gpio_src_ddr; 1047 end 1048 end 1049 1050 // 3) Select if the radio or the ps drives the output 1051 // The following is implementing a 2:1 mux in a LUT6 explicitly to avoid 1052 // glitching behavior that is introduced by unexpected Vivado synthesis. 1053 (* dont_touch = "TRUE" *) LUT3 #( 1054 .INIT(8'hCA) // Specify LUT Contents. O = ~I2&I0 | I2&I1 1055 ) mux_out_i ( 1056 .O(fp_gpio_out_int[i]), // LUT general output. Mux output 1057 .I0(radio_gpio_src_out_reg[i]), // LUT input. Input 1 1058 .I1(ps_gpio_out[i]), // LUT input. Input 2 1059 .I2(fp_gpio_master_reg[i])// LUT input. Select bit 1060 ); 1061 // 4) Select if the radio or the ps drives the direction 1062 (* dont_touch = "TRUE" *) LUT3 #( 1063 .INIT(8'hC5) // Specify LUT Contents. O = ~I2&I0 | I2&~I1 1064 ) mux_ddr_i ( 1065 .O(fp_gpio_ddr_int[i]), // LUT general output. Mux output 1066 .I0(radio_gpio_src_ddr_reg[i]), // LUT input. Input 1 1067 .I1(ps_gpio_tri[i]), // LUT input. Input 2 1068 .I2(fp_gpio_master_reg[i]) // LUT input. Select bit 1069 ); 1070 1071 // Infer the IOBUFT 1072 assign fp_gpio_inout[i] = fp_gpio_ddr_int[i] ? 1'bz : fp_gpio_out_int[i]; 1073 assign fp_gpio_in_int[i] = fp_gpio_inout[i]; 1074 end 1075 endgenerate 1076 1077 1078 ///////////////////////////////////////////////////////////////////////////// 1079 // 1080 // Timekeeper 1081 // 1082 ///////////////////////////////////////////////////////////////////////////// 1083 1084 wire [63:0] radio_time; 1085 1086 timekeeper #( 1087 .BASE_ADDR (0), // ctrlport_decoder removes the base offset 1088 .TIME_INCREMENT (1'b1) 1089 ) timekeeper_i ( 1090 .tb_clk (radio_clk), 1091 .tb_rst (radio_rst), 1092 .s_ctrlport_clk (bus_clk), 1093 .s_ctrlport_req_wr (cp_tk_req_wr), 1094 .s_ctrlport_req_rd (cp_tk_req_rd), 1095 .s_ctrlport_req_addr (cp_tk_req_addr), 1096 .s_ctrlport_req_data (cp_tk_req_data), 1097 .s_ctrlport_resp_ack (cp_tk_resp_ack), 1098 .s_ctrlport_resp_data (cp_tk_resp_data), 1099 .sample_rx_stb (rx_stb[0]), 1100 .pps (pps), 1101 .tb_timestamp (radio_time), 1102 .tb_timestamp_last_pps (), 1103 .tb_period_ns_q32 () 1104 ); 1105 1106 1107 ///////////////////////////////////////////////////////////////////////////// 1108 // 1109 // RFNoC Image Core 1110 // 1111 ///////////////////////////////////////////////////////////////////////////// 1112 1113 // Unused memory AXI ports 1114 for (i = 0; i < NUM_DRAM_FIFOS; i = i+1) begin : gen_unused_ram_signals 1115 assign dram_axi_buser[i] = 4'b0; 1116 assign dram_axi_ruser[i] = 4'b0; 1117 end 1118 1119 1120 rfnoc_image_core #( 1121 .PROTOVER(RFNOC_PROTOVER) 1122 ) rfnoc_sandbox_i ( 1123 .chdr_aclk (bus_clk ), 1124 .ctrl_aclk (clk40 ), 1125 .core_arst (bus_rst ), 1126 .device_id (device_id ), 1127 .radio_clk (radio_clk ), 1128 .dram_clk (ddr3_dma_clk), 1129 `ifndef N300 1130 .m_ctrlport_radio1_req_wr (m_ctrlport_req_wr_radio1 ), 1131 .m_ctrlport_radio1_req_rd (m_ctrlport_req_rd_radio1 ), 1132 .m_ctrlport_radio1_req_addr (m_ctrlport_req_addr_radio1 ), 1133 .m_ctrlport_radio1_req_data (m_ctrlport_req_data_radio1 ), 1134 .m_ctrlport_radio1_req_byte_en (m_ctrlport_req_byte_en_radio1 ), 1135 .m_ctrlport_radio1_req_has_time (m_ctrlport_req_has_time_radio1), 1136 .m_ctrlport_radio1_req_time (m_ctrlport_req_time_radio1 ), 1137 .m_ctrlport_radio1_resp_ack (m_ctrlport_resp_ack_radio1 ), 1138 .m_ctrlport_radio1_resp_status (m_ctrlport_resp_status_radio1 ), 1139 .m_ctrlport_radio1_resp_data (m_ctrlport_resp_data_radio1 ), 1140 `endif 1141 .m_ctrlport_radio0_req_wr (m_ctrlport_req_wr_radio0 ), 1142 .m_ctrlport_radio0_req_rd (m_ctrlport_req_rd_radio0 ), 1143 .m_ctrlport_radio0_req_addr (m_ctrlport_req_addr_radio0 ), 1144 .m_ctrlport_radio0_req_data (m_ctrlport_req_data_radio0 ), 1145 .m_ctrlport_radio0_req_byte_en (m_ctrlport_req_byte_en_radio0 ), 1146 .m_ctrlport_radio0_req_has_time (m_ctrlport_req_has_time_radio0), 1147 .m_ctrlport_radio0_req_time (m_ctrlport_req_time_radio0 ), 1148 .m_ctrlport_radio0_resp_ack (m_ctrlport_resp_ack_radio0 ), 1149 .m_ctrlport_radio0_resp_status (m_ctrlport_resp_status_radio0 ), 1150 .m_ctrlport_radio0_resp_data (m_ctrlport_resp_data_radio0 ), 1151 .axi_rst (ddr3_dma_rst), 1152 .m_axi_awid ({dram_axi_awid [3], dram_axi_awid [2], dram_axi_awid [1], dram_axi_awid [0]}), 1153 .m_axi_awaddr ({dram_axi_awaddr [3], dram_axi_awaddr [2], dram_axi_awaddr [1], dram_axi_awaddr [0]}), 1154 .m_axi_awlen ({dram_axi_awlen [3], dram_axi_awlen [2], dram_axi_awlen [1], dram_axi_awlen [0]}), 1155 .m_axi_awsize ({dram_axi_awsize [3], dram_axi_awsize [2], dram_axi_awsize [1], dram_axi_awsize [0]}), 1156 .m_axi_awburst ({dram_axi_awburst [3], dram_axi_awburst [2], dram_axi_awburst [1], dram_axi_awburst [0]}), 1157 .m_axi_awlock ({dram_axi_awlock [3], dram_axi_awlock [2], dram_axi_awlock [1], dram_axi_awlock [0]}), 1158 .m_axi_awcache ({dram_axi_awcache [3], dram_axi_awcache [2], dram_axi_awcache [1], dram_axi_awcache [0]}), 1159 .m_axi_awprot ({dram_axi_awprot [3], dram_axi_awprot [2], dram_axi_awprot [1], dram_axi_awprot [0]}), 1160 .m_axi_awqos ({dram_axi_awqos [3], dram_axi_awqos [2], dram_axi_awqos [1], dram_axi_awqos [0]}), 1161 .m_axi_awregion ({dram_axi_awregion[3], dram_axi_awregion[2], dram_axi_awregion[1], dram_axi_awregion[0]}), 1162 .m_axi_awuser ({dram_axi_awuser [3], dram_axi_awuser [2], dram_axi_awuser [1], dram_axi_awuser [0]}), 1163 .m_axi_awvalid ({dram_axi_awvalid [3], dram_axi_awvalid [2], dram_axi_awvalid [1], dram_axi_awvalid [0]}), 1164 .m_axi_awready ({dram_axi_awready [3], dram_axi_awready [2], dram_axi_awready [1], dram_axi_awready [0]}), 1165 .m_axi_wdata ({dram_axi_wdata [3], dram_axi_wdata [2], dram_axi_wdata [1], dram_axi_wdata [0]}), 1166 .m_axi_wstrb ({dram_axi_wstrb [3], dram_axi_wstrb [2], dram_axi_wstrb [1], dram_axi_wstrb [0]}), 1167 .m_axi_wlast ({dram_axi_wlast [3], dram_axi_wlast [2], dram_axi_wlast [1], dram_axi_wlast [0]}), 1168 .m_axi_wuser ({dram_axi_wuser [3], dram_axi_wuser [2], dram_axi_wuser [1], dram_axi_wuser [0]}), 1169 .m_axi_wvalid ({dram_axi_wvalid [3], dram_axi_wvalid [2], dram_axi_wvalid [1], dram_axi_wvalid [0]}), 1170 .m_axi_wready ({dram_axi_wready [3], dram_axi_wready [2], dram_axi_wready [1], dram_axi_wready [0]}), 1171 .m_axi_bid ({dram_axi_bid [3], dram_axi_bid [2], dram_axi_bid [1], dram_axi_bid [0]}), 1172 .m_axi_bresp ({dram_axi_bresp [3], dram_axi_bresp [2], dram_axi_bresp [1], dram_axi_bresp [0]}), 1173 .m_axi_buser ({dram_axi_buser [3], dram_axi_buser [2], dram_axi_buser [1], dram_axi_buser [0]}), 1174 .m_axi_bvalid ({dram_axi_bvalid [3], dram_axi_bvalid [2], dram_axi_bvalid [1], dram_axi_bvalid [0]}), 1175 .m_axi_bready ({dram_axi_bready [3], dram_axi_bready [2], dram_axi_bready [1], dram_axi_bready [0]}), 1176 .m_axi_arid ({dram_axi_arid [3], dram_axi_arid [2], dram_axi_arid [1], dram_axi_arid [0]}), 1177 .m_axi_araddr ({dram_axi_araddr [3], dram_axi_araddr [2], dram_axi_araddr [1], dram_axi_araddr [0]}), 1178 .m_axi_arlen ({dram_axi_arlen [3], dram_axi_arlen [2], dram_axi_arlen [1], dram_axi_arlen [0]}), 1179 .m_axi_arsize ({dram_axi_arsize [3], dram_axi_arsize [2], dram_axi_arsize [1], dram_axi_arsize [0]}), 1180 .m_axi_arburst ({dram_axi_arburst [3], dram_axi_arburst [2], dram_axi_arburst [1], dram_axi_arburst [0]}), 1181 .m_axi_arlock ({dram_axi_arlock [3], dram_axi_arlock [2], dram_axi_arlock [1], dram_axi_arlock [0]}), 1182 .m_axi_arcache ({dram_axi_arcache [3], dram_axi_arcache [2], dram_axi_arcache [1], dram_axi_arcache [0]}), 1183 .m_axi_arprot ({dram_axi_arprot [3], dram_axi_arprot [2], dram_axi_arprot [1], dram_axi_arprot [0]}), 1184 .m_axi_arqos ({dram_axi_arqos [3], dram_axi_arqos [2], dram_axi_arqos [1], dram_axi_arqos [0]}), 1185 .m_axi_arregion ({dram_axi_arregion[3], dram_axi_arregion[2], dram_axi_arregion[1], dram_axi_arregion[0]}), 1186 .m_axi_aruser ({dram_axi_aruser [3], dram_axi_aruser [2], dram_axi_aruser [1], dram_axi_aruser [0]}), 1187 .m_axi_arvalid ({dram_axi_arvalid [3], dram_axi_arvalid [2], dram_axi_arvalid [1], dram_axi_arvalid [0]}), 1188 .m_axi_arready ({dram_axi_arready [3], dram_axi_arready [2], dram_axi_arready [1], dram_axi_arready [0]}), 1189 .m_axi_rid ({dram_axi_rid [3], dram_axi_rid [2], dram_axi_rid [1], dram_axi_rid [0]}), 1190 .m_axi_rdata ({dram_axi_rdata [3], dram_axi_rdata [2], dram_axi_rdata [1], dram_axi_rdata [0]}), 1191 .m_axi_rresp ({dram_axi_rresp [3], dram_axi_rresp [2], dram_axi_rresp [1], dram_axi_rresp [0]}), 1192 .m_axi_rlast ({dram_axi_rlast [3], dram_axi_rlast [2], dram_axi_rlast [1], dram_axi_rlast [0]}), 1193 .m_axi_ruser ({dram_axi_ruser [3], dram_axi_ruser [2], dram_axi_ruser [1], dram_axi_ruser [0]}), 1194 .m_axi_rvalid ({dram_axi_rvalid [3], dram_axi_rvalid [2], dram_axi_rvalid [1], dram_axi_rvalid [0]}), 1195 .m_axi_rready ({dram_axi_rready [3], dram_axi_rready [2], dram_axi_rready [1], dram_axi_rready [0]}), 1196 .radio_time (radio_time ), 1197 `ifdef N320 1198 .radio_rx_stb_radio0 ( rx_stb [0] ), 1199 .radio_rx_data_radio0 ( rx_data[0] ), 1200 .radio_rx_running_radio0 ( rx_running[0] ), 1201 .radio_tx_stb_radio0 ( tx_stb [0] ), 1202 .radio_tx_data_radio0 ( tx_data[0] ), 1203 .radio_tx_running_radio0 ( tx_running[0] ), 1204 .radio_rx_stb_radio1 ( rx_stb [1] ), 1205 .radio_rx_data_radio1 ( rx_data[1] ), 1206 .radio_rx_running_radio1 ( rx_running[1] ), 1207 .radio_tx_stb_radio1 ( tx_stb [1] ), 1208 .radio_tx_data_radio1 ( tx_data[1] ), 1209 .radio_tx_running_radio1 ( tx_running[1] ), 1210 `endif 1211 `ifndef N320 1212 .radio_rx_stb_radio0 ({rx_stb[1], rx_stb [0] }), 1213 .radio_rx_data_radio0 ({rx_data[1], rx_data[0] }), 1214 .radio_rx_running_radio0 ({rx_running[1], rx_running[0]}), 1215 .radio_tx_stb_radio0 ({tx_stb[1], tx_stb [0] }), 1216 .radio_tx_data_radio0 ({tx_data[1], tx_data[0] }), 1217 .radio_tx_running_radio0 ({tx_running[1], tx_running[0]}), 1218 `endif 1219 `ifdef N310 1220 .radio_rx_stb_radio1 ({rx_stb[3], rx_stb [2] }), 1221 .radio_rx_data_radio1 ({rx_data[3], rx_data[2] }), 1222 .radio_rx_running_radio1 ({rx_running[3], rx_running[2]}), 1223 .radio_tx_stb_radio1 ({tx_stb[3], tx_stb [2] }), 1224 .radio_tx_data_radio1 ({tx_data[3], tx_data[2] }), 1225 .radio_tx_running_radio1 ({tx_running[3], tx_running[2]}), 1226 `endif 1227 .s_eth0_tdata (e2v0_tdata ), 1228 .s_eth0_tlast (e2v0_tlast ), 1229 .s_eth0_tvalid (e2v0_tvalid), 1230 .s_eth0_tready (e2v0_tready), 1231 .m_eth0_tdata (v2e0_tdata ), 1232 .m_eth0_tlast (v2e0_tlast ), 1233 .m_eth0_tvalid (v2e0_tvalid), 1234 .m_eth0_tready (v2e0_tready), 1235 .s_eth1_tdata (e2v1_tdata ), 1236 .s_eth1_tlast (e2v1_tlast ), 1237 .s_eth1_tvalid (e2v1_tvalid), 1238 .s_eth1_tready (e2v1_tready), 1239 .m_eth1_tdata (v2e1_tdata ), 1240 .m_eth1_tlast (v2e1_tlast ), 1241 .m_eth1_tvalid (v2e1_tvalid), 1242 .m_eth1_tready (v2e1_tready), 1243 .s_dma_tdata (s_dma_tdata), 1244 .s_dma_tlast (s_dma_tlast), 1245 .s_dma_tvalid (s_dma_tvalid), 1246 .s_dma_tready (s_dma_tready), 1247 .m_dma_tdata (m_dma_tdata), 1248 .m_dma_tlast (m_dma_tlast), 1249 .m_dma_tvalid (m_dma_tvalid), 1250 .m_dma_tready (m_dma_tready) 1251 ); 1252 1253 1254 //--------------------------------------------------------------------------- 1255 // Convert Control Port to Settings Bus 1256 //--------------------------------------------------------------------------- 1257`ifdef N320 1258 ctrlport_to_settings_bus # ( 1259 .NUM_PORTS (NUM_CHANNELS_PER_RADIO), 1260 .USE_TIME (1) 1261 ) ctrlport0_to_settings_bus_i ( 1262 .ctrlport_clk (radio_clk), 1263 .ctrlport_rst (radio_rst), 1264 .s_ctrlport_req_wr (m_ctrlport_req_wr_radio0), 1265 .s_ctrlport_req_rd (m_ctrlport_req_rd_radio0), 1266 .s_ctrlport_req_addr (m_ctrlport_req_addr_radio0), 1267 .s_ctrlport_req_data (m_ctrlport_req_data_radio0), 1268 .s_ctrlport_req_has_time (m_ctrlport_req_has_time_radio0), 1269 .s_ctrlport_req_time (m_ctrlport_req_time_radio0), 1270 .s_ctrlport_resp_ack (m_ctrlport_resp_ack_radio0), 1271 .s_ctrlport_resp_data (m_ctrlport_resp_data_radio0), 1272 .set_data (db_fe_set_data[0]), 1273 .set_addr (db_fe_set_addr[0]), 1274 .set_stb (db_fe_set_stb[0]), 1275 .set_time (), 1276 .set_has_time (), 1277 .rb_stb (db_fe_rb_stb[0]), 1278 .rb_addr (db_fe_rb_addr[0]), 1279 .rb_data (db_fe_rb_data[0]), 1280 .timestamp (radio_time) 1281 ); 1282 1283 ctrlport_to_settings_bus # ( 1284 .NUM_PORTS (NUM_CHANNELS_PER_RADIO), 1285 .USE_TIME (1) 1286 ) ctrlport1_to_settings_bus_i ( 1287 .ctrlport_clk (radio_clk), 1288 .ctrlport_rst (radio_rst), 1289 .s_ctrlport_req_wr (m_ctrlport_req_wr_radio1), 1290 .s_ctrlport_req_rd (m_ctrlport_req_rd_radio1), 1291 .s_ctrlport_req_addr (m_ctrlport_req_addr_radio1), 1292 .s_ctrlport_req_data (m_ctrlport_req_data_radio1), 1293 .s_ctrlport_req_has_time (m_ctrlport_req_has_time_radio1), 1294 .s_ctrlport_req_time (m_ctrlport_req_time_radio1), 1295 .s_ctrlport_resp_ack (m_ctrlport_resp_ack_radio1), 1296 .s_ctrlport_resp_data (m_ctrlport_resp_data_radio1), 1297 .set_data (db_fe_set_data[1]), 1298 .set_addr (db_fe_set_addr[1]), 1299 .set_stb (db_fe_set_stb[1]), 1300 .set_time (), 1301 .set_has_time (), 1302 .rb_stb (db_fe_rb_stb[1]), 1303 .rb_addr (db_fe_rb_addr[1]), 1304 .rb_data (db_fe_rb_data[1]), 1305 .timestamp (radio_time) 1306 ); 1307`endif 1308 1309 1310`ifndef N320 1311 ctrlport_to_settings_bus # ( 1312 .NUM_PORTS (NUM_CHANNELS_PER_RADIO), 1313 .USE_TIME (1) 1314 ) ctrlport0_to_settings_bus_i ( 1315 .ctrlport_clk (radio_clk), 1316 .ctrlport_rst (radio_rst), 1317 .s_ctrlport_req_wr (m_ctrlport_req_wr_radio0), 1318 .s_ctrlport_req_rd (m_ctrlport_req_rd_radio0), 1319 .s_ctrlport_req_addr (m_ctrlport_req_addr_radio0), 1320 .s_ctrlport_req_data (m_ctrlport_req_data_radio0), 1321 .s_ctrlport_req_has_time (m_ctrlport_req_has_time_radio0), 1322 .s_ctrlport_req_time (m_ctrlport_req_time_radio0), 1323 .s_ctrlport_resp_ack (m_ctrlport_resp_ack_radio0), 1324 .s_ctrlport_resp_data (m_ctrlport_resp_data_radio0), 1325 .set_data ({db_fe_set_data[1], db_fe_set_data[0]}), 1326 .set_addr ({db_fe_set_addr[1], db_fe_set_addr[0]}), 1327 .set_stb ({db_fe_set_stb[1], db_fe_set_stb[0] }), 1328 .set_time (), 1329 .set_has_time (), 1330 .rb_stb ({db_fe_rb_stb[1], db_fe_rb_stb[0] }), 1331 .rb_addr ({db_fe_rb_addr[1], db_fe_rb_addr[0] }), 1332 .rb_data ({db_fe_rb_data[1], db_fe_rb_data[0] }), 1333 .timestamp (radio_time) 1334 ); 1335 1336 `ifndef N300 1337 ctrlport_to_settings_bus # ( 1338 .NUM_PORTS (NUM_CHANNELS_PER_RADIO), 1339 .USE_TIME (1) 1340 ) ctrlport1_to_settings_bus_i ( 1341 .ctrlport_clk (radio_clk), 1342 .ctrlport_rst (radio_rst), 1343 .s_ctrlport_req_wr (m_ctrlport_req_wr_radio1), 1344 .s_ctrlport_req_rd (m_ctrlport_req_rd_radio1), 1345 .s_ctrlport_req_addr (m_ctrlport_req_addr_radio1), 1346 .s_ctrlport_req_data (m_ctrlport_req_data_radio1), 1347 .s_ctrlport_req_has_time (m_ctrlport_req_has_time_radio1), 1348 .s_ctrlport_req_time (m_ctrlport_req_time_radio1), 1349 .s_ctrlport_resp_ack (m_ctrlport_resp_ack_radio1), 1350 .s_ctrlport_resp_data (m_ctrlport_resp_data_radio1), 1351 .set_data ({db_fe_set_data[3], db_fe_set_data[2]}), 1352 .set_addr ({db_fe_set_addr[3], db_fe_set_addr[2]}), 1353 .set_stb ({db_fe_set_stb[3], db_fe_set_stb[2] }), 1354 .set_time (), 1355 .set_has_time (), 1356 .rb_stb ({db_fe_rb_stb[3], db_fe_rb_stb[2] }), 1357 .rb_addr ({db_fe_rb_addr[3], db_fe_rb_addr[2] }), 1358 .rb_data ({db_fe_rb_data[3], db_fe_rb_data[2] }), 1359 .timestamp (radio_time) 1360 ); 1361 `endif 1362`endif 1363 1364endmodule //n3xx_core 1365