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Searched refs:REG_R3 (Results 1 – 25 of 380) sorted by relevance

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/dports/devel/hs-ormolu/ormolu-0.4.0.0/_cabal_deps/ghc-lib-parser-9.2.1.20211101/includes/stg/
H A DMachRegs.h27 #undef REG_R3
169 #define REG_R3 rsi macro
311 #define REG_R3 r16 macro
448 #define REG_R3 l3 macro
521 #define REG_R3 r9 macro
578 #define REG_R3 r24 macro
632 #define REG_R3 r13 macro
704 #define REG_R3 s6 macro
770 # elif defined(REG_R3)
/dports/devel/hs-hlint/hlint-3.3.4/_cabal_deps/ghc-lib-parser-9.0.1.20210324/includes/stg/
H A DMachRegs.h27 #undef REG_R3
169 #define REG_R3 rsi macro
311 #define REG_R3 r16 macro
448 #define REG_R3 l3 macro
521 #define REG_R3 r9 macro
578 #define REG_R3 r24 macro
632 #define REG_R3 r13 macro
708 # elif defined(REG_R3)
/dports/devel/hs-haskell-language-server/haskell-language-server-1.4.0/_cabal_deps/ghc-lib-parser-8.10.7.20210828/includes/stg/
H A DMachRegs.h27 #undef REG_R3
167 #define REG_R3 rsi macro
309 #define REG_R3 r16 macro
446 #define REG_R3 l3 macro
519 #define REG_R3 r9 macro
576 #define REG_R3 r24 macro
630 #define REG_R3 r13 macro
706 # elif defined(REG_R3)
/dports/lang/ghc/ghc-8.10.7/includes/stg/
H A DMachRegs.h27 #undef REG_R3
167 #define REG_R3 rsi macro
309 #define REG_R3 r16 macro
446 #define REG_R3 l3 macro
519 #define REG_R3 r9 macro
576 #define REG_R3 r24 macro
630 #define REG_R3 r13 macro
706 # elif defined(REG_R3)
/dports/emulators/mess/mame-mame0226/src/devices/cpu/unsp/
H A Dunsp_fxxx.cpp77 m_core->m_r[REG_R3] = (uint16_t)lres; in execute_fxxx_000_group()
218 m_core->m_r[REG_PC] = m_core->m_r[REG_R3]; in execute_fxxx_011_group()
258 m_core->m_r[REG_R3] = (uint16_t)lres; in execute_fxxx_100_group()
275 m_core->m_divq_dividend = (m_core->m_r[REG_R4] << 16) | m_core->m_r[REG_R3]; in execute_divq()
291 m_core->m_r[REG_R3] = (uint16_t)m_core->m_divq_dividend; in execute_divq()
328 std::swap<uint32_t>(m_core->m_r[REG_R3], m_core->m_secbank[REG_SR3]); in execute_fxxx_101_group()
339 std::swap<uint32_t>(m_core->m_r[REG_R3], m_core->m_secbank[REG_SR3]); in execute_fxxx_101_group()
366 uint32_t addr = m_core->m_r[REG_R3] | ((m_core->m_r[REG_R4] & 0x3f) << 16); in execute_fxxx_101_group()
552 m_core->m_r[REG_R3] = (uint16_t)lres; in execute_muls_ss()
H A Dunsp_exxx.cpp240 m_core->m_r[REG_R3] = (uint16_t)lres; in execute_exxx_group()
287 m_core->m_r[REG_R3] |= (uint16_t)res; in execute_exxx_group()
289 LOGMASKED(LOG_UNSP_SHIFTS, "result: %04x%04x\n", m_core->m_r[REG_R4], m_core->m_r[REG_R3]); in execute_exxx_group()
312 m_core->m_r[REG_R3] = (uint16_t)res; in execute_exxx_group()
314 LOGMASKED(LOG_UNSP_SHIFTS, "result: %04x%04x\n", m_core->m_r[REG_R4], m_core->m_r[REG_R3]); in execute_exxx_group()
337 m_core->m_r[REG_R3] |= (uint16_t)res; in execute_exxx_group()
339 LOGMASKED(LOG_UNSP_SHIFTS, "result: %04x%04x\n", m_core->m_r[REG_R4], m_core->m_r[REG_R3]); in execute_exxx_group()
/dports/emulators/mame/mame-mame0226/src/devices/cpu/unsp/
H A Dunsp_fxxx.cpp77 m_core->m_r[REG_R3] = (uint16_t)lres; in execute_fxxx_000_group()
218 m_core->m_r[REG_PC] = m_core->m_r[REG_R3]; in execute_fxxx_011_group()
258 m_core->m_r[REG_R3] = (uint16_t)lres; in execute_fxxx_100_group()
275 m_core->m_divq_dividend = (m_core->m_r[REG_R4] << 16) | m_core->m_r[REG_R3]; in execute_divq()
291 m_core->m_r[REG_R3] = (uint16_t)m_core->m_divq_dividend; in execute_divq()
328 std::swap<uint32_t>(m_core->m_r[REG_R3], m_core->m_secbank[REG_SR3]); in execute_fxxx_101_group()
339 std::swap<uint32_t>(m_core->m_r[REG_R3], m_core->m_secbank[REG_SR3]); in execute_fxxx_101_group()
366 uint32_t addr = m_core->m_r[REG_R3] | ((m_core->m_r[REG_R4] & 0x3f) << 16); in execute_fxxx_101_group()
552 m_core->m_r[REG_R3] = (uint16_t)lres; in execute_muls_ss()
H A Dunsp_exxx.cpp240 m_core->m_r[REG_R3] = (uint16_t)lres; in execute_exxx_group()
287 m_core->m_r[REG_R3] |= (uint16_t)res; in execute_exxx_group()
289 LOGMASKED(LOG_UNSP_SHIFTS, "result: %04x%04x\n", m_core->m_r[REG_R4], m_core->m_r[REG_R3]); in execute_exxx_group()
312 m_core->m_r[REG_R3] = (uint16_t)res; in execute_exxx_group()
314 LOGMASKED(LOG_UNSP_SHIFTS, "result: %04x%04x\n", m_core->m_r[REG_R4], m_core->m_r[REG_R3]); in execute_exxx_group()
337 m_core->m_r[REG_R3] |= (uint16_t)res; in execute_exxx_group()
339 LOGMASKED(LOG_UNSP_SHIFTS, "result: %04x%04x\n", m_core->m_r[REG_R4], m_core->m_r[REG_R3]); in execute_exxx_group()
/dports/lang/ghc/ghc-8.8.4-boot/includes/stg/
H A DMachRegs.h27 #undef REG_R3
167 #define REG_R3 rsi macro
309 #define REG_R3 r16 macro
443 #define REG_R3 l3 macro
516 #define REG_R3 r9 macro
573 #define REG_R3 r24 macro
631 # elif defined(REG_R3)
/dports/lang/zig/zig-0.9.0/lib/libc/include/arm-linux-gnueabi/sys/
H A Ducontext.h53 REG_R3 = 3, enumerator
54 # define REG_R3 REG_R3 macro
/dports/lang/zig/zig-0.9.0/lib/libc/include/armeb-linux-gnueabihf/sys/
H A Ducontext.h53 REG_R3 = 3, enumerator
54 # define REG_R3 REG_R3 macro
/dports/lang/zig-devel/zig-0.9.0/lib/libc/include/arm-linux-gnueabihf/sys/
H A Ducontext.h53 REG_R3 = 3, enumerator
54 # define REG_R3 REG_R3 macro
/dports/lang/zig-devel/zig-0.9.0/lib/libc/include/armeb-linux-gnueabi/sys/
H A Ducontext.h53 REG_R3 = 3, enumerator
54 # define REG_R3 REG_R3 macro
/dports/lang/zig-devel/zig-0.9.0/lib/libc/include/armeb-linux-gnueabihf/sys/
H A Ducontext.h53 REG_R3 = 3, enumerator
54 # define REG_R3 REG_R3 macro
/dports/lang/zig-devel/zig-0.9.0/lib/libc/include/arm-linux-gnueabi/sys/
H A Ducontext.h53 REG_R3 = 3, enumerator
54 # define REG_R3 REG_R3 macro
/dports/lang/zig/zig-0.9.0/lib/libc/include/arm-linux-gnueabihf/sys/
H A Ducontext.h53 REG_R3 = 3, enumerator
54 # define REG_R3 REG_R3 macro
/dports/lang/zig/zig-0.9.0/lib/libc/include/armeb-linux-gnueabi/sys/
H A Ducontext.h53 REG_R3 = 3, enumerator
54 # define REG_R3 REG_R3 macro
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gcc/gcc/config/dsp16xx/
H A Ddsp16xx.h437 #define REG_R3 12 macro
495 #define IS_ADDRESS_REGISTER(REGNO) ((REGNO) >= REG_R0 && (REGNO) <= REG_R3)
546 REG_C1, REG_C2, REG_R3, \
570 REG_R3, REG_YBASE, REG_PT, REG_C0, REG_C1, REG_C2, \
653 #define STACK_POINTER_REGNUM REG_R3
958 (((REGNO) >= REG_R0 && (REGNO) < REG_R3 + 1) || ((unsigned) reg_renumber[REGNO] >= REG_R0 \
959 && (unsigned) reg_renumber[REGNO] < REG_R3 + 1))
1318 ((REGNO (X) >= REG_R0 && REGNO (X) < REG_R3 + 1 ) \
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gcc/gcc/config/dsp16xx/
H A Ddsp16xx.h437 #define REG_R3 12 macro
495 #define IS_ADDRESS_REGISTER(REGNO) ((REGNO) >= REG_R0 && (REGNO) <= REG_R3)
546 REG_C1, REG_C2, REG_R3, \
570 REG_R3, REG_YBASE, REG_PT, REG_C0, REG_C1, REG_C2, \
653 #define STACK_POINTER_REGNUM REG_R3
958 (((REGNO) >= REG_R0 && (REGNO) < REG_R3 + 1) || ((unsigned) reg_renumber[REGNO] >= REG_R0 \
959 && (unsigned) reg_renumber[REGNO] < REG_R3 + 1))
1318 ((REGNO (X) >= REG_R0 && REGNO (X) < REG_R3 + 1 ) \
/dports/net/google-cloud-sdk-app-engine-go/platform/google_appengine/goroot-1.9/src/cmd/internal/obj/s390x/
H A Dobjz.go381 q.To.Reg = REG_R3
386 q.From.Reg = REG_R3
398 q.From.Reg = REG_R3
436 q.To.Reg = REG_R3
538 p.To.Reg = REG_R3
553 p.From.Reg = REG_R3
584 p.From.Reg = REG_R3
609 p.From.Reg = REG_R3
629 p.From.Reg = REG_R3
/dports/lang/go-devel/go-dragonfly-amd64-bootstrap/src/cmd/internal/obj/s390x/
H A Dobjz.go407 q.To.Reg = REG_R3
412 q.From.Reg = REG_R3
424 q.From.Reg = REG_R3
462 q.To.Reg = REG_R3
577 p.To.Reg = REG_R3
593 p.From.Reg = REG_R3
613 p.From.Reg = REG_R3
638 p.From.Reg = REG_R3
658 p.From.Reg = REG_R3
/dports/devel/libfirm/libfirm-1.21.0/ir/be/arm/
H A Darm_cconv.c45 &arm_registers[REG_R3]
52 &arm_registers[REG_R3]
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/arm/nwfpe/
H A Dfpmodule.h30 #define REG_R3 3 macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/arm/nwfpe/
H A Dfpmodule.h30 #define REG_R3 3 macro
/dports/multimedia/libv4l/linux-5.13-rc2/arch/arm/nwfpe/
H A Dfpmodule.h30 #define REG_R3 3 macro

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