1 /* ----------------------------------------------------------------------------- 2 * 3 * (c) The GHC Team, 1998-2014 4 * 5 * Registers used in STG code. Might or might not correspond to 6 * actual machine registers. 7 * 8 * Do not #include this file directly: #include "Rts.h" instead. 9 * 10 * To understand the structure of the RTS headers, see the wiki: 11 * https://gitlab.haskell.org/ghc/ghc/wikis/commentary/source-tree/includes 12 * 13 * ---------------------------------------------------------------------------*/ 14 15 #pragma once 16 17 /* This file is #included into Haskell code in the compiler: #defines 18 * only in here please. 19 */ 20 21 /* 22 * Undefine these as a precaution: some of them were found to be 23 * defined by system headers on ARM/Linux. 24 */ 25 #undef REG_R1 26 #undef REG_R2 27 #undef REG_R3 28 #undef REG_R4 29 #undef REG_R5 30 #undef REG_R6 31 #undef REG_R7 32 #undef REG_R8 33 #undef REG_R9 34 #undef REG_R10 35 36 /* 37 * Defining MACHREGS_NO_REGS to 1 causes no global registers to be used. 38 * MACHREGS_NO_REGS is typically controlled by NO_REGS, which is 39 * typically defined by GHC, via a command-line option passed to gcc, 40 * when the -funregisterised flag is given. 41 * 42 * NB. When MACHREGS_NO_REGS to 1, calling & return conventions may be 43 * different. For example, all function arguments will be passed on 44 * the stack, and components of an unboxed tuple will be returned on 45 * the stack rather than in registers. 46 */ 47 #if MACHREGS_NO_REGS == 1 48 49 /* Nothing */ 50 51 #elif MACHREGS_NO_REGS == 0 52 53 /* ---------------------------------------------------------------------------- 54 Caller saves and callee-saves regs. 55 56 Caller-saves regs have to be saved around C-calls made from STG 57 land, so this file defines CALLER_SAVES_<reg> for each <reg> that 58 is designated caller-saves in that machine's C calling convention. 59 60 As it stands, the only registers that are ever marked caller saves 61 are the RX, FX, DX and USER registers; as a result, if you 62 decide to caller save a system register (e.g. SP, HP, etc), note that 63 this code path is completely untested! -- EZY 64 65 See Note [Register parameter passing] for details. 66 -------------------------------------------------------------------------- */ 67 68 /* ----------------------------------------------------------------------------- 69 The x86 register mapping 70 71 Ok, we've only got 6 general purpose registers, a frame pointer and a 72 stack pointer. \tr{%eax} and \tr{%edx} are return values from C functions, 73 hence they get trashed across ccalls and are caller saves. \tr{%ebx}, 74 \tr{%esi}, \tr{%edi}, \tr{%ebp} are all callee-saves. 75 76 Reg STG-Reg 77 --------------- 78 ebx Base 79 ebp Sp 80 esi R1 81 edi Hp 82 83 Leaving SpLim out of the picture. 84 -------------------------------------------------------------------------- */ 85 86 #if defined(MACHREGS_i386) 87 88 #define REG(x) __asm__("%" #x) 89 90 #if !defined(not_doing_dynamic_linking) 91 #define REG_Base ebx 92 #endif 93 #define REG_Sp ebp 94 95 #if !defined(STOLEN_X86_REGS) 96 #define STOLEN_X86_REGS 4 97 #endif 98 99 #if STOLEN_X86_REGS >= 3 100 # define REG_R1 esi 101 #endif 102 103 #if STOLEN_X86_REGS >= 4 104 # define REG_Hp edi 105 #endif 106 #define REG_MachSp esp 107 108 #define REG_XMM1 xmm0 109 #define REG_XMM2 xmm1 110 #define REG_XMM3 xmm2 111 #define REG_XMM4 xmm3 112 113 #define REG_YMM1 ymm0 114 #define REG_YMM2 ymm1 115 #define REG_YMM3 ymm2 116 #define REG_YMM4 ymm3 117 118 #define REG_ZMM1 zmm0 119 #define REG_ZMM2 zmm1 120 #define REG_ZMM3 zmm2 121 #define REG_ZMM4 zmm3 122 123 #define MAX_REAL_VANILLA_REG 1 /* always, since it defines the entry conv */ 124 #define MAX_REAL_FLOAT_REG 0 125 #define MAX_REAL_DOUBLE_REG 0 126 #define MAX_REAL_LONG_REG 0 127 #define MAX_REAL_XMM_REG 4 128 #define MAX_REAL_YMM_REG 4 129 #define MAX_REAL_ZMM_REG 4 130 131 /* ----------------------------------------------------------------------------- 132 The x86-64 register mapping 133 134 %rax caller-saves, don't steal this one 135 %rbx YES 136 %rcx arg reg, caller-saves 137 %rdx arg reg, caller-saves 138 %rsi arg reg, caller-saves 139 %rdi arg reg, caller-saves 140 %rbp YES (our *prime* register) 141 %rsp (unavailable - stack pointer) 142 %r8 arg reg, caller-saves 143 %r9 arg reg, caller-saves 144 %r10 caller-saves 145 %r11 caller-saves 146 %r12 YES 147 %r13 YES 148 %r14 YES 149 %r15 YES 150 151 %xmm0-7 arg regs, caller-saves 152 %xmm8-15 caller-saves 153 154 Use the caller-saves regs for Rn, because we don't always have to 155 save those (as opposed to Sp/Hp/SpLim etc. which always have to be 156 saved). 157 158 --------------------------------------------------------------------------- */ 159 160 #elif defined(MACHREGS_x86_64) 161 162 #define REG(x) __asm__("%" #x) 163 164 #define REG_Base r13 165 #define REG_Sp rbp 166 #define REG_Hp r12 167 #define REG_R1 rbx 168 #define REG_R2 r14 169 #define REG_R3 rsi 170 #define REG_R4 rdi 171 #define REG_R5 r8 172 #define REG_R6 r9 173 #define REG_SpLim r15 174 #define REG_MachSp rsp 175 176 /* 177 Map both Fn and Dn to register xmmn so that we can pass a function any 178 combination of up to six Float# or Double# arguments without touching 179 the stack. See Note [Overlapping global registers] for implications. 180 */ 181 182 #define REG_F1 xmm1 183 #define REG_F2 xmm2 184 #define REG_F3 xmm3 185 #define REG_F4 xmm4 186 #define REG_F5 xmm5 187 #define REG_F6 xmm6 188 189 #define REG_D1 xmm1 190 #define REG_D2 xmm2 191 #define REG_D3 xmm3 192 #define REG_D4 xmm4 193 #define REG_D5 xmm5 194 #define REG_D6 xmm6 195 196 #define REG_XMM1 xmm1 197 #define REG_XMM2 xmm2 198 #define REG_XMM3 xmm3 199 #define REG_XMM4 xmm4 200 #define REG_XMM5 xmm5 201 #define REG_XMM6 xmm6 202 203 #define REG_YMM1 ymm1 204 #define REG_YMM2 ymm2 205 #define REG_YMM3 ymm3 206 #define REG_YMM4 ymm4 207 #define REG_YMM5 ymm5 208 #define REG_YMM6 ymm6 209 210 #define REG_ZMM1 zmm1 211 #define REG_ZMM2 zmm2 212 #define REG_ZMM3 zmm3 213 #define REG_ZMM4 zmm4 214 #define REG_ZMM5 zmm5 215 #define REG_ZMM6 zmm6 216 217 #if !defined(mingw32_HOST_OS) 218 #define CALLER_SAVES_R3 219 #define CALLER_SAVES_R4 220 #endif 221 #define CALLER_SAVES_R5 222 #define CALLER_SAVES_R6 223 224 #define CALLER_SAVES_F1 225 #define CALLER_SAVES_F2 226 #define CALLER_SAVES_F3 227 #define CALLER_SAVES_F4 228 #define CALLER_SAVES_F5 229 #if !defined(mingw32_HOST_OS) 230 #define CALLER_SAVES_F6 231 #endif 232 233 #define CALLER_SAVES_D1 234 #define CALLER_SAVES_D2 235 #define CALLER_SAVES_D3 236 #define CALLER_SAVES_D4 237 #define CALLER_SAVES_D5 238 #if !defined(mingw32_HOST_OS) 239 #define CALLER_SAVES_D6 240 #endif 241 242 #define CALLER_SAVES_XMM1 243 #define CALLER_SAVES_XMM2 244 #define CALLER_SAVES_XMM3 245 #define CALLER_SAVES_XMM4 246 #define CALLER_SAVES_XMM5 247 #if !defined(mingw32_HOST_OS) 248 #define CALLER_SAVES_XMM6 249 #endif 250 251 #define CALLER_SAVES_YMM1 252 #define CALLER_SAVES_YMM2 253 #define CALLER_SAVES_YMM3 254 #define CALLER_SAVES_YMM4 255 #define CALLER_SAVES_YMM5 256 #if !defined(mingw32_HOST_OS) 257 #define CALLER_SAVES_YMM6 258 #endif 259 260 #define CALLER_SAVES_ZMM1 261 #define CALLER_SAVES_ZMM2 262 #define CALLER_SAVES_ZMM3 263 #define CALLER_SAVES_ZMM4 264 #define CALLER_SAVES_ZMM5 265 #if !defined(mingw32_HOST_OS) 266 #define CALLER_SAVES_ZMM6 267 #endif 268 269 #define MAX_REAL_VANILLA_REG 6 270 #define MAX_REAL_FLOAT_REG 6 271 #define MAX_REAL_DOUBLE_REG 6 272 #define MAX_REAL_LONG_REG 0 273 #define MAX_REAL_XMM_REG 6 274 #define MAX_REAL_YMM_REG 6 275 #define MAX_REAL_ZMM_REG 6 276 277 /* ----------------------------------------------------------------------------- 278 The PowerPC register mapping 279 280 0 system glue? (caller-save, volatile) 281 1 SP (callee-save, non-volatile) 282 2 AIX, powerpc64-linux: 283 RTOC (a strange special case) 284 powerpc32-linux: 285 reserved for use by system 286 287 3-10 args/return (caller-save, volatile) 288 11,12 system glue? (caller-save, volatile) 289 13 on 64-bit: reserved for thread state pointer 290 on 32-bit: (callee-save, non-volatile) 291 14-31 (callee-save, non-volatile) 292 293 f0 (caller-save, volatile) 294 f1-f13 args/return (caller-save, volatile) 295 f14-f31 (callee-save, non-volatile) 296 297 \tr{14}--\tr{31} are wonderful callee-save registers on all ppc OSes. 298 \tr{0}--\tr{12} are caller-save registers. 299 300 \tr{%f14}--\tr{%f31} are callee-save floating-point registers. 301 302 We can do the Whole Business with callee-save registers only! 303 -------------------------------------------------------------------------- */ 304 305 #elif defined(MACHREGS_powerpc) 306 307 #define REG(x) __asm__(#x) 308 309 #define REG_R1 r14 310 #define REG_R2 r15 311 #define REG_R3 r16 312 #define REG_R4 r17 313 #define REG_R5 r18 314 #define REG_R6 r19 315 #define REG_R7 r20 316 #define REG_R8 r21 317 #define REG_R9 r22 318 #define REG_R10 r23 319 320 #define REG_F1 fr14 321 #define REG_F2 fr15 322 #define REG_F3 fr16 323 #define REG_F4 fr17 324 #define REG_F5 fr18 325 #define REG_F6 fr19 326 327 #define REG_D1 fr20 328 #define REG_D2 fr21 329 #define REG_D3 fr22 330 #define REG_D4 fr23 331 #define REG_D5 fr24 332 #define REG_D6 fr25 333 334 #define REG_Sp r24 335 #define REG_SpLim r25 336 #define REG_Hp r26 337 #define REG_Base r27 338 339 #define MAX_REAL_FLOAT_REG 6 340 #define MAX_REAL_DOUBLE_REG 6 341 342 /* ----------------------------------------------------------------------------- 343 The Sun SPARC register mapping 344 345 !! IMPORTANT: if you change this register mapping you must also update 346 compiler/GHC/CmmToAsm/SPARC/Regs.hs. That file handles the 347 mapping for the NCG. This one only affects via-c code. 348 349 The SPARC register (window) story: Remember, within the Haskell 350 Threaded World, we essentially ``shut down'' the register-window 351 mechanism---the window doesn't move at all while in this World. It 352 *does* move, of course, if we call out to arbitrary~C... 353 354 The %i, %l, and %o registers (8 each) are the input, local, and 355 output registers visible in one register window. The 8 %g (global) 356 registers are visible all the time. 357 358 zero: always zero 359 scratch: volatile across C-fn calls. used by linker. 360 app: usable by application 361 system: reserved for system 362 363 alloc: allocated to in the register allocator, intra-closure only 364 365 GHC usage v8 ABI v9 ABI 366 Global 367 %g0 zero zero zero 368 %g1 alloc scratch scrach 369 %g2 alloc app app 370 %g3 alloc app app 371 %g4 alloc app scratch 372 %g5 system scratch 373 %g6 system system 374 %g7 system system 375 376 Output: can be zapped by callee 377 %o0-o5 alloc caller saves 378 %o6 C stack ptr 379 %o7 C ret addr 380 381 Local: maintained by register windowing mechanism 382 %l0 alloc 383 %l1 R1 384 %l2 R2 385 %l3 R3 386 %l4 R4 387 %l5 R5 388 %l6 alloc 389 %l7 alloc 390 391 Input 392 %i0 Sp 393 %i1 Base 394 %i2 SpLim 395 %i3 Hp 396 %i4 alloc 397 %i5 R6 398 %i6 C frame ptr 399 %i7 C ret addr 400 401 The paired nature of the floating point registers causes complications for 402 the native code generator. For convenience, we pretend that the first 22 403 fp regs %f0 .. %f21 are actually 11 double regs, and the remaining 10 are 404 float (single) regs. The NCG acts accordingly. That means that the 405 following FP assignment is rather fragile, and should only be changed 406 with extreme care. The current scheme is: 407 408 %f0 /%f1 FP return from C 409 %f2 /%f3 D1 410 %f4 /%f5 D2 411 %f6 /%f7 ncg double spill tmp #1 412 %f8 /%f9 ncg double spill tmp #2 413 %f10/%f11 allocatable 414 %f12/%f13 allocatable 415 %f14/%f15 allocatable 416 %f16/%f17 allocatable 417 %f18/%f19 allocatable 418 %f20/%f21 allocatable 419 420 %f22 F1 421 %f23 F2 422 %f24 F3 423 %f25 F4 424 %f26 ncg single spill tmp #1 425 %f27 ncg single spill tmp #2 426 %f28 allocatable 427 %f29 allocatable 428 %f30 allocatable 429 %f31 allocatable 430 431 -------------------------------------------------------------------------- */ 432 433 #elif defined(MACHREGS_sparc) 434 435 #define REG(x) __asm__("%" #x) 436 437 #define CALLER_SAVES_USER 438 439 #define CALLER_SAVES_F1 440 #define CALLER_SAVES_F2 441 #define CALLER_SAVES_F3 442 #define CALLER_SAVES_F4 443 #define CALLER_SAVES_D1 444 #define CALLER_SAVES_D2 445 446 #define REG_R1 l1 447 #define REG_R2 l2 448 #define REG_R3 l3 449 #define REG_R4 l4 450 #define REG_R5 l5 451 #define REG_R6 i5 452 453 #define REG_F1 f22 454 #define REG_F2 f23 455 #define REG_F3 f24 456 #define REG_F4 f25 457 458 /* for each of the double arg regs, 459 Dn_2 is the high half. */ 460 461 #define REG_D1 f2 462 #define REG_D1_2 f3 463 464 #define REG_D2 f4 465 #define REG_D2_2 f5 466 467 #define REG_Sp i0 468 #define REG_SpLim i2 469 470 #define REG_Hp i3 471 472 #define REG_Base i1 473 474 #define NCG_FirstFloatReg f22 475 476 /* ----------------------------------------------------------------------------- 477 The ARM EABI register mapping 478 479 Here we consider ARM mode (i.e. 32bit isns) 480 and also CPU with full VFPv3 implementation 481 482 ARM registers (see Chapter 5.1 in ARM IHI 0042D and 483 Section 9.2.2 in ARM Software Development Toolkit Reference Guide) 484 485 r15 PC The Program Counter. 486 r14 LR The Link Register. 487 r13 SP The Stack Pointer. 488 r12 IP The Intra-Procedure-call scratch register. 489 r11 v8/fp Variable-register 8. 490 r10 v7/sl Variable-register 7. 491 r9 v6/SB/TR Platform register. The meaning of this register is 492 defined by the platform standard. 493 r8 v5 Variable-register 5. 494 r7 v4 Variable register 4. 495 r6 v3 Variable register 3. 496 r5 v2 Variable register 2. 497 r4 v1 Variable register 1. 498 r3 a4 Argument / scratch register 4. 499 r2 a3 Argument / scratch register 3. 500 r1 a2 Argument / result / scratch register 2. 501 r0 a1 Argument / result / scratch register 1. 502 503 VFPv2/VFPv3/NEON registers 504 s0-s15/d0-d7/q0-q3 Argument / result/ scratch registers 505 s16-s31/d8-d15/q4-q7 callee-saved registers (must be preserved across 506 subroutine calls) 507 508 VFPv3/NEON registers (added to the VFPv2 registers set) 509 d16-d31/q8-q15 Argument / result/ scratch registers 510 ----------------------------------------------------------------------------- */ 511 512 #elif defined(MACHREGS_arm) 513 514 #define REG(x) __asm__(#x) 515 516 #define REG_Base r4 517 #define REG_Sp r5 518 #define REG_Hp r6 519 #define REG_R1 r7 520 #define REG_R2 r8 521 #define REG_R3 r9 522 #define REG_R4 r10 523 #define REG_SpLim r11 524 525 #if !defined(arm_HOST_ARCH_PRE_ARMv6) 526 /* d8 */ 527 #define REG_F1 s16 528 #define REG_F2 s17 529 /* d9 */ 530 #define REG_F3 s18 531 #define REG_F4 s19 532 533 #define REG_D1 d10 534 #define REG_D2 d11 535 #endif 536 537 /* ----------------------------------------------------------------------------- 538 The ARMv8/AArch64 ABI register mapping 539 540 The AArch64 provides 31 64-bit general purpose registers 541 and 32 128-bit SIMD/floating point registers. 542 543 General purpose registers (see Chapter 5.1.1 in ARM IHI 0055B) 544 545 Register | Special | Role in the procedure call standard 546 ---------+---------+------------------------------------ 547 SP | | The Stack Pointer 548 r30 | LR | The Link Register 549 r29 | FP | The Frame Pointer 550 r19-r28 | | Callee-saved registers 551 r18 | | The Platform Register, if needed; 552 | | or temporary register 553 r17 | IP1 | The second intra-procedure-call temporary register 554 r16 | IP0 | The first intra-procedure-call scratch register 555 r9-r15 | | Temporary registers 556 r8 | | Indirect result location register 557 r0-r7 | | Parameter/result registers 558 559 560 FPU/SIMD registers 561 562 s/d/q/v0-v7 Argument / result/ scratch registers 563 s/d/q/v8-v15 callee-saved registers (must be preserved across subroutine calls, 564 but only bottom 64-bit value needs to be preserved) 565 s/d/q/v16-v31 temporary registers 566 567 ----------------------------------------------------------------------------- */ 568 569 #elif defined(MACHREGS_aarch64) 570 571 #define REG(x) __asm__(#x) 572 573 #define REG_Base r19 574 #define REG_Sp r20 575 #define REG_Hp r21 576 #define REG_R1 r22 577 #define REG_R2 r23 578 #define REG_R3 r24 579 #define REG_R4 r25 580 #define REG_R5 r26 581 #define REG_R6 r27 582 #define REG_SpLim r28 583 584 #define REG_F1 s8 585 #define REG_F2 s9 586 #define REG_F3 s10 587 #define REG_F4 s11 588 589 #define REG_D1 d12 590 #define REG_D2 d13 591 #define REG_D3 d14 592 #define REG_D4 d15 593 594 /* ----------------------------------------------------------------------------- 595 The s390x register mapping 596 597 Register | Role(s) | Call effect 598 ------------+-------------------------------------+----------------- 599 r0,r1 | - | caller-saved 600 r2 | Argument / return value | caller-saved 601 r3,r4,r5 | Arguments | caller-saved 602 r6 | Argument | callee-saved 603 r7...r11 | - | callee-saved 604 r12 | (Commonly used as GOT pointer) | callee-saved 605 r13 | (Commonly used as literal pool pointer) | callee-saved 606 r14 | Return address | caller-saved 607 r15 | Stack pointer | callee-saved 608 f0 | Argument / return value | caller-saved 609 f2,f4,f6 | Arguments | caller-saved 610 f1,f3,f5,f7 | - | caller-saved 611 f8...f15 | - | callee-saved 612 v0...v31 | - | caller-saved 613 614 Each general purpose register r0 through r15 as well as each floating-point 615 register f0 through f15 is 64 bits wide. Each vector register v0 through v31 616 is 128 bits wide. 617 618 Note, the vector registers v0 through v15 overlap with the floating-point 619 registers f0 through f15. 620 621 -------------------------------------------------------------------------- */ 622 623 #elif defined(MACHREGS_s390x) 624 625 #define REG(x) __asm__("%" #x) 626 627 #define REG_Base r7 628 #define REG_Sp r8 629 #define REG_Hp r10 630 #define REG_R1 r11 631 #define REG_R2 r12 632 #define REG_R3 r13 633 #define REG_R4 r6 634 #define REG_R5 r2 635 #define REG_R6 r3 636 #define REG_R7 r4 637 #define REG_R8 r5 638 #define REG_SpLim r9 639 #define REG_MachSp r15 640 641 #define REG_F1 f8 642 #define REG_F2 f9 643 #define REG_F3 f10 644 #define REG_F4 f11 645 #define REG_F5 f0 646 #define REG_F6 f1 647 648 #define REG_D1 f12 649 #define REG_D2 f13 650 #define REG_D3 f14 651 #define REG_D4 f15 652 #define REG_D5 f2 653 #define REG_D6 f3 654 655 #define CALLER_SAVES_R5 656 #define CALLER_SAVES_R6 657 #define CALLER_SAVES_R7 658 #define CALLER_SAVES_R8 659 660 #define CALLER_SAVES_F5 661 #define CALLER_SAVES_F6 662 663 #define CALLER_SAVES_D5 664 #define CALLER_SAVES_D6 665 666 #else 667 668 #error Cannot find platform to give register info for 669 670 #endif 671 672 #else 673 674 #error Bad MACHREGS_NO_REGS value 675 676 #endif 677 678 /* ----------------------------------------------------------------------------- 679 * These constants define how many stg registers will be used for 680 * passing arguments (and results, in the case of an unboxed-tuple 681 * return). 682 * 683 * We usually set MAX_REAL_VANILLA_REG and co. to be the number of the 684 * highest STG register to occupy a real machine register, otherwise 685 * the calling conventions will needlessly shuffle data between the 686 * stack and memory-resident STG registers. We might occasionally 687 * set these macros to other values for testing, though. 688 * 689 * Registers above these values might still be used, for instance to 690 * communicate with PrimOps and RTS functions. 691 */ 692 693 #if !defined(MAX_REAL_VANILLA_REG) 694 # if defined(REG_R10) 695 # define MAX_REAL_VANILLA_REG 10 696 # elif defined(REG_R9) 697 # define MAX_REAL_VANILLA_REG 9 698 # elif defined(REG_R8) 699 # define MAX_REAL_VANILLA_REG 8 700 # elif defined(REG_R7) 701 # define MAX_REAL_VANILLA_REG 7 702 # elif defined(REG_R6) 703 # define MAX_REAL_VANILLA_REG 6 704 # elif defined(REG_R5) 705 # define MAX_REAL_VANILLA_REG 5 706 # elif defined(REG_R4) 707 # define MAX_REAL_VANILLA_REG 4 708 # elif defined(REG_R3) 709 # define MAX_REAL_VANILLA_REG 3 710 # elif defined(REG_R2) 711 # define MAX_REAL_VANILLA_REG 2 712 # elif defined(REG_R1) 713 # define MAX_REAL_VANILLA_REG 1 714 # else 715 # define MAX_REAL_VANILLA_REG 0 716 # endif 717 #endif 718 719 #if !defined(MAX_REAL_FLOAT_REG) 720 # if defined(REG_F4) 721 # define MAX_REAL_FLOAT_REG 4 722 # elif defined(REG_F3) 723 # define MAX_REAL_FLOAT_REG 3 724 # elif defined(REG_F2) 725 # define MAX_REAL_FLOAT_REG 2 726 # elif defined(REG_F1) 727 # define MAX_REAL_FLOAT_REG 1 728 # else 729 # define MAX_REAL_FLOAT_REG 0 730 # endif 731 #endif 732 733 #if !defined(MAX_REAL_DOUBLE_REG) 734 # if defined(REG_D2) 735 # define MAX_REAL_DOUBLE_REG 2 736 # elif defined(REG_D1) 737 # define MAX_REAL_DOUBLE_REG 1 738 # else 739 # define MAX_REAL_DOUBLE_REG 0 740 # endif 741 #endif 742 743 #if !defined(MAX_REAL_LONG_REG) 744 # if defined(REG_L1) 745 # define MAX_REAL_LONG_REG 1 746 # else 747 # define MAX_REAL_LONG_REG 0 748 # endif 749 #endif 750 751 #if !defined(MAX_REAL_XMM_REG) 752 # if defined(REG_XMM6) 753 # define MAX_REAL_XMM_REG 6 754 # elif defined(REG_XMM5) 755 # define MAX_REAL_XMM_REG 5 756 # elif defined(REG_XMM4) 757 # define MAX_REAL_XMM_REG 4 758 # elif defined(REG_XMM3) 759 # define MAX_REAL_XMM_REG 3 760 # elif defined(REG_XMM2) 761 # define MAX_REAL_XMM_REG 2 762 # elif defined(REG_XMM1) 763 # define MAX_REAL_XMM_REG 1 764 # else 765 # define MAX_REAL_XMM_REG 0 766 # endif 767 #endif 768 769 /* define NO_ARG_REGS if we have no argument registers at all (we can 770 * optimise certain code paths using this predicate). 771 */ 772 #if MAX_REAL_VANILLA_REG < 2 773 #define NO_ARG_REGS 774 #else 775 #undef NO_ARG_REGS 776 #endif 777