| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/CodeGen/ |
| H A D | LiveIntervalUnion.cpp | 35 LiveRange::const_iterator RegPos = Range.begin(); in unify() local
37 SegmentIter SegPos = Segments.find(RegPos->start); in unify()
40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
41 if (++RegPos == RegEnd) in unify()
43 SegPos.advanceTo(RegPos->start); in unify()
51 for (; RegPos != RegEnd; ++RegPos, ++SegPos) in unify()
52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
62 LiveRange::const_iterator RegPos = Range.begin(); in extract() local
73 RegPos = Range.advanceTo(RegPos, SegPos.start()); in extract()
74 if (RegPos == RegEnd) in extract()
[all …]
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/CodeGen/ |
| H A D | LiveIntervalUnion.cpp | 35 LiveRange::const_iterator RegPos = Range.begin(); in unify() local
37 SegmentIter SegPos = Segments.find(RegPos->start); in unify()
40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
41 if (++RegPos == RegEnd) in unify()
43 SegPos.advanceTo(RegPos->start); in unify()
51 for (; RegPos != RegEnd; ++RegPos, ++SegPos) in unify()
52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
62 LiveRange::const_iterator RegPos = Range.begin(); in extract() local
73 RegPos = Range.advanceTo(RegPos, SegPos.start()); in extract()
74 if (RegPos == RegEnd) in extract()
[all …]
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/CodeGen/ |
| H A D | LiveIntervalUnion.cpp | 35 LiveRange::const_iterator RegPos = Range.begin(); in unify() local
37 SegmentIter SegPos = Segments.find(RegPos->start); in unify()
40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
41 if (++RegPos == RegEnd) in unify()
43 SegPos.advanceTo(RegPos->start); in unify()
51 for (; RegPos != RegEnd; ++RegPos, ++SegPos) in unify()
52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
62 LiveRange::const_iterator RegPos = Range.begin(); in extract() local
73 RegPos = Range.advanceTo(RegPos, SegPos.start()); in extract()
74 if (RegPos == RegEnd) in extract()
[all …]
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/CodeGen/ |
| H A D | LiveIntervalUnion.cpp | 35 LiveRange::const_iterator RegPos = Range.begin(); in unify() local
37 SegmentIter SegPos = Segments.find(RegPos->start); in unify()
40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
41 if (++RegPos == RegEnd) in unify()
43 SegPos.advanceTo(RegPos->start); in unify()
51 for (; RegPos != RegEnd; ++RegPos, ++SegPos) in unify()
52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
62 LiveRange::const_iterator RegPos = Range.begin(); in extract() local
73 RegPos = Range.advanceTo(RegPos, SegPos.start()); in extract()
74 if (RegPos == RegEnd) in extract()
[all …]
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/CodeGen/ |
| H A D | LiveIntervalUnion.cpp | 35 LiveRange::const_iterator RegPos = Range.begin(); in unify() local
37 SegmentIter SegPos = Segments.find(RegPos->start); in unify()
40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
41 if (++RegPos == RegEnd) in unify()
43 SegPos.advanceTo(RegPos->start); in unify()
51 for (; RegPos != RegEnd; ++RegPos, ++SegPos) in unify()
52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
62 LiveRange::const_iterator RegPos = Range.begin(); in extract() local
73 RegPos = Range.advanceTo(RegPos, SegPos.start()); in extract()
74 if (RegPos == RegEnd) in extract()
[all …]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| H A D | LiveIntervalUnion.cpp | 35 LiveRange::const_iterator RegPos = Range.begin(); in unify() local
37 SegmentIter SegPos = Segments.find(RegPos->start); in unify()
40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
41 if (++RegPos == RegEnd) in unify()
43 SegPos.advanceTo(RegPos->start); in unify()
51 for (; RegPos != RegEnd; ++RegPos, ++SegPos) in unify()
52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
62 LiveRange::const_iterator RegPos = Range.begin(); in extract() local
73 RegPos = Range.advanceTo(RegPos, SegPos.start()); in extract()
74 if (RegPos == RegEnd) in extract()
[all …]
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/CodeGen/ |
| H A D | LiveIntervalUnion.cpp | 35 LiveRange::const_iterator RegPos = Range.begin(); in unify() local
37 SegmentIter SegPos = Segments.find(RegPos->start); in unify()
40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
41 if (++RegPos == RegEnd) in unify()
43 SegPos.advanceTo(RegPos->start); in unify()
51 for (; RegPos != RegEnd; ++RegPos, ++SegPos) in unify()
52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
62 LiveRange::const_iterator RegPos = Range.begin(); in extract() local
73 RegPos = Range.advanceTo(RegPos, SegPos.start()); in extract()
74 if (RegPos == RegEnd) in extract()
[all …]
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/CodeGen/ |
| H A D | LiveIntervalUnion.cpp | 35 LiveRange::const_iterator RegPos = Range.begin(); in unify() local
37 SegmentIter SegPos = Segments.find(RegPos->start); in unify()
40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
41 if (++RegPos == RegEnd) in unify()
43 SegPos.advanceTo(RegPos->start); in unify()
51 for (; RegPos != RegEnd; ++RegPos, ++SegPos) in unify()
52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
62 LiveRange::const_iterator RegPos = Range.begin(); in extract() local
73 RegPos = Range.advanceTo(RegPos, SegPos.start()); in extract()
74 if (RegPos == RegEnd) in extract()
[all …]
|
| /dports/devel/llvm90/llvm-9.0.1.src/lib/CodeGen/ |
| H A D | LiveIntervalUnion.cpp | 35 LiveRange::const_iterator RegPos = Range.begin(); in unify() local
37 SegmentIter SegPos = Segments.find(RegPos->start); in unify()
40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
41 if (++RegPos == RegEnd) in unify()
43 SegPos.advanceTo(RegPos->start); in unify()
51 for (; RegPos != RegEnd; ++RegPos, ++SegPos) in unify()
52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
62 LiveRange::const_iterator RegPos = Range.begin(); in extract() local
73 RegPos = Range.advanceTo(RegPos, SegPos.start()); in extract()
74 if (RegPos == RegEnd) in extract()
[all …]
|
| /dports/devel/llvm80/llvm-8.0.1.src/lib/CodeGen/ |
| H A D | LiveIntervalUnion.cpp | 36 LiveRange::const_iterator RegPos = Range.begin(); in unify() local
38 SegmentIter SegPos = Segments.find(RegPos->start); in unify()
41 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
42 if (++RegPos == RegEnd) in unify()
44 SegPos.advanceTo(RegPos->start); in unify()
52 for (; RegPos != RegEnd; ++RegPos, ++SegPos) in unify()
53 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
63 LiveRange::const_iterator RegPos = Range.begin(); in extract() local
74 RegPos = Range.advanceTo(RegPos, SegPos.start()); in extract()
75 if (RegPos == RegEnd) in extract()
[all …]
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/CodeGen/ |
| H A D | LiveIntervalUnion.cpp | 36 LiveRange::const_iterator RegPos = Range.begin(); in unify() local
38 SegmentIter SegPos = Segments.find(RegPos->start); in unify()
41 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
42 if (++RegPos == RegEnd) in unify()
44 SegPos.advanceTo(RegPos->start); in unify()
52 for (; RegPos != RegEnd; ++RegPos, ++SegPos) in unify()
53 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
63 LiveRange::const_iterator RegPos = Range.begin(); in extract() local
74 RegPos = Range.advanceTo(RegPos, SegPos.start()); in extract()
75 if (RegPos == RegEnd) in extract()
[all …]
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/CodeGen/ |
| H A D | LiveIntervalUnion.cpp | 35 LiveRange::const_iterator RegPos = Range.begin(); in unify() local
37 SegmentIter SegPos = Segments.find(RegPos->start); in unify()
40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
41 if (++RegPos == RegEnd) in unify()
43 SegPos.advanceTo(RegPos->start); in unify()
51 for (; RegPos != RegEnd; ++RegPos, ++SegPos) in unify()
52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
62 LiveRange::const_iterator RegPos = Range.begin(); in extract() local
73 RegPos = Range.advanceTo(RegPos, SegPos.start()); in extract()
74 if (RegPos == RegEnd) in extract()
[all …]
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/CodeGen/ |
| H A D | LiveIntervalUnion.cpp | 35 LiveRange::const_iterator RegPos = Range.begin(); in unify() local
37 SegmentIter SegPos = Segments.find(RegPos->start); in unify()
40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
41 if (++RegPos == RegEnd) in unify()
43 SegPos.advanceTo(RegPos->start); in unify()
51 for (; RegPos != RegEnd; ++RegPos, ++SegPos) in unify()
52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
62 LiveRange::const_iterator RegPos = Range.begin(); in extract() local
73 RegPos = Range.advanceTo(RegPos, SegPos.start()); in extract()
74 if (RegPos == RegEnd) in extract()
[all …]
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/CodeGen/ |
| H A D | LiveIntervalUnion.cpp | 35 LiveRange::const_iterator RegPos = Range.begin(); in unify() local
37 SegmentIter SegPos = Segments.find(RegPos->start); in unify()
40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
41 if (++RegPos == RegEnd) in unify()
43 SegPos.advanceTo(RegPos->start); in unify()
51 for (; RegPos != RegEnd; ++RegPos, ++SegPos) in unify()
52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
62 LiveRange::const_iterator RegPos = Range.begin(); in extract() local
73 RegPos = Range.advanceTo(RegPos, SegPos.start()); in extract()
74 if (RegPos == RegEnd) in extract()
[all …]
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/CodeGen/ |
| H A D | LiveIntervalUnion.cpp | 35 LiveRange::const_iterator RegPos = Range.begin(); in unify() local
37 SegmentIter SegPos = Segments.find(RegPos->start); in unify()
40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
41 if (++RegPos == RegEnd) in unify()
43 SegPos.advanceTo(RegPos->start); in unify()
51 for (; RegPos != RegEnd; ++RegPos, ++SegPos) in unify()
52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
62 LiveRange::const_iterator RegPos = Range.begin(); in extract() local
73 RegPos = Range.advanceTo(RegPos, SegPos.start()); in extract()
74 if (RegPos == RegEnd) in extract()
[all …]
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/CodeGen/ |
| H A D | LiveIntervalUnion.cpp | 35 LiveRange::const_iterator RegPos = Range.begin(); in unify() local
37 SegmentIter SegPos = Segments.find(RegPos->start); in unify()
40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
41 if (++RegPos == RegEnd) in unify()
43 SegPos.advanceTo(RegPos->start); in unify()
51 for (; RegPos != RegEnd; ++RegPos, ++SegPos) in unify()
52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
62 LiveRange::const_iterator RegPos = Range.begin(); in extract() local
73 RegPos = Range.advanceTo(RegPos, SegPos.start()); in extract()
74 if (RegPos == RegEnd) in extract()
[all …]
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/CodeGen/ |
| H A D | LiveIntervalUnion.cpp | 35 LiveRange::const_iterator RegPos = Range.begin(); in unify() local
37 SegmentIter SegPos = Segments.find(RegPos->start); in unify()
40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
41 if (++RegPos == RegEnd) in unify()
43 SegPos.advanceTo(RegPos->start); in unify()
51 for (; RegPos != RegEnd; ++RegPos, ++SegPos) in unify()
52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
62 LiveRange::const_iterator RegPos = Range.begin(); in extract() local
73 RegPos = Range.advanceTo(RegPos, SegPos.start()); in extract()
74 if (RegPos == RegEnd) in extract()
[all …]
|
| /dports/devel/asl/asl-current/ |
| H A D | code960.c | 83 ShortInt RegPos; member
592 ShortInt MemPos = (Op->RegPos > 0) ? 3 - Op->RegPos : 1; in DecodeMemO()
593 unsigned NumArgs = 1 + Ord(Op->RegPos > 0); in DecodeMemO()
596 else if ((Op->RegPos > 0) && (DecodeIReg(&ArgStr[Op->RegPos], &Reg, True) != eIsReg)); in DecodeMemO()
597 else if (Reg & OpMasks[Op->Type]) WrStrErrorPos(ErrNum_InvReg, &ArgStr[Op->RegPos]); in DecodeMemO()
720 MemOrders[InstrZ].RegPos = NPos; in AddMem()
|
| /dports/textproc/texi2html/texi2html-5.0/test/xemacs_manual/ |
| H A D | regs.texi | 31 * Position: RegPos. Saving positions in registers.
40 @node RegPos, RegText, Registers, Registers
73 @node RegText, RegRect, RegPos, Registers
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineScheduler.cpp | 1467 std::set<unsigned>::iterator RegPos = PredOutRegs.find(Reg); in SIScheduleBlockScheduler() local
1469 if (RegPos != PredOutRegs.end()) { in SIScheduleBlockScheduler()
1531 std::set<unsigned>::iterator RegPos = PredOutRegs.find(Reg); in SIScheduleBlockScheduler() local
1533 if (RegPos != PredOutRegs.end()) { in SIScheduleBlockScheduler()
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineScheduler.cpp | 1467 std::set<unsigned>::iterator RegPos = PredOutRegs.find(Reg); in SIScheduleBlockScheduler() local
1469 if (RegPos != PredOutRegs.end()) { in SIScheduleBlockScheduler()
1531 std::set<unsigned>::iterator RegPos = PredOutRegs.find(Reg); in SIScheduleBlockScheduler() local
1533 if (RegPos != PredOutRegs.end()) { in SIScheduleBlockScheduler()
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AMDGPU/ |
| H A D | SIMachineScheduler.cpp | 1465 std::set<unsigned>::iterator RegPos = PredOutRegs.find(Reg); in SIScheduleBlockScheduler() local
1467 if (RegPos != PredOutRegs.end()) { in SIScheduleBlockScheduler()
1529 std::set<unsigned>::iterator RegPos = PredOutRegs.find(Reg); in SIScheduleBlockScheduler() local
1531 if (RegPos != PredOutRegs.end()) { in SIScheduleBlockScheduler()
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineScheduler.cpp | 1447 std::set<unsigned>::iterator RegPos = PredOutRegs.find(Reg);
1449 if (RegPos != PredOutRegs.end()) {
1511 std::set<unsigned>::iterator RegPos = PredOutRegs.find(Reg);
1513 if (RegPos != PredOutRegs.end()) {
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AMDGPU/ |
| H A D | SIMachineScheduler.cpp | 1447 std::set<unsigned>::iterator RegPos = PredOutRegs.find(Reg); in SIScheduleBlockScheduler() local
1449 if (RegPos != PredOutRegs.end()) { in SIScheduleBlockScheduler()
1511 std::set<unsigned>::iterator RegPos = PredOutRegs.find(Reg); in SIScheduleBlockScheduler() local
1513 if (RegPos != PredOutRegs.end()) { in SIScheduleBlockScheduler()
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineScheduler.cpp | 1447 std::set<unsigned>::iterator RegPos = PredOutRegs.find(Reg); in SIScheduleBlockScheduler() local
1449 if (RegPos != PredOutRegs.end()) { in SIScheduleBlockScheduler()
1511 std::set<unsigned>::iterator RegPos = PredOutRegs.find(Reg); in SIScheduleBlockScheduler() local
1513 if (RegPos != PredOutRegs.end()) { in SIScheduleBlockScheduler()
|