1 //===- LiveIntervalUnion.cpp - Live interval union data structure ---------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // LiveIntervalUnion represents a coalesced set of live intervals. This may be
10 // used during coalescing to represent a congruence class, or during register
11 // allocation to model liveness of a physical register.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/LiveIntervalUnion.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SparseBitVector.h"
18 #include "llvm/CodeGen/LiveInterval.h"
19 #include "llvm/CodeGen/TargetRegisterInfo.h"
20 #include "llvm/Support/raw_ostream.h"
21 #include <cassert>
22 #include <cstdlib>
23 
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "regalloc"
27 
28 // Merge a LiveInterval's segments. Guarantee no overlaps.
unify(LiveInterval & VirtReg,const LiveRange & Range)29 void LiveIntervalUnion::unify(LiveInterval &VirtReg, const LiveRange &Range) {
30   if (Range.empty())
31     return;
32   ++Tag;
33 
34   // Insert each of the virtual register's live segments into the map.
35   LiveRange::const_iterator RegPos = Range.begin();
36   LiveRange::const_iterator RegEnd = Range.end();
37   SegmentIter SegPos = Segments.find(RegPos->start);
38 
39   while (SegPos.valid()) {
40     SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
41     if (++RegPos == RegEnd)
42       return;
43     SegPos.advanceTo(RegPos->start);
44   }
45 
46   // We have reached the end of Segments, so it is no longer necessary to search
47   // for the insertion position.
48   // It is faster to insert the end first.
49   --RegEnd;
50   SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg);
51   for (; RegPos != RegEnd; ++RegPos, ++SegPos)
52     SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
53 }
54 
55 // Remove a live virtual register's segments from this union.
extract(LiveInterval & VirtReg,const LiveRange & Range)56 void LiveIntervalUnion::extract(LiveInterval &VirtReg, const LiveRange &Range) {
57   if (Range.empty())
58     return;
59   ++Tag;
60 
61   // Remove each of the virtual register's live segments from the map.
62   LiveRange::const_iterator RegPos = Range.begin();
63   LiveRange::const_iterator RegEnd = Range.end();
64   SegmentIter SegPos = Segments.find(RegPos->start);
65 
66   while (true) {
67     assert(SegPos.value() == &VirtReg && "Inconsistent LiveInterval");
68     SegPos.erase();
69     if (!SegPos.valid())
70       return;
71 
72     // Skip all segments that may have been coalesced.
73     RegPos = Range.advanceTo(RegPos, SegPos.start());
74     if (RegPos == RegEnd)
75       return;
76 
77     SegPos.advanceTo(RegPos->start);
78   }
79 }
80 
81 void
print(raw_ostream & OS,const TargetRegisterInfo * TRI) const82 LiveIntervalUnion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) const {
83   if (empty()) {
84     OS << " empty\n";
85     return;
86   }
87   for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) {
88     OS << " [" << SI.start() << ' ' << SI.stop()
89        << "):" << printReg(SI.value()->reg(), TRI);
90   }
91   OS << '\n';
92 }
93 
94 #ifndef NDEBUG
95 // Verify the live intervals in this union and add them to the visited set.
verify(LiveVirtRegBitSet & VisitedVRegs)96 void LiveIntervalUnion::verify(LiveVirtRegBitSet& VisitedVRegs) {
97   for (SegmentIter SI = Segments.begin(); SI.valid(); ++SI)
98     VisitedVRegs.set(SI.value()->reg());
99 }
100 #endif //!NDEBUG
101 
getOneVReg() const102 LiveInterval *LiveIntervalUnion::getOneVReg() const {
103   if (empty())
104     return nullptr;
105   for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) {
106     // return the first valid live interval
107     return SI.value();
108   }
109   return nullptr;
110 }
111 
112 // Scan the vector of interfering virtual registers in this union. Assume it's
113 // quite small.
isSeenInterference(LiveInterval * VirtReg) const114 bool LiveIntervalUnion::Query::isSeenInterference(LiveInterval *VirtReg) const {
115   return is_contained(InterferingVRegs, VirtReg);
116 }
117 
118 // Collect virtual registers in this union that interfere with this
119 // query's live virtual register.
120 //
121 // The query state is one of:
122 //
123 // 1. CheckedFirstInterference == false: Iterators are uninitialized.
124 // 2. SeenAllInterferences == true: InterferingVRegs complete, iterators unused.
125 // 3. Iterators left at the last seen intersection.
126 //
127 unsigned LiveIntervalUnion::Query::
collectInterferingVRegs(unsigned MaxInterferingRegs)128 collectInterferingVRegs(unsigned MaxInterferingRegs) {
129   // Fast path return if we already have the desired information.
130   if (SeenAllInterferences || InterferingVRegs.size() >= MaxInterferingRegs)
131     return InterferingVRegs.size();
132 
133   // Set up iterators on the first call.
134   if (!CheckedFirstInterference) {
135     CheckedFirstInterference = true;
136 
137     // Quickly skip interference check for empty sets.
138     if (LR->empty() || LiveUnion->empty()) {
139       SeenAllInterferences = true;
140       return 0;
141     }
142 
143     // In most cases, the union will start before LR.
144     LRI = LR->begin();
145     LiveUnionI.setMap(LiveUnion->getMap());
146     LiveUnionI.find(LRI->start);
147   }
148 
149   LiveRange::const_iterator LREnd = LR->end();
150   LiveInterval *RecentReg = nullptr;
151   while (LiveUnionI.valid()) {
152     assert(LRI != LREnd && "Reached end of LR");
153 
154     // Check for overlapping interference.
155     while (LRI->start < LiveUnionI.stop() && LRI->end > LiveUnionI.start()) {
156       // This is an overlap, record the interfering register.
157       LiveInterval *VReg = LiveUnionI.value();
158       if (VReg != RecentReg && !isSeenInterference(VReg)) {
159         RecentReg = VReg;
160         InterferingVRegs.push_back(VReg);
161         if (InterferingVRegs.size() >= MaxInterferingRegs)
162           return InterferingVRegs.size();
163       }
164       // This LiveUnion segment is no longer interesting.
165       if (!(++LiveUnionI).valid()) {
166         SeenAllInterferences = true;
167         return InterferingVRegs.size();
168       }
169     }
170 
171     // The iterators are now not overlapping, LiveUnionI has been advanced
172     // beyond LRI.
173     assert(LRI->end <= LiveUnionI.start() && "Expected non-overlap");
174 
175     // Advance the iterator that ends first.
176     LRI = LR->advanceTo(LRI, LiveUnionI.start());
177     if (LRI == LREnd)
178       break;
179 
180     // Detect overlap, handle above.
181     if (LRI->start < LiveUnionI.stop())
182       continue;
183 
184     // Still not overlapping. Catch up LiveUnionI.
185     LiveUnionI.advanceTo(LRI->start);
186   }
187   SeenAllInterferences = true;
188   return InterferingVRegs.size();
189 }
190 
init(LiveIntervalUnion::Allocator & Alloc,unsigned NSize)191 void LiveIntervalUnion::Array::init(LiveIntervalUnion::Allocator &Alloc,
192                                     unsigned NSize) {
193   // Reuse existing allocation.
194   if (NSize == Size)
195     return;
196   clear();
197   Size = NSize;
198   LIUs = static_cast<LiveIntervalUnion*>(
199       safe_malloc(sizeof(LiveIntervalUnion)*NSize));
200   for (unsigned i = 0; i != Size; ++i)
201     new(LIUs + i) LiveIntervalUnion(Alloc);
202 }
203 
clear()204 void LiveIntervalUnion::Array::clear() {
205   if (!LIUs)
206     return;
207   for (unsigned i = 0; i != Size; ++i)
208     LIUs[i].~LiveIntervalUnion();
209   free(LIUs);
210   Size =  0;
211   LIUs = nullptr;
212 }
213