/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/AMDGPU/ |
H A D | sign_extend.ll | 152 ; VI-DAG: v_lshrrev_b16_e32 [[SH16:v[0-9]+]], 8, [[VAL]] 156 ; VI-DAG: v_bfe_i32 [[EXT1:v[0-9]+]], [[SH16]], 0, 8
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/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/AMDGPU/ |
H A D | sign_extend.ll | 152 ; VI-DAG: v_lshrrev_b16_e32 [[SH16:v[0-9]+]], 8, [[VAL]] 156 ; VI-DAG: v_bfe_i32 [[EXT1:v[0-9]+]], [[SH16]], 0, 8
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/dports/lang/erlang-runtime22/otp-OTP-22.3.4.24/lib/hipe/ppc/ |
H A D | hipe_ppc_encode.erl | 1155 SH16 = {sh,16}, 1340 t(OS,'srawi',{R14,R10,SH16}), 1341 t(OS,'srawi.',{R14,R10,SH16}), 1524 t(OS,'rlwimi',{R14,R10,SH16,MB10,ME20}), 1525 t(OS,'rlwimi.',{R14,R10,SH16,MB10,ME20}), 1526 t(OS,'rlwinm',{R14,R10,SH16,MB10,ME20}), 1527 t(OS,'rlwinm.',{R14,R10,SH16,MB10,ME20}),
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/dports/lang/erlang-runtime23/otp-OTP-23.3.4.10/lib/hipe/ppc/ |
H A D | hipe_ppc_encode.erl | 1155 SH16 = {sh,16}, 1340 t(OS,'srawi',{R14,R10,SH16}), 1341 t(OS,'srawi.',{R14,R10,SH16}), 1524 t(OS,'rlwimi',{R14,R10,SH16,MB10,ME20}), 1525 t(OS,'rlwimi.',{R14,R10,SH16,MB10,ME20}), 1526 t(OS,'rlwinm',{R14,R10,SH16,MB10,ME20}), 1527 t(OS,'rlwinm.',{R14,R10,SH16,MB10,ME20}),
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/dports/lang/erlang-runtime21/otp-OTP-21.3.8.24/lib/hipe/ppc/ |
H A D | hipe_ppc_encode.erl | 1155 SH16 = {sh,16}, 1340 t(OS,'srawi',{R14,R10,SH16}), 1341 t(OS,'srawi.',{R14,R10,SH16}), 1524 t(OS,'rlwimi',{R14,R10,SH16,MB10,ME20}), 1525 t(OS,'rlwimi.',{R14,R10,SH16,MB10,ME20}), 1526 t(OS,'rlwinm',{R14,R10,SH16,MB10,ME20}), 1527 t(OS,'rlwinm.',{R14,R10,SH16,MB10,ME20}),
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/dports/editors/hte/ht-e9e63373148da5d7df397d8075740d8c096ecb1d/asm/ |
H A D | ppcopc.cc | 816 #define SH16 S + 1 macro 2939 { "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 2940 { "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 2945 { "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 2946 { "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 3065 { "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 3066 { "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 3077 { "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 3078 { "dscriq.", ZRC(63,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
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/dports/lang/gnat_util/gcc-6-20180516/gcc/config/mips/ |
H A D | constraints.md | 351 A microMIPS memory operand for use with the LHU16/SH16 insns."
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/dports/devel/arm-none-eabi-gcc492/gcc-4.9.2/gcc/config/mips/ |
H A D | constraints.md | 348 A microMIPS memory operand for use with the LHU16/SH16 insns."
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/dports/lang/gcc6-aux/gcc-6-20180516/gcc/config/mips/ |
H A D | constraints.md | 351 A microMIPS memory operand for use with the LHU16/SH16 insns."
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/dports/emulators/qemu/qemu-6.2.0/disas/ |
H A D | ppc.c | 881 #define SH16 S + 1 macro 883 #define DCM SH16 888 #define EH SH16 + 1 4769 { "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4770 { "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4775 { "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4776 { "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4941 { "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4942 { "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4953 { "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, [all …]
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/dports/emulators/qemu42/qemu-4.2.1/disas/ |
H A D | ppc.c | 881 #define SH16 S + 1 macro 883 #define DCM SH16 888 #define EH SH16 + 1 4769 { "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4770 { "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4775 { "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4776 { "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4941 { "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4942 { "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4953 { "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, [all …]
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/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/ |
H A D | ppc-dis.c | 880 #define SH16 S + 1 macro 882 #define DCM SH16 887 #define EH SH16 + 1 4749 { "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4750 { "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4755 { "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4756 { "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4921 { "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4922 { "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4933 { "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, [all …]
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/dports/emulators/qemu5/qemu-5.2.0/disas/ |
H A D | ppc.c | 881 #define SH16 S + 1 macro 883 #define DCM SH16 888 #define EH SH16 + 1 4769 { "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4770 { "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4775 { "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4776 { "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4941 { "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4942 { "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4953 { "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, [all …]
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/dports/emulators/qemu60/qemu-6.0.0/disas/ |
H A D | ppc.c | 881 #define SH16 S + 1 macro 883 #define DCM SH16 888 #define EH SH16 + 1 4769 { "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4770 { "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4775 { "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4776 { "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4941 { "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4942 { "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4953 { "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, [all …]
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/disas/ |
H A D | ppc.c | 881 #define SH16 S + 1 macro 883 #define DCM SH16 888 #define EH SH16 + 1 4764 { "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4765 { "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4770 { "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4771 { "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4936 { "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4937 { "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4948 { "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, [all …]
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/dports/devel/radare2/radare2-5.1.1/libr/asm/arch/ppc/gnu/ |
H A D | ppc-opc.c | 574 #define SH16 (S + 1) macro 576 #define DCM SH16 581 #define EH (SH16 + 1) 4874 {"dscli", ZRC(59,66,0), Z_MASK, POWER6, {FRT, FRA, SH16}}, 4875 {"dscli.", ZRC(59,66,1), Z_MASK, POWER6, {FRT, FRA, SH16}}, 4880 {"dscri", ZRC(59,98,0), Z_MASK, POWER6, {FRT, FRA, SH16}}, 4881 {"dscri.", ZRC(59,98,1), Z_MASK, POWER6, {FRT, FRA, SH16}}, 5051 {"dscliq", ZRC(63,66,0), Z_MASK, POWER6, {FRT, FRA, SH16}}, 5052 {"dscliq.", ZRC(63,66,1), Z_MASK, POWER6, {FRT, FRA, SH16}}, 5063 {"dscriq", ZRC(63,98,0), Z_MASK, POWER6, {FRT, FRA, SH16}}, [all …]
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/dports/emulators/qemu-utils/qemu-4.2.1/disas/ |
H A D | ppc.c | 881 #define SH16 S + 1 macro 883 #define DCM SH16 888 #define EH SH16 + 1 4769 { "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4770 { "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4775 { "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4776 { "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4941 { "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4942 { "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4953 { "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, [all …]
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/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/disas/ |
H A D | ppc.c | 881 #define SH16 S + 1 macro 883 #define DCM SH16 888 #define EH SH16 + 1 4769 { "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4770 { "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4775 { "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4776 { "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4941 { "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4942 { "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4953 { "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, [all …]
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/disas/ |
H A D | ppc.c | 881 #define SH16 S + 1 macro 883 #define DCM SH16 888 #define EH SH16 + 1 4769 { "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4770 { "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4775 { "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4776 { "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4941 { "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4942 { "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4953 { "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, [all …]
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/disas/ |
H A D | ppc.c | 881 #define SH16 S + 1 macro 883 #define DCM SH16 888 #define EH SH16 + 1 4769 { "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4770 { "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4775 { "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4776 { "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4941 { "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4942 { "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4953 { "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, [all …]
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/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/config/mips/ |
H A D | constraints.md | 406 A microMIPS memory operand for use with the LHU16/SH16 insns."
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/dports/lang/gcc9/gcc-9.4.0/gcc/config/mips/ |
H A D | constraints.md | 406 A microMIPS memory operand for use with the LHU16/SH16 insns."
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/dports/devel/riscv64-gcc/gcc-8.3.0/gcc/config/mips/ |
H A D | constraints.md | 406 A microMIPS memory operand for use with the LHU16/SH16 insns."
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/dports/devel/avr-gcc/gcc-10.2.0/gcc/config/mips/ |
H A D | constraints.md | 406 A microMIPS memory operand for use with the LHU16/SH16 insns."
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/dports/lang/gcc11-devel/gcc-11-20211009/gcc/config/mips/ |
H A D | constraints.md | 406 A microMIPS memory operand for use with the LHU16/SH16 insns."
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