1 /*
2 * HT Editor
3 * ppcopc.cc
4 *
5 * Copyright (C) 1999-2003 Sebastian Biallas (sb@biallas.net)
6 * Copyright 1994 Free Software Foundation, Inc.
7 * Written by Ian Lance Taylor, Cygnus Support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23 #include <cstdio>
24 #include "ppcopc.h"
25
26 /* The functions used to insert and extract complicated operands. */
27
28 /* The BA field in an XL form instruction when it must be the same as
29 the BT field in the same instruction. This operand is marked FAKE.
30 The insertion function just copies the BT field into the BA field,
31 and the extraction function just checks that the fields are the
32 same. */
33
extract_bat(uint32 insn,bool * invalid)34 static uint32 extract_bat(uint32 insn, bool *invalid)
35 {
36 if (invalid != NULL && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) *invalid = 1;
37 return 0;
38 }
39
40 /* The BB field in an XL form instruction when it must be the same as
41 the BA field in the same instruction. This operand is marked FAKE.
42 The insertion function just copies the BA field into the BB field,
43 and the extraction function just checks that the fields are the
44 same. */
45
extract_bba(uint32 insn,bool * invalid)46 static uint32 extract_bba(uint32 insn, bool *invalid)
47 {
48 if (invalid != NULL && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) *invalid = 1;
49 return 0;
50 }
51
52 /* The BD field in a B form instruction. The lower two bits are
53 forced to zero. */
54
55
extract_bd(uint32 insn,bool * invalid)56 static uint32 extract_bd(uint32 insn, bool *invalid)
57 {
58 if ((insn & 0x8000) != 0) {
59 return (insn & 0xfffc) - 0x10000;
60 } else {
61 return insn & 0xfffc;
62 }
63 }
64
65 /* The BD field in a B form instruction when the - modifier is used.
66 This modifier means that the branch is not expected to be taken.
67 For chips built to versions of the architecture prior to version 2
68 (ie. not Power4 compatible), we set the y bit of the BO field to 1
69 if the offset is negative. When extracting, we require that the y
70 bit be 1 and that the offset be positive, since if the y bit is 0
71 we just want to print the normal form of the instruction.
72 Power4 compatible targets use two bits, "a", and "t", instead of
73 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
74 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
75 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
76 for branch on CTR. We only handle the taken/not-taken hint here. */
77
extract_bdm(uint32 insn,bool * invalid)78 static uint32 extract_bdm(uint32 insn, bool *invalid)
79 {
80 if (invalid) {
81 if ((insn & (0x17 << 21)) != (0x06 << 21)
82 && (insn & (0x1d << 21)) != (0x18 << 21))
83 *invalid = true;
84 }
85 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
86 }
87
88 /* The BD field in a B form instruction when the + modifier is used.
89 This is like BDM, above, except that the branch is expected to be
90 taken. */
91
extract_bdp(uint32 insn,bool * invalid)92 static uint32 extract_bdp(uint32 insn, bool *invalid)
93 {
94 if (invalid) {
95 if ((insn & (0x17 << 21)) != (0x07 << 21)
96 && (insn & (0x1d << 21)) != (0x19 << 21))
97 *invalid = true;
98 }
99 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
100 }
101
102 /* Check for legal values of a BO field. */
103
valid_bo(uint32 value)104 static bool valid_bo(uint32 value)
105 {
106 /* Certain encodings have bits that are required to be zero.
107 These are (z must be zero, a & t may be anything):
108 0000z
109 0001z
110 0100z
111 0101z
112 001at
113 011at
114 1a00t
115 1a01t
116 1z1zz
117 */
118 switch (value & 0x14) {
119 case 0:
120 return (value & 1) == 0;
121 case 0x4:
122 case 0x10:
123 return true;
124 case 0x14:
125 return value == 0x14;
126 }
127 return false;
128 }
129
130 /* The BO field in a B form instruction. Warn about attempts to set
131 the field to an illegal value. */
132
extract_bo(uint32 insn,bool * invalid)133 static uint32 extract_bo(uint32 insn, bool *invalid)
134 {
135 uint32 value;
136
137 value = (insn >> 21) & 0x1f;
138 if (invalid != NULL && !valid_bo(value))
139 *invalid = true;
140 return value;
141 }
142
143 /* The BO field in a B form instruction when the + or - modifier is
144 used. This is like the BO field, but it must be even. When
145 extracting it, we force it to be even. */
146
extract_boe(uint32 insn,bool * invalid)147 static uint32 extract_boe(uint32 insn, bool *invalid)
148 {
149 uint32 value;
150
151 value = (insn >> 21) & 0x1f;
152 if (invalid != NULL && !valid_bo(value)) *invalid = true;
153 return value & 0x1e;
154 }
155
156 /* The DS field in a DS form instruction. This is like D, but the
157 lower two bits are forced to zero. */
158
extract_ds(uint32 insn,bool * invalid)159 static uint32 extract_ds(uint32 insn, bool *invalid)
160 {
161 if ((insn & 0x8000) != 0) {
162 return (insn & 0xfffc) - 0x10000;
163 } else {
164 return insn & 0xfffc;
165 }
166 }
167
168 /* The DE field in a DE form instruction. */
169
extract_de(uint32 insn,bool * invalid)170 static uint32 extract_de(uint32 insn, bool *invalid)
171 {
172 return (insn & 0xfff0) >> 4;
173 }
174
175 /* The DES field in a DES form instruction. */
176
extract_des(uint32 insn,bool * invalid)177 static uint32 extract_des(uint32 insn, bool *invalid)
178 {
179 return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
180 }
181
182 /* The DQ field in a DQ form instruction. This is like D, but the
183 lower four bits are forced to zero. */
184
extract_dq(uint32 insn,bool * invalid)185 static uint32 extract_dq(uint32 insn, bool *invalid)
186 {
187 return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
188 }
189
190 /* The LI field in an I form instruction. The lower two bits are
191 forced to zero. */
192
extract_li(uint32 insn,bool * invalid)193 static uint32 extract_li(uint32 insn, bool *invalid)
194 {
195 if ((insn & 0x2000000) != 0) {
196 return (insn & 0x3fffffc) - 0x4000000;
197 } else {
198 return insn & 0x3fffffc;
199 }
200 }
201
202 /* The MB and ME fields in an M form instruction expressed as a single
203 operand which is itself a bitmask. The extraction function always
204 marks it as invalid, since we never want to recognize an
205 instruction which uses a field of this type. */
206
extract_mbe(uint32 insn,bool * invalid)207 static uint32 extract_mbe(uint32 insn, bool *invalid)
208 {
209 uint32 ret;
210 int mb, me;
211 int i;
212
213 if (invalid != NULL) *invalid = 1;
214
215 ret = 0;
216 mb = (insn >> 6) & 0x1f;
217 me = (insn >> 1) & 0x1f;
218 for (i = mb; i < me; i++) ret |= 1 << (31 - i);
219 return ret;
220 }
221
extract_mbe_special1(uint32 insn,bool * invalid)222 static uint32 extract_mbe_special1(uint32 insn, bool *invalid)
223 {
224 // slwi
225 if (invalid) {
226 int sh = (insn >> 11) & 0x1f;
227 int mb = (insn >> 6) & 0x1f;
228 int me = (insn >> 1) & 0x1f;
229 *invalid = !(mb == 0 && me == 31-sh);
230 }
231 return 0;
232 }
233
extract_mbe_special2(uint32 insn,bool * invalid)234 static uint32 extract_mbe_special2(uint32 insn, bool *invalid)
235 {
236 // srwi
237 if (invalid) {
238 int sh = (insn >> 11) & 0x1f;
239 int mb = (insn >> 6) & 0x1f;
240 int me = (insn >> 1) & 0x1f;
241 *invalid = !(sh == 32-mb && me == 31);
242 }
243 return 0;
244 }
245
246 /* The MB or ME field in an MD or MDS form instruction. The high bit
247 is wrapped to the low end. */
248
249
extract_mb6(uint32 insn,bool * invalid)250 static uint32 extract_mb6(uint32 insn, bool *invalid)
251 {
252 return ((insn >> 6) & 0x1f) | (insn & 0x20);
253 }
254
255 /* The NB field in an X form instruction. The value 32 is stored as
256 0. */
257
258
extract_nb(uint32 insn,bool * invalid)259 static uint32 extract_nb(uint32 insn, bool *invalid)
260 {
261 uint32 ret;
262
263 ret = (insn >> 11) & 0x1f;
264 if (ret == 0) ret = 32;
265 return ret;
266 }
267
268 /* The NSI field in a D form instruction. This is the same as the SI
269 field, only negated. The extraction function always marks it as
270 invalid, since we never want to recognize an instruction which uses
271 a field of this type. */
272
extract_nsi(uint32 insn,bool * invalid)273 static uint32 extract_nsi(uint32 insn, bool *invalid)
274 {
275 if (invalid != NULL) *invalid = 1;
276 if ((insn & 0x8000) != 0) {
277 return - ((insn & 0xffff) - 0x10000);
278 } else {
279 return - (insn & 0xffff);
280 }
281 }
282
283 /* The RA field in a D or X form instruction which is an updating
284 load, which means that the RA field may not be zero and may not
285 equal the RT field. */
286
287 /* The RB field in an X form instruction when it must be the same as
288 the RS field in the instruction. This is used for extended
289 mnemonics like mr. This operand is marked FAKE. The insertion
290 function just copies the BT field into the BA field, and the
291 extraction function just checks that the fields are the same. */
292
extract_rbs(uint32 insn,bool * invalid)293 static uint32 extract_rbs(uint32 insn, bool *invalid)
294 {
295 if (invalid != NULL
296 && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
297 *invalid = true;
298 return 0;
299 }
300
extract_vab(uint32 insn,bool * invalid)301 static uint32 extract_vab(uint32 insn, bool *invalid)
302 {
303 if (invalid != NULL
304 && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
305 *invalid = true;
306 return 0;
307 }
308
309 /* The SH field in an MD form instruction. This is split. */
310
extract_sh6(uint32 insn,bool * invalid)311 static uint32 extract_sh6(uint32 insn, bool *invalid)
312 {
313 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
314 }
315
316 /* The SPR field in an XFX form instruction. This is flipped--the
317 lower 5 bits are stored in the upper 5 and vice- versa. */
318
extract_spr(uint32 insn,bool * invalid)319 static uint32 extract_spr(uint32 insn, bool *invalid)
320 {
321 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
322 }
323
324 /* The TBR field in an XFX instruction. This is just like SPR, but it
325 is optional. When TBR is omitted, it must be inserted as 268 (the
326 magic number of the TB register). These functions treat 0
327 (indicating an omitted optional operand) as 268. This means that
328 ``mftb 4,0'' is not handled correctly. This does not matter very
329 much, since the architecture manual does not define mftb as
330 accepting any values other than 268 or 269. */
331
332 #define TB (268)
333
extract_tbr(uint32 insn,bool * invalid)334 static uint32 extract_tbr(uint32 insn, bool *invalid)
335 {
336 uint32 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
337 if (ret == TB) ret = 0;
338 return ret;
339 }
340
extract_vds128(uint32 insn,bool * invalid)341 static uint32 extract_vds128(uint32 insn, bool *invalid)
342 {
343 return ((insn<<3) & 0x60) | ((insn>>21) & 0x1f);
344 }
345
extract_va128(uint32 insn,bool * invalid)346 static uint32 extract_va128(uint32 insn, bool *invalid)
347 {
348 return ((insn>>4) & 0x40) | (insn & 0x20) | ((insn>>16) & 0x1f);
349 }
350
extract_vb128(uint32 insn,bool * invalid)351 static uint32 extract_vb128(uint32 insn, bool *invalid)
352 {
353 return ((insn<<5) & 0x60) | ((insn>>11) & 0x1f);
354 }
355
extract_vperm(uint32 insn,bool * invalid)356 static uint32 extract_vperm(uint32 insn, bool *invalid)
357 {
358 return ((insn>>1) & 0xe0) | ((insn>>16) & 0x1f);
359 }
360
361 /* The operands table.
362
363 The fields are bits, shift, signed, extract, flags. */
364
365 #undef UNUSED
366
367 const struct powerpc_operand powerpc_operands[] =
368 {
369 /* The zero index is used to indicate the end of the list of
370 operands. */
371 #define UNUSED 0
372 { 0, 0, 0, 0 },
373
374 /* The BA field in an XL form instruction. */
375 #define BA UNUSED + 1
376 #define BA_MASK (0x1f << 16)
377 { 5, 16, 0, PPC_OPERAND_CR },
378
379 /* The BA field in an XL form instruction when it must be the same
380 as the BT field in the same instruction. */
381 #define BAT BA + 1
382 { 5, 16, extract_bat, PPC_OPERAND_FAKE },
383
384 /* The BB field in an XL form instruction. */
385 #define BB BAT + 1
386 #define BB_MASK (0x1f << 11)
387 { 5, 11, 0, PPC_OPERAND_CR },
388
389 /* The BB field in an XL form instruction when it must be the same
390 as the BA field in the same instruction. */
391 #define BBA BB + 1
392 { 5, 11, extract_bba, PPC_OPERAND_FAKE },
393
394 /* The BD field in a B form instruction. The lower two bits are
395 forced to zero. */
396 #define BD BBA + 1
397 { 16, 0, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
398
399 /* The BD field in a B form instruction when absolute addressing is
400 used. */
401 #define BDA BD + 1
402 { 16, 0, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
403
404 /* The BD field in a B form instruction when the - modifier is used.
405 This sets the y bit of the BO field appropriately. */
406 #define BDM BDA + 1
407 { 16, 0, extract_bdm,
408 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
409
410 /* The BD field in a B form instruction when the - modifier is used
411 and absolute address is used. */
412 #define BDMA BDM + 1
413 { 16, 0, extract_bdm,
414 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
415
416 /* The BD field in a B form instruction when the + modifier is used.
417 This sets the y bit of the BO field appropriately. */
418 #define BDP BDMA + 1
419 { 16, 0, extract_bdp,
420 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
421
422 /* The BD field in a B form instruction when the + modifier is used
423 and absolute addressing is used. */
424 #define BDPA BDP + 1
425 { 16, 0, extract_bdp,
426 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
427
428 /* The BF field in an X or XL form instruction. */
429 #define BF BDPA + 1
430 { 3, 23, 0, PPC_OPERAND_CR },
431
432 /* An optional BF field. This is used for comparison instructions,
433 in which an omitted BF field is taken as zero. */
434 #define OBF BF + 1
435 { 3, 23, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
436
437 /* The BFA field in an X or XL form instruction. */
438 #define BFA OBF + 1
439 { 3, 18, 0, PPC_OPERAND_CR },
440
441 /* The BI field in a B form or XL form instruction. */
442 #define BI BFA + 1
443 #define BI_MASK (0x1f << 16)
444 { 5, 16, 0, PPC_OPERAND_CR },
445
446 /* The BO field in a B form instruction. Certain values are
447 illegal. */
448 #define BO BI + 1
449 #define BO_MASK (0x1f << 21)
450 { 5, 21, extract_bo, 0 },
451
452 /* The BO field in a B form instruction when the + or - modifier is
453 used. This is like the BO field, but it must be even. */
454 #define BOE BO + 1
455 { 5, 21, extract_boe, 0 },
456
457 /* The BT field in an X or XL form instruction. */
458 #define BT BOE + 1
459 { 5, 21, 0, PPC_OPERAND_CR },
460
461 /* The condition register number portion of the BI field in a B form
462 or XL form instruction. This is used for the extended
463 conditional branch mnemonics, which set the lower two bits of the
464 BI field. This field is optional. */
465 #define CR BT + 1
466 { 3, 18, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
467
468 /* The CRB field in an X form instruction. */
469 #define CRB CR + 1
470 { 5, 6, 0, 0 },
471
472 /* The CRFD field in an X form instruction. */
473 #define CRFD CRB + 1
474 { 3, 23, 0, PPC_OPERAND_CR },
475
476 /* The CRFS field in an X form instruction. */
477 #define CRFS CRFD + 1
478 { 3, 0, 0, PPC_OPERAND_CR },
479
480 /* The CT field in an X form instruction. */
481 #define CT CRFS + 1
482 { 5, 21, 0, PPC_OPERAND_OPTIONAL },
483
484 /* The D field in a D form instruction. This is a displacement off
485 a register, and implies that the next operand is a register in
486 parentheses. */
487 #define D CT + 1
488 { 16, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
489
490 /* The DE field in a DE form instruction. This is like D, but is 12
491 bits only. */
492 #define DE D + 1
493 { 14, 0, extract_de, PPC_OPERAND_PARENS },
494
495 /* The DES field in a DES form instruction. This is like DS, but is 14
496 bits only (12 stored.) */
497 #define DES DE + 1
498 { 14, 0, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
499
500 /* The DQ field in a DQ form instruction. This is like D, but the
501 lower four bits are forced to zero. */
502 #define DQ DES + 1
503 { 16, 0, extract_dq,
504 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
505
506 /* The DS field in a DS form instruction. This is like D, but the
507 lower two bits are forced to zero. */
508 #define DS DQ + 1
509 { 16, 0, extract_ds,
510 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
511
512 /* The FLM field in an XFL form instruction. */
513 #define FLM DS + 1
514 { 8, 17, 0, 0 },
515
516 /* The FRA field in an X or A form instruction. */
517 #define FRA FLM + 1
518 #define FRA_MASK (0x1f << 16)
519 { 5, 16, 0, PPC_OPERAND_FPR },
520
521 /* The FRB field in an X or A form instruction. */
522 #define FRB FRA + 1
523 #define FRB_MASK (0x1f << 11)
524 { 5, 11, 0, PPC_OPERAND_FPR },
525
526 /* The FRC field in an A form instruction. */
527 #define FRC FRB + 1
528 #define FRC_MASK (0x1f << 6)
529 { 5, 6, 0, PPC_OPERAND_FPR },
530
531 /* The FRS field in an X form instruction or the FRT field in a D, X
532 or A form instruction. */
533 #define FRS FRC + 1
534 #define FRT FRS
535 { 5, 21, 0, PPC_OPERAND_FPR },
536
537 /* The FXM field in an XFX instruction. */
538 #define FXM FRS + 1
539 #define FXM_MASK (0xff << 12)
540 { 8, 12, 0, 0 },
541
542 /* The L field in a D or X form instruction. */
543 #define L FXM + 1
544 { 1, 21, 0, PPC_OPERAND_OPTIONAL },
545
546 /* The LI field in an I form instruction. The lower two bits are
547 forced to zero. */
548 #define LI L + 1
549 { 26, 0, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
550
551 /* The LI field in an I form instruction when used as an absolute
552 address. */
553 #define LIA LI + 1
554 { 26, 0, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
555
556 /* The LS field in an X (sync) form instruction. */
557 #define LS LIA + 1
558 { 2, 21, 0, PPC_OPERAND_OPTIONAL },
559
560 /* The MB field in an M form instruction. */
561 #define MB LS + 1
562 #define MB_MASK (0x1f << 6)
563 { 5, 6, 0, 0 },
564
565 /* The ME field in an M form instruction. */
566 #define ME MB + 1
567 #define ME_MASK (0x1f << 1)
568 { 5, 1, 0, 0 },
569
570 /* The MB and ME fields in an M form instruction expressed a single
571 operand which is a bitmask indicating which bits to select. This
572 is a two operand form using PPC_OPERAND_NEXT. See the
573 description in opcode/ppc.h for what this means. */
574 #define MBE ME + 1
575 { 5, 6, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
576 { 32, 0, extract_mbe, 0 },
577
578 /* The MB or ME field in an MD or MDS form instruction. The high
579 bit is wrapped to the low end. */
580 #define MB6 MBE + 2
581 #define ME6 MB6
582 #define MB6_MASK (0x3f << 5)
583 { 6, 5, extract_mb6, 0 },
584
585 #define MSLWI MB6 + 1
586 { 0, 0, extract_mbe_special1, PPC_OPERAND_FAKE },
587
588 #define MSRWI MSLWI + 1
589 { 0, 0, extract_mbe_special2, PPC_OPERAND_FAKE },
590
591 /* The MO field in an mbar instruction. */
592 #define MO MSRWI + 1
593 { 5, 21, 0, 0 },
594
595 /* The NB field in an X form instruction. The value 32 is stored as
596 0. */
597 #define NB MO + 1
598 { 6, 11, extract_nb, 0 },
599
600 /* The NSI field in a D form instruction. This is the same as the
601 SI field, only negated. */
602 #define NSI NB + 1
603 { 16, 0, extract_nsi, PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
604
605 /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */
606 #define RA NSI + 1
607 #define RAM RA
608 #define RAS RA
609 #define RAL RA
610 #define RA_MASK (0x1f << 16)
611 { 5, 16, 0, PPC_OPERAND_GPR },
612
613 /* As above, but 0 in the RA field means zero, not r0. */
614 #define RA0 RA + 1
615 #define RAQ RA0
616 { 5, 16, 0, PPC_OPERAND_GPR_0 },
617
618 /* The RB field in an X, XO, M, or MDS form instruction. */
619 #define RB RA0 + 1
620 #define RB_MASK (0x1f << 11)
621 { 5, 11, 0, PPC_OPERAND_GPR },
622
623 /* The RB field in an X form instruction when it must be the same as
624 the RS field in the instruction. This is used for extended
625 mnemonics like mr. */
626 #define RBS RB + 1
627 { 5, 1, extract_rbs, PPC_OPERAND_FAKE },
628
629 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
630 instruction or the RT field in a D, DS, X, XFX or XO form
631 instruction. */
632 #define RS RBS + 1
633 #define RT RS
634 #define RT_MASK (0x1f << 21)
635 { 5, 21, 0, PPC_OPERAND_GPR },
636
637 /* The RS field of the DS form stq instruction, which has special
638 value restrictions. */
639 #define RSQ RS + 1
640 { 5, 21, 0, PPC_OPERAND_GPR_0 },
641
642 /* The RT field of the DQ form lq instruction, which has special
643 value restrictions. */
644 #define RTQ RSQ + 1
645 { 5, 21, 0, PPC_OPERAND_GPR_0 },
646
647 /* The SH field in an X or M form instruction. */
648 #define SH RTQ + 1
649 #define SH_MASK (0x1f << 11)
650 { 5, 11, 0, 0 },
651
652 /* The SH field in an MD form instruction. This is split. */
653 #define SH6 SH + 1
654 #define SH6_MASK ((0x1f << 11) | (1 << 1))
655 { 6, 1, extract_sh6, 0 },
656
657 /* The SI field in a D form instruction. */
658 #define SI SH6 + 1
659 { 16, 0, 0, PPC_OPERAND_SIGNED },
660
661 /* The SI field in a D form instruction when we accept a wide range
662 of positive values. */
663 #define SISIGNOPT SI + 1
664 { 16, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
665
666 /* The SPR field in an XFX form instruction. This is flipped--the
667 lower 5 bits are stored in the upper 5 and vice- versa. */
668 #define SPR SISIGNOPT + 1
669 #define PMR SPR
670 #define SPR_MASK (0x3ff << 11)
671 { 10, 11, extract_spr, 0 },
672
673 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
674 #define SPRBAT SPR + 1
675 #define SPRBAT_MASK (0x3 << 17)
676 { 2, 17, 0, 0 },
677
678 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
679 #define SPRG SPRBAT + 1
680 #define SPRG_MASK (0x3 << 16)
681 { 2, 16, 0, 0 },
682
683 /* The SR field in an X form instruction. */
684 #define SR SPRG + 1
685 { 4, 16, 0, 0 },
686
687 /* The STRM field in an X AltiVec form instruction. */
688 #define STRM SR + 1
689 #define STRM_MASK (0x3 << 21)
690 { 2, 21, 0, 0 },
691
692 /* The SV field in a POWER SC form instruction. */
693 #define SV STRM + 1
694 { 14, 2, 0, 0 },
695
696 /* The TBR field in an XFX form instruction. This is like the SPR
697 field, but it is optional. */
698 #define TBR SV + 1
699 { 10, 11, extract_tbr, PPC_OPERAND_OPTIONAL },
700
701 /* The TO field in a D or X form instruction. */
702 #define TO TBR + 1
703 #define TO_MASK (0x1f << 21)
704 { 5, 21, 0, 0 },
705
706 /* The U field in an X form instruction. */
707 #define U TO + 1
708 { 4, 12, 0, 0 },
709
710 /* The UI field in a D form instruction. */
711 #define UI U + 1
712 { 16, 0, 0, 0 },
713
714 /* The VA field in a VA, VX or VXR form instruction. */
715 #define VA UI + 1
716 #define VA_MASK (0x1f << 16)
717 { 5, 16, 0, PPC_OPERAND_VR },
718
719 /* The VB field in a VA, VX or VXR form instruction. */
720 #define VB VA + 1
721 #define VB_MASK (0x1f << 11)
722 { 5, 11, 0, PPC_OPERAND_VR },
723
724 /* The VB field in a VA, VX or VXR form instruction. */
725 #define VAB VB + 1
726 #define VAB_MASK (0x1f << 11)
727 { 5, 11, extract_vab, PPC_OPERAND_FAKE },
728
729 /* The VC field in a VA form instruction. */
730 #define VC VAB + 1
731 #define VC_MASK (0x1f << 6)
732 { 5, 6, 0, PPC_OPERAND_VR },
733
734 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
735 #define VD VC + 1
736 #define VS VD
737 #define VD_MASK (0x1f << 21)
738 { 5, 21, 0, PPC_OPERAND_VR },
739
740 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
741 #define VD128 VD + 1
742 #define VS128 VD128
743 #define VD128_MASK (0x1f << 21)
744 { 0, 0, extract_vds128, PPC_OPERAND_VR },
745
746 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
747 #define VA128 VD128 + 1
748 #define VA128_MASK (0x1f << 21)
749 { 0, 0, extract_va128, PPC_OPERAND_VR },
750
751 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
752 #define VB128 VA128 + 1
753 #define VB128_MASK (0x1f << 21)
754 { 0, 0, extract_vb128, PPC_OPERAND_VR },
755
756 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
757 #define VC128 VB128 + 1
758 #define VC128_MASK (0x1f << 21)
759 { 3, 6, 0, PPC_OPERAND_VR },
760
761 #define VPERM128 VC128 + 1
762 #define VPERM_MASK (0x1f << 21)
763 { 0, 0, extract_vperm, 0 },
764
765 #define VD3D0 VPERM128 + 1
766 { 3, 18, 0, 0 },
767
768 #define VD3D1 VD3D0 + 1
769 { 2, 16, 0, 0 },
770
771 #define VD3D2 VD3D1 + 1
772 { 2, 6, 0, 0 },
773
774 /* The SIMM field in a VX form instruction. */
775 #define SIMM VD3D2 + 1
776 { 5, 16, 0, PPC_OPERAND_SIGNED},
777
778 /* The UIMM field in a VX form instruction. */
779 #define UIMM SIMM + 1
780 { 5, 16, 0, 0 },
781
782 /* The SHB field in a VA form instruction. */
783 #define SHB UIMM + 1
784 { 4, 6, 0, 0 },
785
786 /* The WS field. */
787 #define WS SHB + 1
788 #define WS_MASK (0x7 << 11)
789 { 3, 11, 0, 0 },
790
791 /* The L field in an mtmsrd instruction */
792 #define MTMSRD_L WS + 1
793 { 1, 16, 0, PPC_OPERAND_OPTIONAL },
794
795 /* The DCM field in a Z form instruction. */
796 #define DCM MTMSRD_L + 1
797 #define DGM DCM
798 { 6, 16, 0, 0 },
799
800 #define TE DGM + 1
801 { 5, 11, 0, 0 },
802
803 #define RMC TE + 1
804 { 2, 21, 0, 0 },
805
806 #define R RMC + 1
807 { 1, 15, 0, 0 },
808
809 #define SP R + 1
810 { 2, 11, 0, 0 },
811
812 #define S SP + 1
813 { 1, 11, 0, 0 },
814
815 /* SH field starting at bit position 16. */
816 #define SH16 S + 1
817 { 6, 10, 0, 0 },
818 };
819
820
821 /* Macros used to form opcodes. */
822
823 /* The main opcode. */
824 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
825 #define OP_MASK OP (0x3f)
826
827 /* The main opcode combined with a trap code in the TO field of a D
828 form instruction. Used for extended mnemonics for the trap
829 instructions. */
830 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
831 #define OPTO_MASK (OP_MASK | TO_MASK)
832
833 /* The main opcode combined with a comparison size bit in the L field
834 of a D form or X form instruction. Used for extended mnemonics for
835 the comparison instructions. */
836 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
837 #define OPL_MASK OPL (0x3f,1)
838
839 /* An A form instruction. */
840 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
841 #define A_MASK A (0x3f, 0x1f, 1)
842
843 /* An A_MASK with the FRB field fixed. */
844 #define AFRB_MASK (A_MASK | FRB_MASK)
845
846 /* An A_MASK with the FRC field fixed. */
847 #define AFRC_MASK (A_MASK | FRC_MASK)
848
849 /* An A_MASK with the FRA and FRC fields fixed. */
850 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
851
852 /* A B form instruction. */
853 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
854 #define B_MASK B (0x3f, 1, 1)
855
856 /* A B form instruction setting the BO field. */
857 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
858 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
859
860 /* A BBO_MASK with the y bit of the BO field removed. This permits
861 matching a conditional branch regardless of the setting of the y
862 bit. Similarly for the 'at' bits used for power4 branch hints. */
863 #define Y_MASK (((unsigned long) 1) << 21)
864 #define AT1_MASK (((unsigned long) 3) << 21)
865 #define AT2_MASK (((unsigned long) 9) << 21)
866 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
867 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
868
869 /* A B form instruction setting the BO field and the condition bits of
870 the BI field. */
871 #define BBOCB(op, bo, cb, aa, lk) \
872 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
873 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
874
875 /* A BBOCB_MASK with the y bit of the BO field removed. */
876 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
877 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
878 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
879
880 /* A BBOYCB_MASK in which the BI field is fixed. */
881 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
882 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
883
884 /* An Context form instruction. */
885 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
886 #define CTX_MASK CTX(0x3f, 0x7)
887
888 /* An User Context form instruction. */
889 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
890 #define UCTX_MASK UCTX(0x3f, 0x1f)
891
892 /* The main opcode mask with the RA field clear. */
893 #define DRA_MASK (OP_MASK | RA_MASK)
894
895 /* A DS form instruction. */
896 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
897 #define DS_MASK DSO (0x3f, 3)
898
899 /* A DE form instruction. */
900 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
901 #define DE_MASK DEO (0x3e, 0xf)
902
903 /* An EVSEL form instruction. */
904 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
905 #define EVSEL_MASK EVSEL(0x3f, 0xff)
906
907 /* An M form instruction. */
908 #define M(op, rc) (OP (op) | ((rc) & 1))
909 #define M_MASK M (0x3f, 1)
910
911 /* An M form instruction with the ME field specified. */
912 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
913
914 /* An M_MASK with the MB and ME fields fixed. */
915 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
916
917 /* An M_MASK with the SH and ME fields fixed. */
918 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
919
920 /* An MD form instruction. */
921 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
922 #define MD_MASK MD (0x3f, 0x7, 1)
923
924 /* An MD_MASK with the MB field fixed. */
925 #define MDMB_MASK (MD_MASK | MB6_MASK)
926
927 /* An MD_MASK with the SH field fixed. */
928 #define MDSH_MASK (MD_MASK | SH6_MASK)
929
930 /* An MDS form instruction. */
931 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
932 #define MDS_MASK MDS (0x3f, 0xf, 1)
933
934 /* An MDS_MASK with the MB field fixed. */
935 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
936
937 /* An SC form instruction. */
938 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
939 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
940
941 /* An VX form instruction. */
942 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
943
944 /* The mask for an VX form instruction. */
945 #define VX_MASK VX(0x3f, 0x7ff)
946
947 /* The mask for an VX form instruction. */
948 #define VX_MASK VX(0x3f, 0x7ff)
949
950 /* An VA form instruction. */
951 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
952
953 /* The mask for an VA form instruction. */
954 #define VXA_MASK VXA(0x3f, 0x3f)
955
956 /* An VXR form instruction. */
957 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
958
959 /* The mask for a VXR form instruction. */
960 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
961
962 /* An VX128 form instruction. */
963 #define VX128(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x3d0))
964
965 /* The mask for an VX form instruction. */
966 #define VX128_MASK VX(0x3f, 0x3d0)
967
968 /* An VX128 form instruction. */
969 #define VX128_1(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7f3))
970
971 /* The mask for an VX form instruction. */
972 #define VX128_1_MASK VX(0x3f, 0x7f3)
973
974 /* An VX128 form instruction. */
975 #define VX128_2(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x210))
976
977 /* The mask for an VX form instruction. */
978 #define VX128_2_MASK VX(0x3f, 0x210)
979
980 /* An VX128 form instruction. */
981 #define VX128_3(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7f0))
982
983 /* The mask for an VX form instruction. */
984 #define VX128_3_MASK VX(0x3f, 0x7f0)
985
986 #define VX128_P(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x630))
987 #define VX128_P_MASK VX(0x3f, 0x630)
988
989 #define VX128_4(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x730))
990 #define VX128_4_MASK VX(0x3f, 0x730)
991
992 #define VX128_5(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x10))
993 #define VX128_5_MASK VX(0x3f, 0x10)
994
995 /* An X form instruction. */
996 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
997
998 /* A Z form instruction. */
999 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1000
1001 /* An X form instruction with the RC bit specified. */
1002 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1003
1004 /* A Z form instruction with the RC bit specified. */
1005 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
1006
1007 /* The mask for an X form instruction. */
1008 #define X_MASK XRC (0x3f, 0x3ff, 1)
1009
1010 /* The mask for a Z form instruction. */
1011 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
1012
1013 /* An X_MASK with the RA field fixed. */
1014 #define XRA_MASK (X_MASK | RA_MASK)
1015
1016 /* An X_MASK with the RB field fixed. */
1017 #define XRB_MASK (X_MASK | RB_MASK)
1018
1019 /* An X_MASK with the RT field fixed. */
1020 #define XRT_MASK (X_MASK | RT_MASK)
1021
1022 /* An X_MASK with the RA and RB fields fixed. */
1023 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1024
1025 /* An XRARB_MASK, but with the L bit clear. */
1026 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1027
1028 /* An X_MASK with the RT and RA fields fixed. */
1029 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1030
1031 /* An XRTRA_MASK, but with L bit clear. */
1032 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1033
1034 /* An X form comparison instruction. */
1035 #define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1036
1037 /* The mask for an X form comparison instruction. */
1038 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1039
1040 /* The mask for an X form comparison instruction with the L field
1041 fixed. */
1042 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1043
1044 /* An X form instruction with the L bit specified. */
1045 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1046
1047 /* An X form trap instruction with the TO field specified. */
1048 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1049 #define XTO_MASK (X_MASK | TO_MASK)
1050
1051 /* An X form tlb instruction with the SH field specified. */
1052 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1053 #define XTLB_MASK (X_MASK | SH_MASK)
1054
1055 /* An X form sync instruction. */
1056 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1057
1058 /* An X form sync instruction with everything filled in except the LS field. */
1059 #define XSYNC_MASK (0xff9fffff)
1060
1061 /* An X form AltiVec dss instruction. */
1062 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1063 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1064
1065 /* An XFL form instruction. */
1066 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1067 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1068
1069 /* An X form isel instruction. */
1070 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1071 #define XISEL_MASK XISEL(0x3f, 0x1f)
1072
1073 /* An XL form instruction with the LK field set to 0. */
1074 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1075
1076 /* An XL form instruction which uses the LK field. */
1077 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1078
1079 /* The mask for an XL form instruction. */
1080 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1081
1082 /* An XL form instruction which explicitly sets the BO field. */
1083 #define XLO(op, bo, xop, lk) \
1084 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1085 #define XLO_MASK (XL_MASK | BO_MASK)
1086
1087 /* An XL form instruction which explicitly sets the y bit of the BO
1088 field. */
1089 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1090 #define XLYLK_MASK (XL_MASK | Y_MASK)
1091
1092 /* An XL form instruction which sets the BO field and the condition
1093 bits of the BI field. */
1094 #define XLOCB(op, bo, cb, xop, lk) \
1095 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1096 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1097
1098 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1099 #define XLBB_MASK (XL_MASK | BB_MASK)
1100 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1101 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1102
1103 /* An XL_MASK with the BO and BB fields fixed. */
1104 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1105
1106 /* An XL_MASK with the BO, BI and BB fields fixed. */
1107 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1108
1109 /* An XO form instruction. */
1110 #define XO(op, xop, oe, rc) \
1111 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1112 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1113
1114 /* An XO_MASK with the RB field fixed. */
1115 #define XORB_MASK (XO_MASK | RB_MASK)
1116
1117 /* An XS form instruction. */
1118 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1119 #define XS_MASK XS (0x3f, 0x1ff, 1)
1120
1121 /* A mask for the FXM version of an XFX form instruction. */
1122 #define XFXFXM_MASK (X_MASK | (((unsigned long)1) << 20) | (((unsigned long)1) << 11))
1123 #define XFXFXM_MASK2 (X_MASK | (((unsigned long)1) << 20))
1124
1125 /* An XFX form instruction with the FXM field filled in. */
1126 #define XFXM(op, xop, fxm) \
1127 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
1128
1129 /* An XFX form instruction with the SPR field filled in. */
1130 #define XSPR(op, xop, spr) \
1131 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1132 #define XSPR_MASK (X_MASK | SPR_MASK)
1133
1134 /* An XFX form instruction with the SPR field filled in except for the
1135 SPRBAT field. */
1136 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1137
1138 /* An XFX form instruction with the SPR field filled in except for the
1139 SPRG field. */
1140 #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1141
1142 /* An X form instruction with everything filled in except the E field. */
1143 #define XE_MASK (0xffff7fff)
1144
1145 /* An X form user context instruction. */
1146 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1147 #define XUC_MASK XUC(0x3f, 0x1f)
1148
1149 /* The BO encodings used in extended conditional branch mnemonics. */
1150 #define BODNZF (0x0)
1151 #define BODNZFP (0x1)
1152 #define BODZF (0x2)
1153 #define BODZFP (0x3)
1154 #define BODNZT (0x8)
1155 #define BODNZTP (0x9)
1156 #define BODZT (0xa)
1157 #define BODZTP (0xb)
1158
1159 #define BOF (0x4)
1160 #define BOFP (0x5)
1161 #define BOFM4 (0x6)
1162 #define BOFP4 (0x7)
1163 #define BOT (0xc)
1164 #define BOTP (0xd)
1165 #define BOTM4 (0xe)
1166 #define BOTP4 (0xf)
1167
1168 #define BODNZ (0x10)
1169 #define BODNZP (0x11)
1170 #define BODZ (0x12)
1171 #define BODZP (0x13)
1172 #define BODNZM4 (0x18)
1173 #define BODNZP4 (0x19)
1174 #define BODZM4 (0x1a)
1175 #define BODZP4 (0x1b)
1176
1177 #define BOU (0x14)
1178
1179 /* The BI condition bit encodings used in extended conditional branch
1180 mnemonics. */
1181 #define CBLT (0)
1182 #define CBGT (1)
1183 #define CBEQ (2)
1184 #define CBSO (3)
1185
1186 /* The TO encodings used in extended trap mnemonics. */
1187 #define TOLGT (0x1)
1188 #define TOLLT (0x2)
1189 #define TOEQ (0x4)
1190 #define TOLGE (0x5)
1191 #define TOLNL (0x5)
1192 #define TOLLE (0x6)
1193 #define TOLNG (0x6)
1194 #define TOGT (0x8)
1195 #define TOGE (0xc)
1196 #define TONL (0xc)
1197 #define TOLT (0x10)
1198 #define TOLE (0x14)
1199 #define TONG (0x14)
1200 #define TONE (0x18)
1201 #define TOU (0x1f)
1202
1203 /* Smaller names for the flags so each entry in the opcodes table will
1204 fit on a single line. */
1205 #undef PPC
1206 #define PPC PPC_OPCODE_PPC
1207 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1208 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1209 #define POWER4 PPC_OPCODE_POWER4
1210 #define POWER5 0
1211 #define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
1212 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
1213 #define PPC403 PPC_OPCODE_403
1214 #define PPC405 PPC403
1215 #define PPC440 PPC_OPCODE_440
1216 #define PPC750 PPC
1217 #define PPC860 PPC
1218 #define PPCVEC PPC_OPCODE_ALTIVEC
1219 #define CELL 0
1220 #define POWER6 0
1221 #define POWER PPC_OPCODE_POWER
1222 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1223 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1224 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1225 #define PPCONLY PPC_OPCODE_PPC
1226 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1227 #define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1228 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
1229 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1230 #define MFDEC1 PPC_OPCODE_POWER
1231 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1232 #define BOOKE PPC_OPCODE_BOOKE
1233 #define BOOKE64 PPC_OPCODE_BOOKE64
1234 #define CLASSIC PPC_OPCODE_CLASSIC
1235 #define PPCE300 PPC_OPCODE_E300
1236 #define PPCSPE PPC_OPCODE_SPE
1237 #define PPCISEL PPC_OPCODE_ISEL
1238 #define PPCEFS PPC_OPCODE_EFS
1239 #define PPCBRLK PPC_OPCODE_BRLOCK
1240 #define PPCPMR PPC_OPCODE_PMR
1241 #define PPCCHLK PPC_OPCODE_CACHELCK
1242 #define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1243 #define PPCRFMCI PPC_OPCODE_RFMCI
1244
1245 /* The opcode table.
1246
1247 The format of the opcode table is:
1248
1249 NAME OPCODE MASK FLAGS { OPERANDS }
1250
1251 NAME is the name of the instruction.
1252 OPCODE is the instruction opcode.
1253 MASK is the opcode mask; this is used to tell the disassembler
1254 which bits in the actual opcode must match OPCODE.
1255 FLAGS are flags indicated what processors support the instruction.
1256 OPERANDS is the list of operands.
1257
1258 The disassembler reads the table in order and prints the first
1259 instruction which matches, so this table is sorted to put more
1260 specific instructions before more general instructions. It is also
1261 sorted by major opcode. */
1262
1263 const struct powerpc_opcode powerpc_opcodes[] = {
1264
1265 { "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
1266 { "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
1267 { "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
1268 { "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
1269 { "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
1270 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1271 { "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
1272 { "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
1273 { "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
1274 { "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
1275 { "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
1276 { "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
1277 { "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
1278 { "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
1279 { "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
1280
1281 { "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
1282 { "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
1283 { "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
1284 { "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
1285 { "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
1286 { "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
1287 { "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
1288 { "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
1289 { "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
1290 { "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
1291 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1292 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
1293 { "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
1294 { "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
1295 { "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
1296 { "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
1297 { "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
1298 { "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
1299 { "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
1300 { "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
1301 { "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
1302 { "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
1303 { "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
1304 { "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
1305 { "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
1306 { "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
1307 { "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
1308 { "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
1309 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
1310 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
1311
1312 { "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
1313 { "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
1314 { "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
1315 { "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
1316 { "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
1317 { "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
1318 { "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
1319 { "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
1320 { "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
1321 { "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
1322 { "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
1323 { "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
1324 { "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
1325 { "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
1326 { "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
1327 { "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
1328 { "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
1329 { "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
1330 { "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
1331 { "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
1332 { "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
1333 { "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1334 { "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1335 { "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1336 { "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1337 { "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1338 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1339 { "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1340 { "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1341 { "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1342 { "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1343 { "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1344 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1345 { "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1346 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1347 { "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1348 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1349 { "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1350 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1351 { "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1352 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1353 { "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1354 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1355 { "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1356 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1357 { "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1358 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1359 { "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1360 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1361 { "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1362 { "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1363 { "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
1364 { "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
1365 { "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
1366 { "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
1367 { "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
1368 { "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
1369 { "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
1370 { "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
1371 { "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
1372 { "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
1373 { "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1374 { "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1375 { "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
1376 { "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
1377 { "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
1378 { "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
1379 { "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
1380 { "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
1381 { "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
1382 { "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1383 { "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
1384 { "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
1385 { "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
1386 { "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
1387 { "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
1388 { "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
1389 { "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1390 { "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1391 { "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1392 { "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1393 { "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1394 { "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1395 { "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
1396 { "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
1397 { "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
1398 { "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
1399 { "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
1400 { "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
1401 { "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
1402 { "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
1403 { "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
1404 { "vnot", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VAB } },
1405 { "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
1406 { "vmr", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VAB } },
1407 { "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
1408 { "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1409 { "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
1410 { "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
1411 { "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
1412 { "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
1413 { "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
1414 { "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
1415 { "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
1416 { "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
1417 { "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
1418 { "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
1419 { "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
1420 { "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
1421 { "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
1422 { "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
1423 { "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
1424 { "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
1425 { "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
1426 { "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
1427 { "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1428 { "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
1429 { "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
1430 { "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
1431 { "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
1432 { "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
1433 { "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
1434 { "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1435 { "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1436 { "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
1437 { "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
1438 { "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
1439 { "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1440 { "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
1441 { "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
1442 { "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
1443 { "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
1444 { "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
1445 { "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
1446 { "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
1447 { "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
1448 { "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
1449 { "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
1450 { "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
1451 { "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
1452 { "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
1453 { "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
1454 { "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
1455 { "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
1456 { "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
1457 { "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
1458 { "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
1459 { "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
1460 { "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
1461 { "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
1462 { "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
1463 { "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
1464 { "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
1465 { "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
1466 { "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
1467 { "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
1468 { "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
1469 { "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
1470 { "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
1471
1472 { "vsldoi128", VX128_5(4, 16), VX128_5_MASK, PPCVEC, { VS128, VA128, VB128, SHB } },
1473 { "lvsl128", VX128_1(4, 3), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },
1474 { "lvsr128", VX128_1(4, 67), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },
1475 { "lvewx128", VX128_1(4, 131), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },
1476 { "lvx128", VX128_1(4, 195), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },
1477 { "stvewx128", VX128_1(4, 387), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },
1478 { "stvx128", VX128_1(4, 451), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },
1479 { "lvxl128", VX128_1(4, 707), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },
1480 { "stvxl128", VX128_1(4, 963), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },
1481 { "lvlx128", VX128_1(4, 1027), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },
1482 { "lvrx128", VX128_1(4, 1091), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },
1483 { "stvlx128", VX128_1(4, 1283), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },
1484 { "stvrx128", VX128_1(4, 1347), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },
1485 { "lvlxl128", VX128_1(4, 1539), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },
1486 { "lvrxl128", VX128_1(4, 1603), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },
1487 { "stvlxl128", VX128_1(4, 1795), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },
1488 { "stvrxl128", VX128_1(4, 1859), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },
1489
1490 { "vperm128", VX128_2(5, 0), VX128_2_MASK, PPCVEC, { VD128, VA128, VB128, VC128 } },
1491 { "vaddfp128", VX128(5, 16), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1492 { "vsubfp128", VX128(5, 80), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1493 { "vmulfp128", VX128(5, 144), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1494 { "vmaddfp128", VX128(5, 208), VX128_MASK, PPCVEC, { VD128, VA128, VB128, VS128 } },
1495 { "vmaddcfp128",VX128(5, 272), VX128_MASK, PPCVEC, { VD128, VA128, VS128, VB128 } },
1496 { "vnmsubfp128",VX128(5, 336), VX128_MASK, PPCVEC, { VD128, VA128, VB128, VS128 } },
1497 { "vmsum3fp128",VX128(5, 400), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1498 { "vmsum4fp128",VX128(5, 464), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1499 { "vpkshss128", VX128(5, 512), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1500 { "vand128", VX128(5, 528), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1501 { "vpkshus128", VX128(5, 576), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1502 { "vandc128", VX128(5, 592), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1503 { "vpkswss128", VX128(5, 640), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1504 { "vnor128", VX128(5, 656), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1505 { "vpkswus128", VX128(5, 704), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1506 { "vor128", VX128(5, 720), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1507 { "vpkuhum128", VX128(5, 768), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1508 { "vxor128", VX128(5, 784), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1509 { "vpkuhus128", VX128(5, 832), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1510 { "vsel128", VX128(5, 848), VX128_MASK, PPCVEC, { VD128, VA128, VB128, VS128 } },
1511 { "vpkuwum128", VX128(5, 896), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1512 { "vslo128", VX128(5, 912), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1513 { "vpkuwus128", VX128(5, 960), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1514 { "vsro128", VX128(5, 976), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1515
1516 { "vpermwi128", VX128_P(6, 528), VX128_P_MASK, PPCVEC, { VD128, VB128, VPERM128 } },
1517 { "vcfpsxws128", VX128_3(6, 560), VX128_3_MASK, PPCVEC, { VD128, VB128, SIMM } },
1518 { "vcfpuxws128", VX128_3(6, 624), VX128_3_MASK, PPCVEC, { VD128, VB128, UIMM } },
1519 { "vcsxwfp128", VX128_3(6, 688), VX128_3_MASK, PPCVEC, { VD128, VB128, SIMM } },
1520 { "vcuxwfp128", VX128_3(6, 752), VX128_3_MASK, PPCVEC, { VD128, VB128, UIMM } },
1521 { "vrfim128", VX128_3(6, 816), VX128_3_MASK, PPCVEC, { VD128, VB128 } },
1522 { "vrfin128", VX128_3(6, 880), VX128_3_MASK, PPCVEC, { VD128, VB128 } },
1523 { "vrfip128", VX128_3(6, 944), VX128_3_MASK, PPCVEC, { VD128, VB128 } },
1524 { "vrfiz128", VX128_3(6, 1008), VX128_3_MASK, PPCVEC, { VD128, VB128 } },
1525 { "vpkd3d128", VX128_4(6, 1552), VX128_4_MASK, PPCVEC, { VD128, VB128, VD3D0, VD3D1, VD3D2} },
1526 { "vrefp128", VX128_3(6, 1584), VX128_3_MASK, PPCVEC, { VD128, VB128 } },
1527 { "vrsqrtefp128",VX128_3(6, 1648), VX128_3_MASK, PPCVEC, { VD128, VB128 } },
1528 { "vexptefp128", VX128_3(6, 1712), VX128_3_MASK, PPCVEC, { VD128, VB128 } },
1529 { "vlogefp128", VX128_3(6, 1776), VX128_3_MASK, PPCVEC, { VD128, VB128 } },
1530 { "vrlimi128", VX128_4(6, 1808), VX128_4_MASK, PPCVEC, { VD128, VB128, UIMM, VD3D2} },
1531 { "vspltw128", VX128_3(6, 1840), VX128_3_MASK, PPCVEC, { VD128, VB128, UIMM } },
1532 { "vspltisw128", VX128_3(6, 1904), VX128_3_MASK, PPCVEC, { VD128, VB128, SIMM } },
1533 { "vupkd3d128", VX128_3(6, 2032), VX128_3_MASK, PPCVEC, { VD128, VB128, UIMM } },
1534 { "vcmpeqfp128", VX128(6, 0), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1535 { "vcmpeqfp128.",VX128(6, 64), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1536 { "vrlw128", VX128(6, 80), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1537 { "vcmpgefp128", VX128(6, 128), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1538 { "vcmpgefp128.",VX128(6, 192), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1539 { "vslw128", VX128(6, 208), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1540 { "vcmpgtfp128", VX128(6, 256), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1541 { "vcmpgtfp128.",VX128(6, 320), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1542 { "vsraw128", VX128(6, 336), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1543 { "vcmpbfp128", VX128(6, 384), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1544 { "vcmpbfp128.", VX128(6, 448), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1545 { "vsrw128", VX128(6, 464), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1546 { "vcmpequw128", VX128(6, 512), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1547 { "vcmpequw128.",VX128(6, 576), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1548 { "vmaxfp128", VX128(6, 640), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1549 { "vminfp128", VX128(6, 704), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1550 { "vmrghw128", VX128(6, 768), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1551 { "vmrglw128", VX128(6, 832), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },
1552 { "vupkhsb128", VX128(6, 896), VX128_MASK, PPCVEC, { VD128, VB128 } },
1553 { "vupklsb128", VX128(6, 960), VX128_MASK, PPCVEC, { VD128, VB128 } },
1554
1555 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
1556
1557 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
1558
1559 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
1560 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
1561 { "cmpli", OP(10), OP_MASK, PPCONLY, { BF, L, RA, UI } },
1562
1563 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
1564 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
1565 { "cmpi", OP(11), OP_MASK, PPCONLY, { BF, L, RA, SI } },
1566
1567 { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
1568 { "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
1569
1570 { "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
1571 { "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
1572
1573 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
1574 { "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } },
1575 { "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } },
1576 { "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA } },
1577
1578 { "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
1579 { "addis", OP(15), OP_MASK, PPCCOM, { RT, RA0, SISIGNOPT } },
1580 { "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } },
1581
1582 { "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
1583 { "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
1584 { "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
1585 { "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
1586 { "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
1587 { "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
1588 { "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
1589 { "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
1590 { "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
1591 { "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
1592 { "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
1593 { "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
1594 { "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
1595 { "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
1596 { "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
1597 { "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
1598 { "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
1599 { "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
1600 { "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
1601 { "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
1602 { "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
1603 { "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
1604 { "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
1605 { "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
1606 { "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1607 { "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1608 { "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
1609 { "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1610 { "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1611 { "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
1612 { "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1613 { "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1614 { "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
1615 { "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1616 { "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1617 { "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
1618 { "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1619 { "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1620 { "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
1621 { "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1622 { "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1623 { "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
1624 { "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1625 { "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1626 { "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
1627 { "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1628 { "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1629 { "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
1630 { "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1631 { "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1632 { "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
1633 { "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1634 { "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1635 { "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
1636 { "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1637 { "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1638 { "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
1639 { "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1640 { "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1641 { "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
1642 { "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1643 { "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1644 { "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
1645 { "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1646 { "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1647 { "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
1648 { "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1649 { "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1650 { "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
1651 { "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1652 { "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1653 { "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
1654 { "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1655 { "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1656 { "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
1657 { "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1658 { "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1659 { "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
1660 { "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1661 { "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1662 { "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
1663 { "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1664 { "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1665 { "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
1666 { "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1667 { "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1668 { "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
1669 { "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1670 { "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1671 { "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
1672 { "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1673 { "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1674 { "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
1675 { "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1676 { "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1677 { "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
1678 { "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1679 { "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1680 { "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
1681 { "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1682 { "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1683 { "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
1684 { "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1685 { "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1686 { "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
1687 { "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1688 { "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1689 { "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
1690 { "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1691 { "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1692 { "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
1693 { "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1694 { "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1695 { "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
1696 { "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1697 { "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1698 { "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
1699 { "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1700 { "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1701 { "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
1702 { "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1703 { "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1704 { "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
1705 { "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1706 { "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1707 { "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
1708 { "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1709 { "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1710 { "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
1711 { "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1712 { "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1713 { "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
1714 { "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1715 { "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1716 { "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
1717 { "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1718 { "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1719 { "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
1720 { "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1721 { "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1722 { "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
1723 { "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1724 { "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1725 { "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
1726 { "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1727 { "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1728 { "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
1729 { "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1730 { "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1731 { "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
1732 { "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1733 { "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1734 { "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
1735 { "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1736 { "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1737 { "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
1738 { "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1739 { "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1740 { "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
1741 { "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1742 { "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1743 { "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
1744 { "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1745 { "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1746 { "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
1747 { "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1748 { "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1749 { "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
1750 { "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
1751 { "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
1752 { "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
1753 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
1754 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
1755 { "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
1756 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
1757 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
1758 { "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
1759 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
1760 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
1761 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
1762 { "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
1763 { "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
1764 { "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
1765 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
1766 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
1767 { "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
1768 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
1769 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
1770 { "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
1771 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
1772 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
1773 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
1774 { "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
1775 { "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
1776 { "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
1777 { "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
1778 { "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
1779 { "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
1780 { "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
1781 { "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
1782 { "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
1783 { "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
1784 { "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
1785 { "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
1786 { "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
1787 { "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
1788 { "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
1789 { "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
1790 { "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
1791 { "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
1792 { "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
1793 { "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
1794 { "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
1795 { "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
1796 { "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
1797 { "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
1798 { "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
1799 { "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
1800 { "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
1801 { "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
1802 { "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
1803 { "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
1804 { "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
1805 { "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
1806 { "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
1807 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
1808 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
1809 { "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
1810 { "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
1811 { "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
1812 { "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
1813 { "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
1814 { "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
1815 { "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
1816 { "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
1817 { "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
1818 { "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
1819 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
1820 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
1821 { "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
1822 { "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } },
1823 { "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } },
1824 { "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
1825 { "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } },
1826 { "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } },
1827 { "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
1828 { "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } },
1829 { "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } },
1830 { "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } },
1831 { "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } },
1832 { "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
1833 { "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
1834
1835 { "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
1836
1837 { "b", B(18,0,0), B_MASK, COM, { LI } },
1838 { "bl", B(18,0,1), B_MASK, COM, { LI } },
1839 { "ba", B(18,1,0), B_MASK, COM, { LIA } },
1840 { "bla", B(18,1,1), B_MASK, COM, { LIA } },
1841
1842 { "mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
1843
1844 { "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
1845 { "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
1846 { "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
1847 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
1848 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
1849 { "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
1850 { "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
1851 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
1852 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
1853 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
1854 { "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
1855 { "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
1856 { "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
1857 { "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
1858 { "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
1859 { "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
1860 { "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
1861 { "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
1862 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
1863 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
1864 { "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
1865 { "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
1866 { "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1867 { "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
1868 { "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
1869 { "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
1870 { "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
1871 { "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1872 { "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1873 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
1874 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
1875 { "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
1876 { "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
1877 { "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1878 { "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1879 { "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
1880 { "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
1881 { "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
1882 { "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
1883 { "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1884 { "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1885 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
1886 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
1887 { "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
1888 { "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
1889 { "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1890 { "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1891 { "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
1892 { "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
1893 { "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
1894 { "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
1895 { "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1896 { "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1897 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
1898 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
1899 { "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
1900 { "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
1901 { "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1902 { "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1903 { "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
1904 { "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
1905 { "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
1906 { "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
1907 { "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1908 { "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1909 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
1910 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
1911 { "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
1912 { "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
1913 { "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1914 { "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1915 { "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
1916 { "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
1917 { "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
1918 { "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
1919 { "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1920 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
1921 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
1922 { "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
1923 { "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
1924 { "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1925 { "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
1926 { "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
1927 { "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
1928 { "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
1929 { "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1930 { "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1931 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
1932 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
1933 { "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
1934 { "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
1935 { "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1936 { "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1937 { "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
1938 { "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
1939 { "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
1940 { "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
1941 { "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1942 { "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1943 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
1944 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
1945 { "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
1946 { "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
1947 { "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1948 { "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1949 { "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
1950 { "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
1951 { "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
1952 { "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
1953 { "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1954 { "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1955 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
1956 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
1957 { "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
1958 { "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
1959 { "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1960 { "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1961 { "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
1962 { "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
1963 { "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
1964 { "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
1965 { "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1966 { "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1967 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
1968 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
1969 { "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
1970 { "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
1971 { "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1972 { "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1973 { "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
1974 { "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
1975 { "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
1976 { "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
1977 { "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1978 { "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1979 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
1980 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
1981 { "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
1982 { "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
1983 { "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1984 { "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1985 { "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
1986 { "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
1987 { "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
1988 { "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
1989 { "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1990 { "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1991 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
1992 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
1993 { "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
1994 { "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
1995 { "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1996 { "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1997 { "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
1998 { "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
1999 { "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2000 { "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2001 { "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2002 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2003 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2004 { "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2005 { "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2006 { "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2007 { "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2008 { "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2009 { "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2010 { "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2011 { "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2012 { "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2013 { "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2014 { "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2015 { "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2016 { "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2017 { "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2018 { "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2019 { "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2020 { "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2021 { "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2022 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2023 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2024 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2025 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2026 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2027 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2028 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2029 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2030 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2031 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2032 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2033 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2034 { "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2035 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2036 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2037 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2038 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2039 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2040 { "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2041 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2042 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2043 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2044 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2045 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2046 { "bclr", XLLK(19,16,0), XLYBB_MASK, PPCCOM, { BO, BI } },
2047 { "bclrl", XLLK(19,16,1), XLYBB_MASK, PPCCOM, { BO, BI } },
2048 { "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2049 { "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2050 { "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2051 { "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2052 { "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
2053 { "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
2054
2055 { "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
2056
2057 { "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
2058 { "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
2059 // XXX
2060 { "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } },
2061
2062 { "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
2063
2064 { "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
2065
2066 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
2067
2068 { "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2069 { "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
2070
2071 { "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
2072
2073 { "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
2074
2075 { "hrfid", XL(19,274), 0xffffffff, POWER5 | CELL, { 0 } },
2076
2077 { "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2078 { "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
2079
2080 { "doze", XL(19,402), 0xffffffff, POWER6, { 0 } },
2081
2082 { "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
2083
2084 { "nap", XL(19,434), 0xffffffff, POWER6, { 0 } },
2085
2086 { "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
2087 { "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
2088
2089 { "sleep", XL(19,466), 0xffffffff, POWER6, { 0 } },
2090 { "rvwinkle", XL(19,498), 0xffffffff, POWER6, { 0 } },
2091
2092 { "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
2093 { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
2094 { "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2095 { "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2096 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2097 { "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2098 { "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2099 { "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2100 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2101 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2102 { "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2103 { "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2104 { "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2105 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2106 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2107 { "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2108 { "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2109 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2110 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2111 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2112 { "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2113 { "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2114 { "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2115 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2116 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2117 { "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2118 { "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2119 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2120 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2121 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2122 { "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2123 { "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2124 { "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2125 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2126 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2127 { "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2128 { "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2129 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2130 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2131 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2132 { "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2133 { "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2134 { "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2135 { "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2136 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2137 { "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2138 { "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2139 { "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2140 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2141 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2142 { "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2143 { "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2144 { "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2145 { "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2146 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2147 { "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2148 { "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2149 { "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2150 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2151 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2152 { "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2153 { "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2154 { "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2155 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2156 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2157 { "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2158 { "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2159 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2160 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2161 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2162 { "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2163 { "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2164 { "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2165 { "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2166 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2167 { "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2168 { "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2169 { "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2170 { "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2171 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2172 { "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2173 { "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2174 { "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2175 { "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2176 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2177 { "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2178 { "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2179 { "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2180 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2181 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2182 { "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2183 { "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2184 { "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2185 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2186 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2187 { "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2188 { "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2189 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2190 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2191 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2192 { "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2193 { "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2194 { "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2195 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2196 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2197 { "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2198 { "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2199 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2200 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2201 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2202 { "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2203 { "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2204 { "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2205 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2206 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2207 { "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2208 { "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2209 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2210 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2211 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2212 { "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2213 { "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2214 { "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
2215 { "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
2216 { "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
2217 { "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
2218 { "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
2219 { "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
2220 { "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
2221 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
2222 { "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
2223 { "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
2224 { "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
2225 { "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
2226 { "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
2227 { "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
2228 { "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
2229 { "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
2230 { "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
2231 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
2232 { "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
2233 { "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
2234 { "bcctr", XLLK(19,528,0), XLYBB_MASK, PPCCOM, { BO, BI } },
2235 { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2236 { "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2237 { "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPCCOM, { BO, BI } },
2238 { "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2239 { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2240 { "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
2241 { "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
2242 { "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } },
2243 { "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } },
2244
2245 { "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2246
2247 { "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2248
2249 { "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
2250 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
2251 { "slwi", M(21, 0), M_MASK, PPCCOM, { RA, RS, SH, MSLWI } },
2252 { "srwi", M(21, 0), M_MASK, PPCCOM, { RA, RS, MB, MSRWI } },
2253 { "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2254 { "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
2255 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
2256 { "slwi.", M(21,1), M_MASK, PPCCOM, { RA, RS, SH, MSLWI } },
2257 { "srwi.", M(21,1), M_MASK, PPCCOM, { RA, RS, MB, MSRWI } },
2258 { "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2259
2260 { "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
2261 { "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
2262 { "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
2263 { "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
2264
2265 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
2266 { "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
2267
2268 { "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
2269
2270 { "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
2271
2272 { "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
2273
2274 { "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
2275
2276 { "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
2277
2278 { "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
2279 { "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
2280 { "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2281 { "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
2282 { "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
2283 { "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2284
2285 { "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
2286 { "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
2287
2288 { "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2289 { "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2290
2291 { "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2292 { "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2293
2294 { "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
2295 { "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
2296 { "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
2297 { "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
2298
2299 { "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
2300 { "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
2301
2302 { "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
2303 { "cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
2304 { "cmp", X(31,0), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
2305
2306 { "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
2307 { "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
2308 { "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
2309 { "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
2310 { "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
2311 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
2312 { "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
2313 { "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
2314 { "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
2315 { "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
2316 { "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
2317 { "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
2318 { "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
2319 { "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
2320 { "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
2321 { "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
2322
2323 { "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2324 { "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
2325 { "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2326 { "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
2327 { "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2328 { "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
2329 { "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2330 { "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
2331
2332 { "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
2333 { "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
2334
2335 { "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2336 { "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2337 { "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2338 { "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2339
2340 { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
2341 { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
2342
2343 { "mfcr", X(31,19), XRARB_MASK, COM, { RT } },
2344 { "mfocrf", X(31,19), X_MASK, PPCVEC, { RT, FXM } },
2345
2346 { "lwarx", X(31,20), X_MASK, PPC, { RT, RA0, RB } },
2347
2348 { "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } },
2349
2350 { "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } },
2351
2352 { "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
2353 { "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
2354
2355 { "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
2356 { "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
2357
2358 { "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
2359 { "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
2360
2361 { "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
2362 { "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
2363
2364 { "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
2365 { "cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
2366 { "cmpl", X(31,32), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
2367
2368 { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
2369 { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
2370 { "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
2371 { "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
2372 { "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
2373 { "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
2374 { "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
2375 { "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
2376
2377 { "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
2378
2379 { "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
2380
2381 { "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
2382
2383 { "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
2384 { "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
2385
2386 { "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
2387 { "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
2388
2389 { "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
2390 { "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
2391 { "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
2392 { "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
2393 { "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
2394 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
2395 { "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
2396 { "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
2397 { "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
2398 { "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
2399 { "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
2400 { "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
2401 { "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
2402 { "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
2403 { "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
2404
2405 { "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
2406 { "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
2407
2408 { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
2409 { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
2410
2411 { "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
2412
2413 { "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
2414
2415 { "ldarx", X(31,84), X_MASK, PPC64, { RT, RA0, RB } },
2416
2417 { "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
2418
2419 { "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
2420
2421 { "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
2422 { "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
2423 { "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
2424 { "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
2425
2426 { "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
2427
2428 { "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
2429
2430 { "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
2431 { "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
2432 { "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
2433 { "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
2434
2435 { "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2436 { "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2437 { "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2438 { "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2439
2440 { "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2441 { "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2442 { "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2443 { "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2444
2445 { "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, COM, { RS }},
2446 { "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
2447 { "mtocrf", X(31,144)|(1<<20),XFXFXM_MASK2, COM, { FXM, RS } },
2448
2449 { "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
2450
2451 { "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } },
2452
2453 { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } },
2454
2455 { "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } },
2456
2457 { "prtyw", X(31,154), XRB_MASK, POWER6, { RA, RS } },
2458
2459 { "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } },
2460
2461 { "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
2462
2463 { "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
2464
2465 { "prtyd", X(31,186), XRB_MASK, POWER6, { RA, RS } },
2466
2467 { "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
2468 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
2469 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
2470 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
2471
2472 { "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
2473 { "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
2474 { "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
2475 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
2476
2477 { "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
2478
2479 { "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } },
2480
2481 { "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } },
2482
2483 { "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
2484 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
2485 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
2486 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
2487
2488 { "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
2489 { "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
2490 { "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
2491 { "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
2492
2493 { "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
2494 { "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
2495 { "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
2496 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
2497
2498 { "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2499 { "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2500 { "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2501 { "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2502
2503 { "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
2504
2505 { "dcbtst", X(31,246), XRT_MASK, PPC, { RA, RB } },
2506
2507 { "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
2508
2509 { "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2510 { "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2511 { "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2512 { "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2513
2514 { "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } },
2515
2516 { "xdcbt", X(31,278)|(1<<25), XRT_MASK, PPC, { RA, RB } },
2517
2518 { "dcbt", X(31,278), XRT_MASK, PPC, { RA, RB } },
2519
2520 { "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } },
2521
2522 { "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
2523 { "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
2524
2525 { "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
2526
2527 { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
2528
2529 { "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
2530
2531 { "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
2532 { "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
2533
2534 { "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
2535 { "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
2536 { "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
2537 { "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
2538 { "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
2539 { "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
2540 { "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
2541 { "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
2542 { "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
2543 { "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
2544 { "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
2545 { "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
2546 { "mfcfar", XSPR(31,339,28), XSPR_MASK, POWER6, { RT } },
2547 { "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
2548 { "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
2549 { "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
2550 { "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
2551 { "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
2552 { "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
2553 { "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
2554 { "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
2555 { "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
2556 { "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2557 { "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2558 { "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2559 { "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2560 { "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
2561 { "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
2562 { "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
2563 { "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
2564 { "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
2565 { "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
2566 { "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
2567 { "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
2568 { "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
2569 { "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
2570 { "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
2571 { "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
2572 { "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
2573 { "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
2574 { "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
2575 { "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
2576 { "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
2577 { "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
2578 { "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
2579 { "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
2580
2581 { "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } },
2582
2583 { "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
2584 { "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
2585
2586 { "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } },
2587
2588 { "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
2589 { "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
2590
2591 { "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
2592
2593 { "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
2594 { "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
2595 { "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
2596
2597 { "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
2598 { "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
2599
2600 { "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
2601
2602 { "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
2603
2604 { "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
2605 { "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
2606
2607 { "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
2608 { "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
2609
2610 { "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
2611
2612 { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
2613
2614 { "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
2615
2616 { "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
2617 { "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
2618 { "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
2619 { "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
2620
2621 { "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
2622 { "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
2623 { "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
2624 { "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
2625
2626 { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
2627 { "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
2628 { "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
2629 { "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
2630
2631 { "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
2632 { "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
2633 { "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
2634 { "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
2635 { "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
2636 { "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
2637 { "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
2638 { "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
2639 { "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
2640 { "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
2641 { "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
2642 { "mtcfar", XSPR(31,467,28), XSPR_MASK, POWER6, { RS } },
2643 { "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RT } },
2644 { "mtsprg", XSPR(31,467,272), XSPRG_MASK,PPC, { SPRG, RS } },
2645 { "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RT } },
2646 { "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RT } },
2647 { "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RT } },
2648 { "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RT } },
2649 { "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
2650 { "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
2651 { "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
2652 { "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
2653 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2654 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2655 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2656 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2657 { "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RT } },
2658 { "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RT } },
2659 { "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RT } },
2660 { "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RT } },
2661 { "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RT } },
2662 { "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RT } },
2663 { "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RT } },
2664 { "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RT } },
2665 { "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RT } },
2666 { "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RT } },
2667 { "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RT } },
2668 { "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RT } },
2669 { "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RT } },
2670 { "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RT } },
2671 { "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RT } },
2672 { "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RT } },
2673 { "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RT } },
2674 { "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RT } },
2675 { "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RT } },
2676 { "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
2677
2678 { "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
2679
2680 { "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
2681 { "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
2682
2683 { "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
2684 { "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
2685 { "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
2686 { "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
2687
2688 { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
2689 { "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
2690 { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
2691 { "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
2692
2693 { "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
2694
2695 { "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
2696
2697 { "cmpb", X(31,508), X_MASK, POWER6, { RA, RS, RB } },
2698
2699 { "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
2700
2701 { "ldbrx", X(31,532), X_MASK, CELL, { RT, RA0, RB } },
2702
2703 { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } },
2704
2705 { "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } },
2706
2707 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } },
2708
2709 { "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
2710 { "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
2711
2712 { "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
2713 { "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
2714
2715 { "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
2716
2717 { "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
2718
2719 { "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
2720
2721 { "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } },
2722
2723 { "lwsync", XSYNC(31,598,1), 0xffffffff, PPCONLY, { 0 } },
2724 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
2725 { "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
2726
2727 { "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } },
2728
2729 { "mffgpr", XRC(31,607,0), XRA_MASK, POWER6, { FRT, RB } },
2730
2731 { "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
2732
2733 { "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
2734
2735 { "stdbrx", X(31,660), X_MASK, CELL, { RS, RA0, RB } },
2736
2737 { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } },
2738
2739 { "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } },
2740
2741 { "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } },
2742
2743 { "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
2744
2745 { "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } },
2746
2747 { "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } },
2748
2749 { "mftgpr", XRC(31,735,0), XRA_MASK, POWER6, { RT, FRB } },
2750
2751 { "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
2752
2753 { "lwzcix", X(31,789), X_MASK, POWER6, { RT, RA0, RB } },
2754
2755 { "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } },
2756
2757 { "lfdpx", X(31,791), X_MASK, POWER6, { FRT, RA, RB } },
2758
2759 { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
2760 { "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
2761
2762 { "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
2763 { "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
2764
2765 { "lhzcix", X(31,821), X_MASK, POWER6, { RT, RA0, RB } },
2766
2767 { "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
2768 { "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } },
2769
2770 { "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
2771 { "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
2772
2773 { "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
2774
2775 { "lbzcix", X(31,853), X_MASK, POWER6, { RT, RA0, RB } },
2776
2777 { "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
2778
2779 { "lfiwax", X(31,855), X_MASK, POWER6, { FRT, RA0, RB } },
2780
2781 { "ldcix", X(31,885), X_MASK, POWER6, { RT, RA0, RB } },
2782
2783 { "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
2784
2785 { "stwcix", X(31,917), X_MASK, POWER6, { RS, RA0, RB } },
2786
2787 { "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } },
2788
2789 { "stfdpx", X(31,919), X_MASK, POWER6, { FRS, RA, RB } },
2790
2791 { "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
2792 { "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
2793
2794 { "sthcix", X(31,949), X_MASK, POWER6, { RS, RA0, RB } },
2795
2796 { "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
2797 { "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
2798
2799 { "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
2800
2801 { "stbcix", X(31,981), X_MASK, POWER6, { RS, RA0, RB } },
2802
2803 { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
2804
2805 { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } },
2806
2807 { "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
2808 { "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
2809
2810 { "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
2811
2812 { "stdcix", X(31,1013), X_MASK, POWER6, { RS, RA0, RB } },
2813
2814 { "dcbzl", XOPL(31,1014,1), XRT_MASK, PPC, { RA, RB } },
2815 { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
2816
2817 { "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA0, RB } },
2818 { "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA0, RB } },
2819 { "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA0, RB } },
2820 { "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA0, RB } },
2821 { "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA0, RB } },
2822 { "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA0, RB } },
2823 { "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA0, RB } },
2824 { "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA0, RB } },
2825 { "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA0, RB } },
2826 { "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA0, RB } },
2827 { "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA0, RB } },
2828 { "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA0, RB } },
2829
2830 { "lvlx", X(31, 519), X_MASK, CELL, { VD, RA0, RB } },
2831 { "lvlxl", X(31, 775), X_MASK, CELL, { VD, RA0, RB } },
2832 { "lvrx", X(31, 551), X_MASK, CELL, { VD, RA0, RB } },
2833 { "lvrxl", X(31, 807), X_MASK, CELL, { VD, RA0, RB } },
2834 { "stvlx", X(31, 647), X_MASK, CELL, { VS, RA0, RB } },
2835 { "stvlxl", X(31, 903), X_MASK, CELL, { VS, RA0, RB } },
2836 { "stvrx", X(31, 679), X_MASK, CELL, { VS, RA0, RB } },
2837 { "stvrxl", X(31, 935), X_MASK, CELL, { VS, RA0, RB } },
2838
2839 { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } },
2840
2841 { "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
2842
2843 { "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } },
2844
2845 { "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
2846
2847 { "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } },
2848
2849 { "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
2850
2851 { "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } },
2852
2853 { "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
2854
2855 { "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } },
2856
2857 { "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
2858
2859 { "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } },
2860
2861 { "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
2862
2863 { "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } },
2864
2865 { "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
2866
2867 { "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
2868
2869 { "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } },
2870
2871 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } },
2872
2873 { "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
2874
2875 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } },
2876
2877 { "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
2878
2879 { "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } },
2880
2881 { "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
2882
2883 { "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } },
2884
2885 { "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
2886
2887 { "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
2888
2889 { "lfdp", OP(57), OP_MASK, POWER6, { FRT, D, RA0 } },
2890
2891 { "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } },
2892
2893 { "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
2894
2895 { "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } },
2896
2897 { "dadd", XRC(59,2,0), X_MASK, POWER6, { FRT, FRA, FRB } },
2898 { "dadd.", XRC(59,2,1), X_MASK, POWER6, { FRT, FRA, FRB } },
2899
2900 { "dqua", ZRC(59,3,0), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
2901 { "dqua.", ZRC(59,3,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
2902
2903 { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2904 { "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2905
2906 { "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2907 { "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2908
2909 { "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2910 { "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2911
2912 { "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
2913 { "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
2914
2915 { "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
2916 { "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
2917
2918 { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2919 { "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2920
2921 { "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2922 { "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2923
2924 { "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2925 { "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2926
2927 { "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2928 { "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2929
2930 { "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2931 { "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2932
2933 { "dmul", XRC(59,34,0), X_MASK, POWER6, { FRT, FRA, FRB } },
2934 { "dmul.", XRC(59,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
2935
2936 { "drrnd", ZRC(59,35,0), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
2937 { "drrnd.", ZRC(59,35,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
2938
2939 { "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
2940 { "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
2941
2942 { "dquai", ZRC(59,67,0), Z_MASK, POWER6, { TE, FRT, FRB, RMC } },
2943 { "dquai.", ZRC(59,67,1), Z_MASK, POWER6, { TE, FRT, FRB, RMC } },
2944
2945 { "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
2946 { "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
2947
2948 { "drintx", ZRC(59,99,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
2949 { "drintx.", ZRC(59,99,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
2950
2951 { "dcmpo", X(59,130), X_MASK, POWER6, { BF, FRA, FRB } },
2952
2953 { "dtstex", X(59,162), X_MASK, POWER6, { BF, FRA, FRB } },
2954 { "dtstdc", Z(59,194), Z_MASK, POWER6, { BF, FRA, DCM } },
2955 { "dtstdg", Z(59,226), Z_MASK, POWER6, { BF, FRA, DGM } },
2956
2957 { "drintn", ZRC(59,227,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
2958 { "drintn.", ZRC(59,227,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
2959
2960 { "dctdp", XRC(59,258,0), X_MASK, POWER6, { FRT, FRB } },
2961 { "dctdp.", XRC(59,258,1), X_MASK, POWER6, { FRT, FRB } },
2962
2963 { "dctfix", XRC(59,290,0), X_MASK, POWER6, { FRT, FRB } },
2964 { "dctfix.", XRC(59,290,1), X_MASK, POWER6, { FRT, FRB } },
2965
2966 { "ddedpd", XRC(59,322,0), X_MASK, POWER6, { SP, FRT, FRB } },
2967 { "ddedpd.", XRC(59,322,1), X_MASK, POWER6, { SP, FRT, FRB } },
2968
2969 { "dxex", XRC(59,354,0), X_MASK, POWER6, { FRT, FRB } },
2970 { "dxex.", XRC(59,354,1), X_MASK, POWER6, { FRT, FRB } },
2971
2972 { "dsub", XRC(59,514,0), X_MASK, POWER6, { FRT, FRA, FRB } },
2973 { "dsub.", XRC(59,514,1), X_MASK, POWER6, { FRT, FRA, FRB } },
2974
2975 { "ddiv", XRC(59,546,0), X_MASK, POWER6, { FRT, FRA, FRB } },
2976 { "ddiv.", XRC(59,546,1), X_MASK, POWER6, { FRT, FRA, FRB } },
2977
2978 { "dcmpu", X(59,642), X_MASK, POWER6, { BF, FRA, FRB } },
2979
2980 { "dtstsf", X(59,674), X_MASK, POWER6, { BF, FRA, FRB } },
2981
2982 { "drsp", XRC(59,770,0), X_MASK, POWER6, { FRT, FRB } },
2983 { "drsp.", XRC(59,770,1), X_MASK, POWER6, { FRT, FRB } },
2984
2985 { "dcffix", XRC(59,802,0), X_MASK, POWER6, { FRT, FRB } },
2986 { "dcffix.", XRC(59,802,1), X_MASK, POWER6, { FRT, FRB } },
2987
2988 { "denbcd", XRC(59,834,0), X_MASK, POWER6, { S, FRT, FRB } },
2989 { "denbcd.", XRC(59,834,1), X_MASK, POWER6, { S, FRT, FRB } },
2990
2991 { "diex", XRC(59,866,0), X_MASK, POWER6, { FRT, FRA, FRB } },
2992 { "diex.", XRC(59,866,1), X_MASK, POWER6, { FRT, FRA, FRB } },
2993
2994 { "stfdp", OP(61), OP_MASK, POWER6, { FRT, D, RA0 } },
2995
2996 { "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } },
2997
2998 { "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
2999
3000 { "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 } },
3001
3002 { "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
3003
3004 { "daddq", XRC(63,2,0), X_MASK, POWER6, { FRT, FRA, FRB } },
3005 { "daddq.", XRC(63,2,1), X_MASK, POWER6, { FRT, FRA, FRB } },
3006
3007 { "dquaq", ZRC(63,3,0), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
3008 { "dquaq.", ZRC(63,3,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
3009
3010 { "fcpsgn", XRC(63,8,0), X_MASK, POWER6, { FRT, FRA, FRB } },
3011 { "fcpsgn.", XRC(63,8,1), X_MASK, POWER6, { FRT, FRA, FRB } },
3012
3013 { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
3014 { "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
3015
3016 { "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
3017 { "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
3018
3019 { "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
3020 { "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
3021
3022 { "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3023 { "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3024
3025 { "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3026 { "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3027
3028 { "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3029 { "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3030
3031 { "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
3032 { "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
3033
3034 { "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3035 { "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3036
3037 { "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
3038 { "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
3039
3040 { "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
3041 { "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
3042
3043 { "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3044 { "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3045
3046 { "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3047 { "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3048
3049 { "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3050 { "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3051
3052 { "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3053 { "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3054
3055 { "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
3056
3057 { "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
3058 { "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
3059
3060 { "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
3061 { "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
3062
3063 { "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
3064
3065 { "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
3066 { "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
3067
3068 { "dquaiq", ZRC(63,67,0), Z_MASK, POWER6, { TE, FRT, FRB, RMC } },
3069 { "dquaiq.", ZRC(63,67,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
3070
3071 { "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
3072 { "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
3073
3074 { "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
3075 { "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
3076
3077 { "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
3078 { "dscriq.", ZRC(63,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
3079
3080 { "drintxq", ZRC(63,99,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
3081 { "drintxq.",ZRC(63,99,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
3082
3083 { "dcmpoq", X(63,130), X_MASK, POWER6, { BF, FRA, FRB } },
3084
3085 { "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
3086 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
3087
3088 { "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
3089 { "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
3090
3091 { "dtstexq", X(63,162), X_MASK, POWER6, { BF, FRA, FRB } },
3092 { "dtstdcq", Z(63,194), Z_MASK, POWER6, { BF, FRA, DCM } },
3093 { "dtstdgq", Z(63,226), Z_MASK, POWER6, { BF, FRA, DGM } },
3094
3095 { "drintnq", ZRC(63,227,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
3096 { "drintnq.",ZRC(63,227,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
3097
3098 { "dctqpq", XRC(63,258,0), X_MASK, POWER6, { FRT, FRB } },
3099 { "dctqpq.", XRC(63,258,1), X_MASK, POWER6, { FRT, FRB } },
3100
3101 { "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
3102 { "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
3103
3104 { "dctfixq", XRC(63,290,0), X_MASK, POWER6, { FRT, FRB } },
3105 { "dctfixq.",XRC(63,290,1), X_MASK, POWER6, { FRT, FRB } },
3106
3107 { "ddedpdq", XRC(63,322,0), X_MASK, POWER6, { SP, FRT, FRB } },
3108 { "ddedpdq.",XRC(63,322,1), X_MASK, POWER6, { SP, FRT, FRB } },
3109
3110 { "dxexq", XRC(63,354,0), X_MASK, POWER6, { FRT, FRB } },
3111 { "dxexq.", XRC(63,354,1), X_MASK, POWER6, { FRT, FRB } },
3112
3113 { "frin", XRC(63,392,0), XRA_MASK, POWER5, { FRT, FRB } },
3114 { "frin.", XRC(63,392,1), XRA_MASK, POWER5, { FRT, FRB } },
3115 { "friz", XRC(63,424,0), XRA_MASK, POWER5, { FRT, FRB } },
3116 { "friz.", XRC(63,424,1), XRA_MASK, POWER5, { FRT, FRB } },
3117 { "frip", XRC(63,456,0), XRA_MASK, POWER5, { FRT, FRB } },
3118 { "frip.", XRC(63,456,1), XRA_MASK, POWER5, { FRT, FRB } },
3119 { "frim", XRC(63,488,0), XRA_MASK, POWER5, { FRT, FRB } },
3120 { "frim.", XRC(63,488,1), XRA_MASK, POWER5, { FRT, FRB } },
3121
3122 { "dsubq", XRC(63,514,0), X_MASK, POWER6, { FRT, FRA, FRB } },
3123 { "dsubq.", XRC(63,514,1), X_MASK, POWER6, { FRT, FRA, FRB } },
3124
3125 { "ddivq", XRC(63,546,0), X_MASK, POWER6, { FRT, FRA, FRB } },
3126 { "ddivq.", XRC(63,546,1), X_MASK, POWER6, { FRT, FRA, FRB } },
3127
3128 { "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
3129 { "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
3130
3131 { "dcmpuq", X(63,642), X_MASK, POWER6, { BF, FRA, FRB } },
3132
3133 { "dtstsfq", X(63,674), X_MASK, POWER6, { BF, FRA, FRB } },
3134
3135 { "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } },
3136 { "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } },
3137
3138 { "drdpq", XRC(63,770,0), X_MASK, POWER6, { FRT, FRB } },
3139 { "drdpq.", XRC(63,770,1), X_MASK, POWER6, { FRT, FRB } },
3140
3141 { "dcffixq", XRC(63,802,0), X_MASK, POWER6, { FRT, FRB } },
3142 { "dcffixq.",XRC(63,802,1), X_MASK, POWER6, { FRT, FRB } },
3143
3144 { "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
3145 { "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
3146
3147 { "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
3148 { "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
3149
3150 { "denbcdq", XRC(63,834,0), X_MASK, POWER6, { S, FRT, FRB } },
3151 { "denbcdq.",XRC(63,834,1), X_MASK, POWER6, { S, FRT, FRB } },
3152
3153 { "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
3154 { "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
3155
3156 { "diexq", XRC(63,866,0), X_MASK, POWER6, { FRT, FRA, FRB } },
3157 { "diexq.", XRC(63,866,1), X_MASK, POWER6, { FRT, FRA, FRB } },
3158
3159 };
3160
3161 const int powerpc_num_opcodes =
3162 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
3163
3164