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Searched refs:SIFIVE_SPI_DELAY1_INTERCS (Results 1 – 25 of 60) sorted by relevance

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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/spi/
H A Dspi-sifive.c64 #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) macro
123 SIFIVE_SPI_DELAY1_INTERCS(1) | in sifive_spi_init()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/spi/
H A Dspi-sifive.c64 #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) macro
123 SIFIVE_SPI_DELAY1_INTERCS(1) | in sifive_spi_init()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/spi/
H A Dspi-sifive.c64 #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) macro
123 SIFIVE_SPI_DELAY1_INTERCS(1) | in sifive_spi_init()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/spi/
H A Dspi-sifive.c65 #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) macro
420 writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0), in sifive_spi_init_hw()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/spi/
H A Dspi-sifive.c65 #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) macro
420 writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0), in sifive_spi_init_hw()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/spi/
H A Dspi-sifive.c65 #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) macro
420 writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0), in sifive_spi_init_hw()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/spi/
H A Dspi-sifive.c65 #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) macro
420 writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0), in sifive_spi_init_hw()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/spi/
H A Dspi-sifive.c65 #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) macro
420 writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0), in sifive_spi_init_hw()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/spi/
H A Dspi-sifive.c65 #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) macro
420 writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0), in sifive_spi_init_hw()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/spi/
H A Dspi-sifive.c65 #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) macro
420 writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0), in sifive_spi_init_hw()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/spi/
H A Dspi-sifive.c65 #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) macro
420 writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0), in sifive_spi_init_hw()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/spi/
H A Dspi-sifive.c65 #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) macro
420 writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0), in sifive_spi_init_hw()
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/spi/
H A Dspi-sifive.c65 #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) macro
420 writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0), in sifive_spi_init_hw()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/spi/
H A Dspi-sifive.c65 #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) macro
420 writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0), in sifive_spi_init_hw()
/dports/sysutils/u-boot-pinebookpro/u-boot-2021.07/drivers/spi/
H A Dspi-sifive.c65 #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) macro
420 writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0), in sifive_spi_init_hw()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/spi/
H A Dspi-sifive.c65 #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) macro
420 writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0), in sifive_spi_init_hw()
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/spi/
H A Dspi-sifive.c65 #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) macro
420 writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0), in sifive_spi_init_hw()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/spi/
H A Dspi-sifive.c65 #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) macro
420 writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0), in sifive_spi_init_hw()
/dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/drivers/spi/
H A Dspi-sifive.c65 #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) macro
420 writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0), in sifive_spi_init_hw()
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/spi/
H A Dspi-sifive.c65 #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) macro
420 writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0), in sifive_spi_init_hw()
/dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/spi/
H A Dspi-sifive.c65 #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) macro
420 writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0), in sifive_spi_init_hw()
/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/spi/
H A Dspi-sifive.c65 #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) macro
420 writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0), in sifive_spi_init_hw()
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/spi/
H A Dspi-sifive.c65 #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) macro
420 writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0), in sifive_spi_init_hw()
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/spi/
H A Dspi-sifive.c65 #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) macro
420 writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0), in sifive_spi_init_hw()
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/spi/
H A Dspi-sifive.c65 #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) macro
420 writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0), in sifive_spi_init_hw()

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