| /dports/devel/tinygo/tinygo-0.14.1/src/machine/ |
| H A D | machine_stm32_spi.go | 63 conf |= stm32.SPI_CR1_SSM | stm32.SPI_CR1_SSI
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| /dports/lang/micropython/micropython-1.17/ports/stm32/boards/LEGO_HUB_NO6/ |
| H A D | hub_display.c | 93 spi->CR1 = SPI_CR1_SSM | SPI_CR1_SSI | 0 << SPI_CR1_BR_Pos | SPI_CR1_MSTR; in hub_display_spi_init()
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| /dports/security/py-ailment/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/ |
| H A D | stm32l1xx_ll_spi.h | 167 #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuratio…
360 MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode); in LL_SPI_SetMode()
374 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); in LL_SPI_GetMode()
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| /dports/security/py-pyvex/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/ |
| H A D | stm32l1xx_ll_spi.h | 167 #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuratio…
360 MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode); in LL_SPI_SetMode()
374 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); in LL_SPI_GetMode()
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| /dports/devel/py-cle/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/ |
| H A D | stm32l1xx_ll_spi.h | 167 #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuratio…
360 MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode); in LL_SPI_SetMode()
374 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); in LL_SPI_GetMode()
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| /dports/security/py-angr/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/ |
| H A D | stm32l1xx_ll_spi.h | 167 #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuratio…
360 MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode); in LL_SPI_SetMode()
374 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); in LL_SPI_GetMode()
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| /dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32G4xx_HAL_Driver/inc/ |
| H A D | stm32g4xx_ll_spi.h | 148 #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuratio…
400 MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode); in LL_SPI_SetMode()
414 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); in LL_SPI_GetMode()
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| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/spi/ |
| H A D | stm32_spi.c | 44 #define SPI_CR1_SSI BIT(12) macro
557 SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX); in stm32_spi_probe()
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| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/spi/ |
| H A D | stm32_spi.c | 44 #define SPI_CR1_SSI BIT(12) macro
557 SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX); in stm32_spi_probe()
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| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/spi/ |
| H A D | stm32_spi.c | 44 #define SPI_CR1_SSI BIT(12) macro
557 SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX); in stm32_spi_probe()
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| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/spi/ |
| H A D | stm32_spi.c | 44 #define SPI_CR1_SSI BIT(12) macro
557 SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX); in stm32_spi_probe()
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| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/spi/ |
| H A D | stm32_spi.c | 44 #define SPI_CR1_SSI BIT(12) macro
557 SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX); in stm32_spi_probe()
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| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/spi/ |
| H A D | stm32_spi.c | 44 #define SPI_CR1_SSI BIT(12) macro
557 SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX); in stm32_spi_probe()
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| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/spi/ |
| H A D | stm32_spi.c | 44 #define SPI_CR1_SSI BIT(12) macro
557 SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX); in stm32_spi_probe()
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| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/spi/ |
| H A D | stm32_spi.c | 44 #define SPI_CR1_SSI BIT(12) macro
557 SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX); in stm32_spi_probe()
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| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/spi/ |
| H A D | stm32_spi.c | 44 #define SPI_CR1_SSI BIT(12) macro
557 SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX); in stm32_spi_probe()
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| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/spi/ |
| H A D | stm32_spi.c | 44 #define SPI_CR1_SSI BIT(12) macro
557 SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX); in stm32_spi_probe()
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| /dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/drivers/spi/ |
| H A D | stm32_spi.c | 44 #define SPI_CR1_SSI BIT(12) macro
557 SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX); in stm32_spi_probe()
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| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/spi/ |
| H A D | stm32_spi.c | 44 #define SPI_CR1_SSI BIT(12) macro
557 SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX); in stm32_spi_probe()
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| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/spi/ |
| H A D | stm32_spi.c | 44 #define SPI_CR1_SSI BIT(12) macro
557 SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX); in stm32_spi_probe()
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| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/spi/ |
| H A D | stm32_spi.c | 44 #define SPI_CR1_SSI BIT(12) macro
557 SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX); in stm32_spi_probe()
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| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/spi/ |
| H A D | stm32_spi.c | 44 #define SPI_CR1_SSI BIT(12) macro
557 SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX); in stm32_spi_probe()
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| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/spi/ |
| H A D | stm32_spi.c | 44 #define SPI_CR1_SSI BIT(12) macro
557 SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX); in stm32_spi_probe()
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| /dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/spi/ |
| H A D | stm32_spi.c | 44 #define SPI_CR1_SSI BIT(12) macro
557 SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX); in stm32_spi_probe()
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| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/spi/ |
| H A D | stm32_spi.c | 44 #define SPI_CR1_SSI BIT(12) macro
557 SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX); in stm32_spi_probe()
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