/dports/graphics/mesa-dri-classic/mesa-20.2.3/src/panfrost/midgard/ |
H A D | midgard_ra.c | 691 ins->src[0] = SSA_FIXED_REGISTER(src1.reg); in install_registers_instr() 693 ins->src[1] = SSA_FIXED_REGISTER(src2.reg); in install_registers_instr() 695 ins->dest = SSA_FIXED_REGISTER(dest.reg); in install_registers_instr() 710 ins->src[0] = SSA_FIXED_REGISTER(src.reg); in install_registers_instr() 715 ins->dest = SSA_FIXED_REGISTER(dst.reg); in install_registers_instr() 729 ins->src[1] = SSA_FIXED_REGISTER(src.reg); in install_registers_instr() 737 ins->src[2] = SSA_FIXED_REGISTER(src.reg); in install_registers_instr() 756 ins->src[1] = SSA_FIXED_REGISTER(coord.reg); in install_registers_instr() 761 ins->dest = SSA_FIXED_REGISTER(dest.reg); in install_registers_instr() 770 ins->src[2] = SSA_FIXED_REGISTER(lod.reg); in install_registers_instr() [all …]
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H A D | helpers.h | 158 #define SSA_FIXED_REGISTER(reg) (((1 + (reg)) << SSA_FIXED_SHIFT) | 1) macro 160 #define SSA_FIXED_MINIMUM SSA_FIXED_REGISTER(0)
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H A D | midgard_schedule.c | 452 unsigned r_constant = SSA_FIXED_REGISTER(REGISTER_CONSTANT); in mir_adjust_constants() 463 if (ins->src[src] != SSA_FIXED_REGISTER(REGISTER_CONSTANT)) in mir_adjust_constants() 923 cond->dest = SSA_FIXED_REGISTER(31); in mir_schedule_condition() 1034 unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(1) : branch->src[idx]; in mir_schedule_zs_write() 1164 vadd->src[0] = SSA_FIXED_REGISTER(31); in mir_schedule_alu() 1173 vadd->src[1] = SSA_FIXED_REGISTER(1); in mir_schedule_alu() 1231 unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : branch->src[0]; in mir_schedule_alu() 1273 … unsigned temp = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : make_compiler_temp(ctx); in mir_schedule_alu()
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/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/panfrost/midgard/ |
H A D | midgard_ra.c | 721 ins->src[0] = SSA_FIXED_REGISTER(src1.reg); in install_registers_instr() 723 ins->src[1] = SSA_FIXED_REGISTER(src2.reg); in install_registers_instr() 725 ins->dest = SSA_FIXED_REGISTER(dest.reg); in install_registers_instr() 740 ins->src[0] = SSA_FIXED_REGISTER(src.reg); in install_registers_instr() 745 ins->dest = SSA_FIXED_REGISTER(dst.reg); in install_registers_instr() 778 ins->src[1] = SSA_FIXED_REGISTER(coord.reg); in install_registers_instr() 783 ins->dest = SSA_FIXED_REGISTER(dest.reg); in install_registers_instr() 792 ins->src[2] = SSA_FIXED_REGISTER(lod.reg); in install_registers_instr() 798 ins->src[3] = SSA_FIXED_REGISTER(offset.reg); in install_registers_instr() 1029 unsigned min_demote = SSA_FIXED_REGISTER(old_work_count); in mir_demote_uniforms() [all …]
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H A D | midgard_schedule.c | 477 unsigned r_constant = SSA_FIXED_REGISTER(REGISTER_CONSTANT); in mir_adjust_constants() 488 if (ins->src[src] != SSA_FIXED_REGISTER(REGISTER_CONSTANT)) in mir_adjust_constants() 987 cond->dest = SSA_FIXED_REGISTER(31); in mir_schedule_condition() 1103 unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(1) : branch->src[idx]; in mir_schedule_zs_write() 1233 vadd->src[0] = SSA_FIXED_REGISTER(31); in mir_schedule_alu() 1242 vadd->src[1] = SSA_FIXED_REGISTER(1); in mir_schedule_alu() 1300 unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : branch->src[0]; in mir_schedule_alu() 1342 … unsigned temp = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : make_compiler_temp(ctx); in mir_schedule_alu()
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H A D | helpers.h | 197 #define SSA_FIXED_REGISTER(reg) (((1 + (reg)) << SSA_FIXED_SHIFT) | 1) macro 199 #define SSA_FIXED_MINIMUM SSA_FIXED_REGISTER(0)
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/dports/graphics/libosmesa/mesa-21.3.6/src/panfrost/midgard/ |
H A D | midgard_ra.c | 721 ins->src[0] = SSA_FIXED_REGISTER(src1.reg); in install_registers_instr() 723 ins->src[1] = SSA_FIXED_REGISTER(src2.reg); in install_registers_instr() 725 ins->dest = SSA_FIXED_REGISTER(dest.reg); in install_registers_instr() 740 ins->src[0] = SSA_FIXED_REGISTER(src.reg); in install_registers_instr() 745 ins->dest = SSA_FIXED_REGISTER(dst.reg); in install_registers_instr() 778 ins->src[1] = SSA_FIXED_REGISTER(coord.reg); in install_registers_instr() 783 ins->dest = SSA_FIXED_REGISTER(dest.reg); in install_registers_instr() 792 ins->src[2] = SSA_FIXED_REGISTER(lod.reg); in install_registers_instr() 798 ins->src[3] = SSA_FIXED_REGISTER(offset.reg); in install_registers_instr() 1029 unsigned min_demote = SSA_FIXED_REGISTER(old_work_count); in mir_demote_uniforms() [all …]
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H A D | midgard_schedule.c | 477 unsigned r_constant = SSA_FIXED_REGISTER(REGISTER_CONSTANT); in mir_adjust_constants() 488 if (ins->src[src] != SSA_FIXED_REGISTER(REGISTER_CONSTANT)) in mir_adjust_constants() 987 cond->dest = SSA_FIXED_REGISTER(31); in mir_schedule_condition() 1103 unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(1) : branch->src[idx]; in mir_schedule_zs_write() 1233 vadd->src[0] = SSA_FIXED_REGISTER(31); in mir_schedule_alu() 1242 vadd->src[1] = SSA_FIXED_REGISTER(1); in mir_schedule_alu() 1300 unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : branch->src[0]; in mir_schedule_alu() 1342 … unsigned temp = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : make_compiler_temp(ctx); in mir_schedule_alu()
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H A D | helpers.h | 197 #define SSA_FIXED_REGISTER(reg) (((1 + (reg)) << SSA_FIXED_SHIFT) | 1) macro 199 #define SSA_FIXED_MINIMUM SSA_FIXED_REGISTER(0)
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/dports/graphics/mesa-libs/mesa-21.3.6/src/panfrost/midgard/ |
H A D | midgard_ra.c | 721 ins->src[0] = SSA_FIXED_REGISTER(src1.reg); in install_registers_instr() 723 ins->src[1] = SSA_FIXED_REGISTER(src2.reg); in install_registers_instr() 725 ins->dest = SSA_FIXED_REGISTER(dest.reg); in install_registers_instr() 740 ins->src[0] = SSA_FIXED_REGISTER(src.reg); in install_registers_instr() 745 ins->dest = SSA_FIXED_REGISTER(dst.reg); in install_registers_instr() 778 ins->src[1] = SSA_FIXED_REGISTER(coord.reg); in install_registers_instr() 783 ins->dest = SSA_FIXED_REGISTER(dest.reg); in install_registers_instr() 792 ins->src[2] = SSA_FIXED_REGISTER(lod.reg); in install_registers_instr() 798 ins->src[3] = SSA_FIXED_REGISTER(offset.reg); in install_registers_instr() 1029 unsigned min_demote = SSA_FIXED_REGISTER(old_work_count); in mir_demote_uniforms() [all …]
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H A D | midgard_schedule.c | 477 unsigned r_constant = SSA_FIXED_REGISTER(REGISTER_CONSTANT); in mir_adjust_constants() 488 if (ins->src[src] != SSA_FIXED_REGISTER(REGISTER_CONSTANT)) in mir_adjust_constants() 987 cond->dest = SSA_FIXED_REGISTER(31); in mir_schedule_condition() 1103 unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(1) : branch->src[idx]; in mir_schedule_zs_write() 1233 vadd->src[0] = SSA_FIXED_REGISTER(31); in mir_schedule_alu() 1242 vadd->src[1] = SSA_FIXED_REGISTER(1); in mir_schedule_alu() 1300 unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : branch->src[0]; in mir_schedule_alu() 1342 … unsigned temp = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : make_compiler_temp(ctx); in mir_schedule_alu()
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/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/panfrost/midgard/ |
H A D | midgard_ra.c | 721 ins->src[0] = SSA_FIXED_REGISTER(src1.reg); in install_registers_instr() 723 ins->src[1] = SSA_FIXED_REGISTER(src2.reg); in install_registers_instr() 725 ins->dest = SSA_FIXED_REGISTER(dest.reg); in install_registers_instr() 740 ins->src[0] = SSA_FIXED_REGISTER(src.reg); in install_registers_instr() 745 ins->dest = SSA_FIXED_REGISTER(dst.reg); in install_registers_instr() 778 ins->src[1] = SSA_FIXED_REGISTER(coord.reg); in install_registers_instr() 783 ins->dest = SSA_FIXED_REGISTER(dest.reg); in install_registers_instr() 792 ins->src[2] = SSA_FIXED_REGISTER(lod.reg); in install_registers_instr() 798 ins->src[3] = SSA_FIXED_REGISTER(offset.reg); in install_registers_instr() 1029 unsigned min_demote = SSA_FIXED_REGISTER(old_work_count); in mir_demote_uniforms() [all …]
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H A D | midgard_schedule.c | 477 unsigned r_constant = SSA_FIXED_REGISTER(REGISTER_CONSTANT); in mir_adjust_constants() 488 if (ins->src[src] != SSA_FIXED_REGISTER(REGISTER_CONSTANT)) in mir_adjust_constants() 987 cond->dest = SSA_FIXED_REGISTER(31); in mir_schedule_condition() 1103 unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(1) : branch->src[idx]; in mir_schedule_zs_write() 1233 vadd->src[0] = SSA_FIXED_REGISTER(31); in mir_schedule_alu() 1242 vadd->src[1] = SSA_FIXED_REGISTER(1); in mir_schedule_alu() 1300 unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : branch->src[0]; in mir_schedule_alu() 1342 … unsigned temp = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : make_compiler_temp(ctx); in mir_schedule_alu()
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/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/panfrost/midgard/ |
H A D | midgard_ra.c | 721 ins->src[0] = SSA_FIXED_REGISTER(src1.reg); in install_registers_instr() 723 ins->src[1] = SSA_FIXED_REGISTER(src2.reg); in install_registers_instr() 725 ins->dest = SSA_FIXED_REGISTER(dest.reg); in install_registers_instr() 740 ins->src[0] = SSA_FIXED_REGISTER(src.reg); in install_registers_instr() 745 ins->dest = SSA_FIXED_REGISTER(dst.reg); in install_registers_instr() 778 ins->src[1] = SSA_FIXED_REGISTER(coord.reg); in install_registers_instr() 783 ins->dest = SSA_FIXED_REGISTER(dest.reg); in install_registers_instr() 792 ins->src[2] = SSA_FIXED_REGISTER(lod.reg); in install_registers_instr() 798 ins->src[3] = SSA_FIXED_REGISTER(offset.reg); in install_registers_instr() 1029 unsigned min_demote = SSA_FIXED_REGISTER(old_work_count); in mir_demote_uniforms() [all …]
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H A D | midgard_schedule.c | 477 unsigned r_constant = SSA_FIXED_REGISTER(REGISTER_CONSTANT); in mir_adjust_constants() 488 if (ins->src[src] != SSA_FIXED_REGISTER(REGISTER_CONSTANT)) in mir_adjust_constants() 987 cond->dest = SSA_FIXED_REGISTER(31); in mir_schedule_condition() 1103 unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(1) : branch->src[idx]; in mir_schedule_zs_write() 1233 vadd->src[0] = SSA_FIXED_REGISTER(31); in mir_schedule_alu() 1242 vadd->src[1] = SSA_FIXED_REGISTER(1); in mir_schedule_alu() 1300 unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : branch->src[0]; in mir_schedule_alu() 1342 … unsigned temp = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : make_compiler_temp(ctx); in mir_schedule_alu()
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/dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/panfrost/midgard/ |
H A D | midgard_ra.c | 721 ins->src[0] = SSA_FIXED_REGISTER(src1.reg); in install_registers_instr() 723 ins->src[1] = SSA_FIXED_REGISTER(src2.reg); in install_registers_instr() 725 ins->dest = SSA_FIXED_REGISTER(dest.reg); in install_registers_instr() 740 ins->src[0] = SSA_FIXED_REGISTER(src.reg); in install_registers_instr() 745 ins->dest = SSA_FIXED_REGISTER(dst.reg); in install_registers_instr() 778 ins->src[1] = SSA_FIXED_REGISTER(coord.reg); in install_registers_instr() 783 ins->dest = SSA_FIXED_REGISTER(dest.reg); in install_registers_instr() 792 ins->src[2] = SSA_FIXED_REGISTER(lod.reg); in install_registers_instr() 798 ins->src[3] = SSA_FIXED_REGISTER(offset.reg); in install_registers_instr() 1029 unsigned min_demote = SSA_FIXED_REGISTER(old_work_count); in mir_demote_uniforms() [all …]
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H A D | midgard_schedule.c | 477 unsigned r_constant = SSA_FIXED_REGISTER(REGISTER_CONSTANT); in mir_adjust_constants() 488 if (ins->src[src] != SSA_FIXED_REGISTER(REGISTER_CONSTANT)) in mir_adjust_constants() 987 cond->dest = SSA_FIXED_REGISTER(31); in mir_schedule_condition() 1103 unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(1) : branch->src[idx]; in mir_schedule_zs_write() 1233 vadd->src[0] = SSA_FIXED_REGISTER(31); in mir_schedule_alu() 1242 vadd->src[1] = SSA_FIXED_REGISTER(1); in mir_schedule_alu() 1300 unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : branch->src[0]; in mir_schedule_alu() 1342 … unsigned temp = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : make_compiler_temp(ctx); in mir_schedule_alu()
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/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/panfrost/midgard/ |
H A D | midgard_ra.c | 721 ins->src[0] = SSA_FIXED_REGISTER(src1.reg); in install_registers_instr() 723 ins->src[1] = SSA_FIXED_REGISTER(src2.reg); in install_registers_instr() 725 ins->dest = SSA_FIXED_REGISTER(dest.reg); in install_registers_instr() 740 ins->src[0] = SSA_FIXED_REGISTER(src.reg); in install_registers_instr() 745 ins->dest = SSA_FIXED_REGISTER(dst.reg); in install_registers_instr() 778 ins->src[1] = SSA_FIXED_REGISTER(coord.reg); in install_registers_instr() 783 ins->dest = SSA_FIXED_REGISTER(dest.reg); in install_registers_instr() 792 ins->src[2] = SSA_FIXED_REGISTER(lod.reg); in install_registers_instr() 798 ins->src[3] = SSA_FIXED_REGISTER(offset.reg); in install_registers_instr() 1029 unsigned min_demote = SSA_FIXED_REGISTER(old_work_count); in mir_demote_uniforms() [all …]
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H A D | midgard_schedule.c | 477 unsigned r_constant = SSA_FIXED_REGISTER(REGISTER_CONSTANT); in mir_adjust_constants() 488 if (ins->src[src] != SSA_FIXED_REGISTER(REGISTER_CONSTANT)) in mir_adjust_constants() 987 cond->dest = SSA_FIXED_REGISTER(31); in mir_schedule_condition() 1103 unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(1) : branch->src[idx]; in mir_schedule_zs_write() 1233 vadd->src[0] = SSA_FIXED_REGISTER(31); in mir_schedule_alu() 1242 vadd->src[1] = SSA_FIXED_REGISTER(1); in mir_schedule_alu() 1300 unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : branch->src[0]; in mir_schedule_alu() 1342 … unsigned temp = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : make_compiler_temp(ctx); in mir_schedule_alu()
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/dports/graphics/mesa-dri/mesa-21.3.6/src/panfrost/midgard/ |
H A D | midgard_ra.c | 721 ins->src[0] = SSA_FIXED_REGISTER(src1.reg); in install_registers_instr() 723 ins->src[1] = SSA_FIXED_REGISTER(src2.reg); in install_registers_instr() 725 ins->dest = SSA_FIXED_REGISTER(dest.reg); in install_registers_instr() 740 ins->src[0] = SSA_FIXED_REGISTER(src.reg); in install_registers_instr() 745 ins->dest = SSA_FIXED_REGISTER(dst.reg); in install_registers_instr() 778 ins->src[1] = SSA_FIXED_REGISTER(coord.reg); in install_registers_instr() 783 ins->dest = SSA_FIXED_REGISTER(dest.reg); in install_registers_instr() 792 ins->src[2] = SSA_FIXED_REGISTER(lod.reg); in install_registers_instr() 798 ins->src[3] = SSA_FIXED_REGISTER(offset.reg); in install_registers_instr() 1029 unsigned min_demote = SSA_FIXED_REGISTER(old_work_count); in mir_demote_uniforms() [all …]
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H A D | midgard_schedule.c | 477 unsigned r_constant = SSA_FIXED_REGISTER(REGISTER_CONSTANT); in mir_adjust_constants() 488 if (ins->src[src] != SSA_FIXED_REGISTER(REGISTER_CONSTANT)) in mir_adjust_constants() 987 cond->dest = SSA_FIXED_REGISTER(31); in mir_schedule_condition() 1103 unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(1) : branch->src[idx]; in mir_schedule_zs_write() 1233 vadd->src[0] = SSA_FIXED_REGISTER(31); in mir_schedule_alu() 1242 vadd->src[1] = SSA_FIXED_REGISTER(1); in mir_schedule_alu() 1300 unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : branch->src[0]; in mir_schedule_alu() 1342 … unsigned temp = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : make_compiler_temp(ctx); in mir_schedule_alu()
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/dports/lang/clover/mesa-21.3.6/src/panfrost/midgard/ |
H A D | midgard_ra.c | 721 ins->src[0] = SSA_FIXED_REGISTER(src1.reg); in install_registers_instr() 723 ins->src[1] = SSA_FIXED_REGISTER(src2.reg); in install_registers_instr() 725 ins->dest = SSA_FIXED_REGISTER(dest.reg); in install_registers_instr() 740 ins->src[0] = SSA_FIXED_REGISTER(src.reg); in install_registers_instr() 745 ins->dest = SSA_FIXED_REGISTER(dst.reg); in install_registers_instr() 778 ins->src[1] = SSA_FIXED_REGISTER(coord.reg); in install_registers_instr() 783 ins->dest = SSA_FIXED_REGISTER(dest.reg); in install_registers_instr() 792 ins->src[2] = SSA_FIXED_REGISTER(lod.reg); in install_registers_instr() 798 ins->src[3] = SSA_FIXED_REGISTER(offset.reg); in install_registers_instr() 1029 unsigned min_demote = SSA_FIXED_REGISTER(old_work_count); in mir_demote_uniforms() [all …]
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H A D | midgard_schedule.c | 477 unsigned r_constant = SSA_FIXED_REGISTER(REGISTER_CONSTANT); in mir_adjust_constants() 488 if (ins->src[src] != SSA_FIXED_REGISTER(REGISTER_CONSTANT)) in mir_adjust_constants() 987 cond->dest = SSA_FIXED_REGISTER(31); in mir_schedule_condition() 1103 unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(1) : branch->src[idx]; in mir_schedule_zs_write() 1233 vadd->src[0] = SSA_FIXED_REGISTER(31); in mir_schedule_alu() 1242 vadd->src[1] = SSA_FIXED_REGISTER(1); in mir_schedule_alu() 1300 unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : branch->src[0]; in mir_schedule_alu() 1342 … unsigned temp = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : make_compiler_temp(ctx); in mir_schedule_alu()
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/dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/panfrost/midgard/ |
H A D | midgard_ra.c | 759 ins->src[0] = SSA_FIXED_REGISTER(src1.reg); in install_registers_instr() 761 ins->src[1] = SSA_FIXED_REGISTER(src2.reg); in install_registers_instr() 763 ins->dest = SSA_FIXED_REGISTER(dest.reg); in install_registers_instr() 778 ins->src[0] = SSA_FIXED_REGISTER(src.reg); in install_registers_instr() 783 ins->dest = SSA_FIXED_REGISTER(dst.reg); in install_registers_instr() 816 ins->src[1] = SSA_FIXED_REGISTER(coord.reg); in install_registers_instr() 821 ins->dest = SSA_FIXED_REGISTER(dest.reg); in install_registers_instr() 830 ins->src[2] = SSA_FIXED_REGISTER(lod.reg); in install_registers_instr() 836 ins->src[3] = SSA_FIXED_REGISTER(offset.reg); in install_registers_instr() 1067 unsigned min_demote = SSA_FIXED_REGISTER(old_work_count); in mir_demote_uniforms() [all …]
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H A D | midgard_schedule.c | 477 unsigned r_constant = SSA_FIXED_REGISTER(REGISTER_CONSTANT); in mir_adjust_constants() 488 if (ins->src[src] != SSA_FIXED_REGISTER(REGISTER_CONSTANT)) in mir_adjust_constants() 987 cond->dest = SSA_FIXED_REGISTER(31); in mir_schedule_condition() 1103 unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(1) : branch->src[idx]; in mir_schedule_zs_write() 1233 vadd->src[0] = SSA_FIXED_REGISTER(31); in mir_schedule_alu() 1242 vadd->src[1] = SSA_FIXED_REGISTER(1); in mir_schedule_alu() 1300 unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : branch->src[0]; in mir_schedule_alu() 1342 … unsigned temp = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : make_compiler_temp(ctx); in mir_schedule_alu()
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