Searched refs:Set_Is_Ref (Results 1 – 13 of 13) sorted by relevance
/dports/cad/ghdl/ghdl-1.0.0/src/vhdl/ |
H A D | vhdl-canon.adb | 1287 Set_Is_Ref (Proc, True); 1329 Set_Is_Ref (If_Stmt, True); 1430 Set_Is_Ref (Proc, True); 1436 Set_Is_Ref (Wait_Stmt, True); 1474 Set_Is_Ref (Stmt, True); 1844 Set_Is_Ref (Proc, True); 1916 Set_Is_Ref (Proc, True); 2392 Set_Is_Ref (Cfg, True); 2773 Set_Is_Ref (Dis, True); 2823 Set_Is_Ref (Limit, True); [all …]
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H A D | vhdl-sem_types.adb | 1480 Set_Is_Ref (Res, True); 1487 Set_Is_Ref (Res, True); 1518 Set_Is_Ref (Res, True); 1564 Set_Is_Ref (Res, True); 1875 Set_Is_Ref (Res, True); 1975 Set_Is_Ref (Res, True); 2224 Set_Is_Ref (Res, True); 2230 Set_Is_Ref (Res, True);
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H A D | vhdl-configuration.adb | 1224 Set_Is_Ref (Gen, False); 1228 Set_Is_Ref (Get_Chain (Gen), False);
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H A D | vhdl-sem_inst.adb | 720 Set_Is_Ref (Res, True);
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H A D | vhdl-sem_decls.adb | 953 Set_Is_Ref (Decl, True);
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H A D | vhdl-sem_assocs.adb | 1069 Set_Is_Ref (Ntype, True);
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H A D | vhdl-nodes.ads | 9179 procedure Set_Is_Ref (N : Iir; Ref : Boolean); subprogspec
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H A D | vhdl-parse.adb | 1788 Set_Is_Ref (Inter, Inter /= First); 1900 Set_Is_Ref (Inter, Inter /= First);
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H A D | vhdl-sem_names.adb | 824 Set_Is_Ref (Slice_Type, True);
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H A D | vhdl-nodes.adb | 7125 procedure Set_Is_Ref (N : Iir; Ref : Boolean) is subprogram 7131 end Set_Is_Ref;
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H A D | vhdl-sem_expr.adb | 3853 Set_Is_Ref (Info.Index_Subtype, True);
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H A D | vhdl-nodes_meta.adb | 5853 Set_Is_Ref (N, V);
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/dports/cad/ghdl/ghdl-1.0.0/pyGHDL/libghdl/vhdl/ |
H A D | nodes.py | 2804 Set_Is_Ref = libghdl.vhdl__nodes__set_is_ref variable
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