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Searched refs:TCCR1D (Results 1 – 25 of 59) sorted by relevance

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/dports/devel/asl/asl-current/include/avr/
H A Dregtnx61.inc200 TCCR1D port 0x26 ; Timer/Counter 1 Control Register D
201 WGM10 avrbit TCCR1D,0 ; Timer/Counter 1 Waveform Generation Mode
202 WGM11 avrbit TCCR1D,1
203 FPF1 avrbit TCCR1D,2 ; Fault Protection Interrupt Flag
204 FPAC1 avrbit TCCR1D,3 ; Fault Protection Analog Comparator Enable
205 FPES1 avrbit TCCR1D,4 ; Fault Protection Edge Select
206 FPNC1 avrbit TCCR1D,5 ; Fault Protection Noise Canceler
207 FPEN1 avrbit TCCR1D,6 ; Fault Protection Mode Enable
208 FPIE1 avrbit TCCR1D,7 ; Fault Protection Interrupt Enable
H A Dregtnx7.inc201 TCCR1D sfr 0x83 ; Timer/Counter 1 Control Register D
202 OC1AU avrbit TCCR1D,0 ; Output Compare Pin Enable for Channel A
203 OC1AV avrbit TCCR1D,1
204 OC1AW avrbit TCCR1D,2
205 OC1AX avrbit TCCR1D,3
206 OC1BU avrbit TCCR1D,4 ; Output Compare Pin Enable for Channel B
207 OC1BV avrbit TCCR1D,5
208 OC1BW avrbit TCCR1D,6
209 OC1BX avrbit TCCR1D,7
/dports/devel/avr-libc/avr-libc-2.0.0/include/avr/
H A Diotnx61.h303 #define TCCR1D _SFR_IO8(0x26) macro
/dports/editors/fpc-ide/fpc-3.2.2/rtl/embedded/avr/
H A Dattiny461.pp55 TCCR1D : byte absolute $00+$46; // Timer/Counter Control Register D
197 // TCCR1D
H A Dattiny461a.pp55 TCCR1D : byte absolute $00+$46; // Timer/Counter Control Register D
197 // TCCR1D
H A Dattiny861.pp55 TCCR1D : byte absolute $00+$46; // Timer/Counter Control Register D
197 // TCCR1D
H A Dattiny861a.pp55 TCCR1D : byte absolute $00+$46; // Timer/Counter Control Register D
197 // TCCR1D
H A Dattiny261.pp55 TCCR1D : byte absolute $00+$46; // Timer/Counter Control Register D
195 // TCCR1D
H A Dattiny261a.pp55 TCCR1D : byte absolute $00+$46; // Timer/Counter Control Register D
195 // TCCR1D
/dports/lang/fpc-source/fpc-3.2.2/rtl/embedded/avr/
H A Dattiny861a.pp55 TCCR1D : byte absolute $00+$46; // Timer/Counter Control Register D
197 // TCCR1D
H A Dattiny261.pp55 TCCR1D : byte absolute $00+$46; // Timer/Counter Control Register D
195 // TCCR1D
H A Dattiny261a.pp55 TCCR1D : byte absolute $00+$46; // Timer/Counter Control Register D
195 // TCCR1D
H A Dattiny461.pp55 TCCR1D : byte absolute $00+$46; // Timer/Counter Control Register D
197 // TCCR1D
H A Dattiny461a.pp55 TCCR1D : byte absolute $00+$46; // Timer/Counter Control Register D
197 // TCCR1D
H A Dattiny861.pp55 TCCR1D : byte absolute $00+$46; // Timer/Counter Control Register D
197 // TCCR1D
/dports/lang/fpc/fpc-3.2.2/rtl/embedded/avr/
H A Dattiny461a.pp55 TCCR1D : byte absolute $00+$46; // Timer/Counter Control Register D
197 // TCCR1D
H A Dattiny261.pp55 TCCR1D : byte absolute $00+$46; // Timer/Counter Control Register D
195 // TCCR1D
H A Dattiny261a.pp55 TCCR1D : byte absolute $00+$46; // Timer/Counter Control Register D
195 // TCCR1D
H A Dattiny461.pp55 TCCR1D : byte absolute $00+$46; // Timer/Counter Control Register D
197 // TCCR1D
H A Dattiny861.pp55 TCCR1D : byte absolute $00+$46; // Timer/Counter Control Register D
197 // TCCR1D
H A Dattiny861a.pp55 TCCR1D : byte absolute $00+$46; // Timer/Counter Control Register D
197 // TCCR1D
/dports/lang/fpc-utils/fpc-3.2.2/rtl/embedded/avr/
H A Dattiny261a.pp55 TCCR1D : byte absolute $00+$46; // Timer/Counter Control Register D
195 // TCCR1D
H A Dattiny261.pp55 TCCR1D : byte absolute $00+$46; // Timer/Counter Control Register D
195 // TCCR1D
H A Dattiny461.pp55 TCCR1D : byte absolute $00+$46; // Timer/Counter Control Register D
197 // TCCR1D
H A Dattiny461a.pp55 TCCR1D : byte absolute $00+$46; // Timer/Counter Control Register D
197 // TCCR1D

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