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Searched refs:TIM_CCMR1_OC1M (Results 1 – 25 of 44) sorted by relevance

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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/STM32F37x_StdPeriph_Driver/src/
H A Dstm32f37x_tim.c786 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M)); in TIM_OC1Init()
1074 *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M); in TIM_SelectOCxM()
1170 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M); in TIM_ForcedOC1Config()
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32F37x_StdPeriph_Driver/src/
H A Dstm32f37x_tim.c786 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M)); in TIM_OC1Init()
1074 *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M); in TIM_SelectOCxM()
1170 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M); in TIM_ForcedOC1Config()
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32F0xx_StdPeriph_Driver/src/
H A Dstm32f0xx_tim.c795 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M)); in TIM_OC1Init()
1153 *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M); in TIM_SelectOCxM()
1251 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M); in TIM_ForcedOC1Config()
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32H7xx_HAL_Driver/inc/
H A Dstm32h7xx_ll_tim.h691 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) …
1896 …MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT… in LL_TIM_OC_SetMode()
1935 …return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT… in LL_TIM_OC_GetMode()
H A Dstm32h7xx_hal_tim.h962 #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M …
/dports/security/py-pyvex/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_ll_tim.h1370 …MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT… in LL_TIM_OC_SetMode()
1399 …return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT… in LL_TIM_OC_GetMode()
H A Dstm32l1xx_hal_tim.h339 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
/dports/devel/py-cle/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_ll_tim.h1370 …MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT… in LL_TIM_OC_SetMode()
1399 …return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT… in LL_TIM_OC_GetMode()
H A Dstm32l1xx_hal_tim.h339 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
/dports/security/py-angr/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_ll_tim.h1370 …MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT… in LL_TIM_OC_SetMode()
1399 …return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT… in LL_TIM_OC_GetMode()
H A Dstm32l1xx_hal_tim.h339 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
/dports/security/py-ailment/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_ll_tim.h1370 …MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT… in LL_TIM_OC_SetMode()
1399 …return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT… in LL_TIM_OC_GetMode()
H A Dstm32l1xx_hal_tim.h339 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32F4xx_StdPeriph_Driver/src/
H A Dstm32f4xx_tim.c695 tmpccmrx &= (uint16_t)~TIM_CCMR1_OC1M; in TIM_OC1Init()
1134 tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1M; in TIM_ForcedOC1Config()
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/STM32F4xx_StdPeriph_Driver/src/
H A Dstm32f4xx_tim.c695 tmpccmrx &= (uint16_t)~TIM_CCMR1_OC1M; in TIM_OC1Init()
1134 tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1M; in TIM_ForcedOC1Config()
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32G4xx_HAL_Driver/inc/
H A Dstm32g4xx_ll_tim.h718 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) …
2658 …MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT… in LL_TIM_OC_SetMode()
2699 …return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT… in LL_TIM_OC_GetMode()
H A Dstm32g4xx_hal_tim.h1075 #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M …
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/STM32F30x_StdPeriph_Driver/src/
H A Dstm32f30x_tim.c703 tmpccmrx &= (uint32_t)~TIM_CCMR1_OC1M; in TIM_OC1Init()
1384 tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC1M; in TIM_ForcedOC1Config()
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32H7xx_HAL_Driver/src/
H A Dstm32h7xx_ll_tim.c841 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode); in OC1Config()
H A Dstm32h7xx_hal_tim.c6137 tmpccmrx &= ~TIM_CCMR1_OC1M; in TIM_OC1_SetConfig()
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32G4xx_HAL_Driver/src/
H A Dstm32g4xx_ll_tim.c829 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode); in OC1Config()
H A Dstm32g4xx_hal_tim.c6857 tmpccmrx &= ~TIM_CCMR1_OC1M; in TIM_OC1_SetConfig()
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f37x/
H A Dstm32f37x.h5023 #define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Outp… macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f0xx/
H A Dstm32f0xx.h5101 #define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Outp… macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f37x/
H A Dstm32f37x.h5023 #define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Outp… macro

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