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Searched refs:UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK (Results 1 – 21 of 21) sorted by relevance

/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_5_0_sh_mask.h765 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x40 macro
H A Duvd_6_0_sh_mask.h763 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x40 macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_5_0_sh_mask.h765 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x40 macro
H A Duvd_6_0_sh_mask.h763 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x40 macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_5_0_sh_mask.h765 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x40 macro
H A Duvd_6_0_sh_mask.h763 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x40 macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h514 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK … macro
H A Dvcn_2_5_sh_mask.h2145 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK … macro
H A Dvcn_2_0_0_sh_mask.h3271 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK … macro
H A Dvcn_2_6_0_sh_mask.h3816 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK … macro
H A Dvcn_3_0_0_sh_mask.h2890 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK … macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h514 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK … macro
H A Dvcn_2_5_sh_mask.h2145 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK … macro
H A Dvcn_2_0_0_sh_mask.h3271 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK … macro
H A Dvcn_2_6_0_sh_mask.h3816 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK … macro
H A Dvcn_3_0_0_sh_mask.h2890 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK … macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h514 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK … macro
H A Dvcn_2_5_sh_mask.h2145 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK … macro
H A Dvcn_2_0_0_sh_mask.h3271 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK … macro
H A Dvcn_2_6_0_sh_mask.h3816 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK … macro
H A Dvcn_3_0_0_sh_mask.h2890 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK … macro