1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _vcn_2_6_0_SH_MASK_HEADER 24 #define _vcn_2_6_0_SH_MASK_HEADER 25 26 27 // addressBlock: uvd0_ecpudec 28 //UVD_VCPU_CACHE_OFFSET0 29 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 30 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x001FFFFFL 31 //UVD_VCPU_CACHE_SIZE0 32 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 33 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x001FFFFFL 34 //UVD_VCPU_CACHE_OFFSET1 35 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 36 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x001FFFFFL 37 //UVD_VCPU_CACHE_SIZE1 38 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 39 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x001FFFFFL 40 //UVD_VCPU_CACHE_OFFSET2 41 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 42 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x001FFFFFL 43 //UVD_VCPU_CACHE_SIZE2 44 #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 45 #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001FFFFFL 46 //UVD_VCPU_CACHE_OFFSET3 47 #define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3__SHIFT 0x0 48 #define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3_MASK 0x001FFFFFL 49 //UVD_VCPU_CACHE_SIZE3 50 #define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3__SHIFT 0x0 51 #define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3_MASK 0x001FFFFFL 52 //UVD_VCPU_CACHE_OFFSET4 53 #define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4__SHIFT 0x0 54 #define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4_MASK 0x001FFFFFL 55 //UVD_VCPU_CACHE_SIZE4 56 #define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4__SHIFT 0x0 57 #define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4_MASK 0x001FFFFFL 58 //UVD_VCPU_CACHE_OFFSET5 59 #define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5__SHIFT 0x0 60 #define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5_MASK 0x001FFFFFL 61 //UVD_VCPU_CACHE_SIZE5 62 #define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5__SHIFT 0x0 63 #define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5_MASK 0x001FFFFFL 64 //UVD_VCPU_CACHE_OFFSET6 65 #define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6__SHIFT 0x0 66 #define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6_MASK 0x001FFFFFL 67 //UVD_VCPU_CACHE_SIZE6 68 #define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6__SHIFT 0x0 69 #define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6_MASK 0x001FFFFFL 70 //UVD_VCPU_CACHE_OFFSET7 71 #define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7__SHIFT 0x0 72 #define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7_MASK 0x001FFFFFL 73 //UVD_VCPU_CACHE_SIZE7 74 #define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7__SHIFT 0x0 75 #define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7_MASK 0x001FFFFFL 76 //UVD_VCPU_CACHE_OFFSET8 77 #define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8__SHIFT 0x0 78 #define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8_MASK 0x001FFFFFL 79 //UVD_VCPU_CACHE_SIZE8 80 #define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8__SHIFT 0x0 81 #define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8_MASK 0x001FFFFFL 82 //UVD_VCPU_NONCACHE_OFFSET0 83 #define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0__SHIFT 0x0 84 #define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0_MASK 0x01FFFFFFL 85 //UVD_VCPU_NONCACHE_SIZE0 86 #define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0__SHIFT 0x0 87 #define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0_MASK 0x001FFFFFL 88 //UVD_VCPU_NONCACHE_OFFSET1 89 #define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1__SHIFT 0x0 90 #define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1_MASK 0x01FFFFFFL 91 //UVD_VCPU_NONCACHE_SIZE1 92 #define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1__SHIFT 0x0 93 #define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1_MASK 0x001FFFFFL 94 //UVD_VCPU_CNTL 95 #define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0 96 #define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5 97 #define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6 98 #define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 99 #define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8 100 #define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 101 #define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa 102 #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb 103 #define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10 104 #define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12 105 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 106 #define UVD_VCPU_CNTL__BLK_RST__SHIFT 0x1c 107 #define UVD_VCPU_CNTL__IRQ_ERR_MASK 0x0000000FL 108 #define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x00000020L 109 #define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x00000040L 110 #define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00000080L 111 #define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x00000100L 112 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L 113 #define UVD_VCPU_CNTL__TRCE_EN_MASK 0x00000400L 114 #define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x00001800L 115 #define UVD_VCPU_CNTL__JTAG_EN_MASK 0x00010000L 116 #define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x00040000L 117 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L 118 #define UVD_VCPU_CNTL__BLK_RST_MASK 0x10000000L 119 //UVD_VCPU_PRID 120 #define UVD_VCPU_PRID__PRID__SHIFT 0x0 121 #define UVD_VCPU_PRID__PRID_MASK 0x0000FFFFL 122 //UVD_VCPU_TRCE 123 #define UVD_VCPU_TRCE__PC__SHIFT 0x0 124 #define UVD_VCPU_TRCE__PC_MASK 0x0FFFFFFFL 125 //UVD_VCPU_TRCE_RD 126 #define UVD_VCPU_TRCE_RD__DATA__SHIFT 0x0 127 #define UVD_VCPU_TRCE_RD__DATA_MASK 0xFFFFFFFFL 128 //UVD_VCPU_IND_INDEX 129 #define UVD_VCPU_IND_INDEX__INDEX__SHIFT 0x0 130 #define UVD_VCPU_IND_INDEX__INDEX_MASK 0x000001FFL 131 //UVD_VCPU_IND_DATA 132 #define UVD_VCPU_IND_DATA__DATA__SHIFT 0x0 133 #define UVD_VCPU_IND_DATA__DATA_MASK 0xFFFFFFFFL 134 135 136 // addressBlock: uvd0_jpegnpdec 137 //UVD_JPEG_CNTL 138 #define UVD_JPEG_CNTL__REQUEST_EN__SHIFT 0x1 139 #define UVD_JPEG_CNTL__ERR_RST_EN__SHIFT 0x2 140 #define UVD_JPEG_CNTL__HUFF_SPEED_EN__SHIFT 0x3 141 #define UVD_JPEG_CNTL__HUFF_SPEED_STATUS__SHIFT 0x4 142 #define UVD_JPEG_CNTL__REQUEST_EN_MASK 0x00000002L 143 #define UVD_JPEG_CNTL__ERR_RST_EN_MASK 0x00000004L 144 #define UVD_JPEG_CNTL__HUFF_SPEED_EN_MASK 0x00000008L 145 #define UVD_JPEG_CNTL__HUFF_SPEED_STATUS_MASK 0x00000010L 146 //UVD_JPEG_RB_BASE 147 #define UVD_JPEG_RB_BASE__RB_BYTE_OFF__SHIFT 0x0 148 #define UVD_JPEG_RB_BASE__RB_BASE__SHIFT 0x6 149 #define UVD_JPEG_RB_BASE__RB_BYTE_OFF_MASK 0x0000003FL 150 #define UVD_JPEG_RB_BASE__RB_BASE_MASK 0xFFFFFFC0L 151 //UVD_JPEG_RB_WPTR 152 #define UVD_JPEG_RB_WPTR__RB_WPTR__SHIFT 0x4 153 #define UVD_JPEG_RB_WPTR__RB_WPTR_MASK 0x3FFFFFF0L 154 //UVD_JPEG_RB_RPTR 155 #define UVD_JPEG_RB_RPTR__RB_RPTR__SHIFT 0x4 156 #define UVD_JPEG_RB_RPTR__RB_RPTR_MASK 0x3FFFFFF0L 157 //UVD_JPEG_RB_SIZE 158 #define UVD_JPEG_RB_SIZE__RB_SIZE__SHIFT 0x4 159 #define UVD_JPEG_RB_SIZE__RB_SIZE_MASK 0x3FFFFFF0L 160 //UVD_JPEG_DEC_CNT 161 #define UVD_JPEG_DEC_CNT__DECODE_COUNT__SHIFT 0x0 162 #define UVD_JPEG_DEC_CNT__DECODE_COUNT_MASK 0xFFFFFFFFL 163 //UVD_JPEG_SPS_INFO 164 #define UVD_JPEG_SPS_INFO__PIC_WIDTH__SHIFT 0x0 165 #define UVD_JPEG_SPS_INFO__PIC_HEIGHT__SHIFT 0x10 166 #define UVD_JPEG_SPS_INFO__PIC_WIDTH_MASK 0x0000FFFFL 167 #define UVD_JPEG_SPS_INFO__PIC_HEIGHT_MASK 0xFFFF0000L 168 //UVD_JPEG_SPS1_INFO 169 #define UVD_JPEG_SPS1_INFO__CHROMA_FORMAT_IDC__SHIFT 0x0 170 #define UVD_JPEG_SPS1_INFO__YUV422_SUBFORMAT__SHIFT 0x3 171 #define UVD_JPEG_SPS1_INFO__OUT_FMT_422__SHIFT 0x4 172 #define UVD_JPEG_SPS1_INFO__CHROMA_FORMAT_IDC_MASK 0x00000007L 173 #define UVD_JPEG_SPS1_INFO__YUV422_SUBFORMAT_MASK 0x00000008L 174 #define UVD_JPEG_SPS1_INFO__OUT_FMT_422_MASK 0x00000010L 175 //UVD_JPEG_RE_TIMER 176 #define UVD_JPEG_RE_TIMER__TIMER_OUT__SHIFT 0x0 177 #define UVD_JPEG_RE_TIMER__TIMER_OUT_EN__SHIFT 0x10 178 #define UVD_JPEG_RE_TIMER__TIMER_OUT_MASK 0x000000FFL 179 #define UVD_JPEG_RE_TIMER__TIMER_OUT_EN_MASK 0x00010000L 180 //UVD_JPEG_DEC_SCRATCH0 181 #define UVD_JPEG_DEC_SCRATCH0__SCRATCH0__SHIFT 0x0 182 #define UVD_JPEG_DEC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 183 //UVD_JPEG_INT_EN 184 #define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN__SHIFT 0x0 185 #define UVD_JPEG_INT_EN__JOB_AVAIL_EN__SHIFT 0x1 186 #define UVD_JPEG_INT_EN__FENCE_VAL_EN__SHIFT 0x2 187 #define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN__SHIFT 0x6 188 #define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN__SHIFT 0x7 189 #define UVD_JPEG_INT_EN__EOI_ERR_EN__SHIFT 0x8 190 #define UVD_JPEG_INT_EN__HFM_ERR_EN__SHIFT 0x9 191 #define UVD_JPEG_INT_EN__RST_ERR_EN__SHIFT 0xa 192 #define UVD_JPEG_INT_EN__ECS_MK_ERR_EN__SHIFT 0xb 193 #define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN__SHIFT 0xc 194 #define UVD_JPEG_INT_EN__MARKER_ERR_EN__SHIFT 0xd 195 #define UVD_JPEG_INT_EN__FMT_ERR_EN__SHIFT 0xe 196 #define UVD_JPEG_INT_EN__PROFILE_ERR_EN__SHIFT 0xf 197 #define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN_MASK 0x00000001L 198 #define UVD_JPEG_INT_EN__JOB_AVAIL_EN_MASK 0x00000002L 199 #define UVD_JPEG_INT_EN__FENCE_VAL_EN_MASK 0x00000004L 200 #define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN_MASK 0x00000040L 201 #define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN_MASK 0x00000080L 202 #define UVD_JPEG_INT_EN__EOI_ERR_EN_MASK 0x00000100L 203 #define UVD_JPEG_INT_EN__HFM_ERR_EN_MASK 0x00000200L 204 #define UVD_JPEG_INT_EN__RST_ERR_EN_MASK 0x00000400L 205 #define UVD_JPEG_INT_EN__ECS_MK_ERR_EN_MASK 0x00000800L 206 #define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN_MASK 0x00001000L 207 #define UVD_JPEG_INT_EN__MARKER_ERR_EN_MASK 0x00002000L 208 #define UVD_JPEG_INT_EN__FMT_ERR_EN_MASK 0x00004000L 209 #define UVD_JPEG_INT_EN__PROFILE_ERR_EN_MASK 0x00008000L 210 //UVD_JPEG_INT_STAT 211 #define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT__SHIFT 0x0 212 #define UVD_JPEG_INT_STAT__JOB_AVAIL_INT__SHIFT 0x1 213 #define UVD_JPEG_INT_STAT__FENCE_VAL_INT__SHIFT 0x2 214 #define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT__SHIFT 0x6 215 #define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT__SHIFT 0x7 216 #define UVD_JPEG_INT_STAT__EOI_ERR_INT__SHIFT 0x8 217 #define UVD_JPEG_INT_STAT__HFM_ERR_INT__SHIFT 0x9 218 #define UVD_JPEG_INT_STAT__RST_ERR_INT__SHIFT 0xa 219 #define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT__SHIFT 0xb 220 #define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT__SHIFT 0xc 221 #define UVD_JPEG_INT_STAT__MARKER_ERR_INT__SHIFT 0xd 222 #define UVD_JPEG_INT_STAT__FMT_ERR_INT__SHIFT 0xe 223 #define UVD_JPEG_INT_STAT__PROFILE_ERR_INT__SHIFT 0xf 224 #define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT_MASK 0x00000001L 225 #define UVD_JPEG_INT_STAT__JOB_AVAIL_INT_MASK 0x00000002L 226 #define UVD_JPEG_INT_STAT__FENCE_VAL_INT_MASK 0x00000004L 227 #define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT_MASK 0x00000040L 228 #define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT_MASK 0x00000080L 229 #define UVD_JPEG_INT_STAT__EOI_ERR_INT_MASK 0x00000100L 230 #define UVD_JPEG_INT_STAT__HFM_ERR_INT_MASK 0x00000200L 231 #define UVD_JPEG_INT_STAT__RST_ERR_INT_MASK 0x00000400L 232 #define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT_MASK 0x00000800L 233 #define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT_MASK 0x00001000L 234 #define UVD_JPEG_INT_STAT__MARKER_ERR_INT_MASK 0x00002000L 235 #define UVD_JPEG_INT_STAT__FMT_ERR_INT_MASK 0x00004000L 236 #define UVD_JPEG_INT_STAT__PROFILE_ERR_INT_MASK 0x00008000L 237 //UVD_JPEG_TIER_CNTL0 238 #define UVD_JPEG_TIER_CNTL0__TIER_SEL__SHIFT 0x0 239 #define UVD_JPEG_TIER_CNTL0__Y_COMP_ID__SHIFT 0x2 240 #define UVD_JPEG_TIER_CNTL0__U_COMP_ID__SHIFT 0x4 241 #define UVD_JPEG_TIER_CNTL0__V_COMP_ID__SHIFT 0x6 242 #define UVD_JPEG_TIER_CNTL0__Y_H_SAMP_FAC__SHIFT 0x8 243 #define UVD_JPEG_TIER_CNTL0__Y_V_SAMP_FAC__SHIFT 0xb 244 #define UVD_JPEG_TIER_CNTL0__U_H_SAMP_FAC__SHIFT 0xe 245 #define UVD_JPEG_TIER_CNTL0__U_V_SAMP_FAC__SHIFT 0x11 246 #define UVD_JPEG_TIER_CNTL0__V_H_SAMP_FAC__SHIFT 0x14 247 #define UVD_JPEG_TIER_CNTL0__V_V_SAMP_FAC__SHIFT 0x17 248 #define UVD_JPEG_TIER_CNTL0__Y_TQ__SHIFT 0x1a 249 #define UVD_JPEG_TIER_CNTL0__U_TQ__SHIFT 0x1c 250 #define UVD_JPEG_TIER_CNTL0__V_TQ__SHIFT 0x1e 251 #define UVD_JPEG_TIER_CNTL0__TIER_SEL_MASK 0x00000003L 252 #define UVD_JPEG_TIER_CNTL0__Y_COMP_ID_MASK 0x0000000CL 253 #define UVD_JPEG_TIER_CNTL0__U_COMP_ID_MASK 0x00000030L 254 #define UVD_JPEG_TIER_CNTL0__V_COMP_ID_MASK 0x000000C0L 255 #define UVD_JPEG_TIER_CNTL0__Y_H_SAMP_FAC_MASK 0x00000700L 256 #define UVD_JPEG_TIER_CNTL0__Y_V_SAMP_FAC_MASK 0x00003800L 257 #define UVD_JPEG_TIER_CNTL0__U_H_SAMP_FAC_MASK 0x0001C000L 258 #define UVD_JPEG_TIER_CNTL0__U_V_SAMP_FAC_MASK 0x000E0000L 259 #define UVD_JPEG_TIER_CNTL0__V_H_SAMP_FAC_MASK 0x00700000L 260 #define UVD_JPEG_TIER_CNTL0__V_V_SAMP_FAC_MASK 0x03800000L 261 #define UVD_JPEG_TIER_CNTL0__Y_TQ_MASK 0x0C000000L 262 #define UVD_JPEG_TIER_CNTL0__U_TQ_MASK 0x30000000L 263 #define UVD_JPEG_TIER_CNTL0__V_TQ_MASK 0xC0000000L 264 //UVD_JPEG_TIER_CNTL1 265 #define UVD_JPEG_TIER_CNTL1__SRC_WIDTH__SHIFT 0x0 266 #define UVD_JPEG_TIER_CNTL1__SRC_HEIGHT__SHIFT 0x10 267 #define UVD_JPEG_TIER_CNTL1__SRC_WIDTH_MASK 0x0000FFFFL 268 #define UVD_JPEG_TIER_CNTL1__SRC_HEIGHT_MASK 0xFFFF0000L 269 //UVD_JPEG_TIER_CNTL2 270 #define UVD_JPEG_TIER_CNTL2__TBL_ECS_SEL__SHIFT 0x0 271 #define UVD_JPEG_TIER_CNTL2__TBL_TYPE__SHIFT 0x1 272 #define UVD_JPEG_TIER_CNTL2__TQ__SHIFT 0x2 273 #define UVD_JPEG_TIER_CNTL2__TH__SHIFT 0x4 274 #define UVD_JPEG_TIER_CNTL2__TC__SHIFT 0x6 275 #define UVD_JPEG_TIER_CNTL2__TD__SHIFT 0x7 276 #define UVD_JPEG_TIER_CNTL2__TA__SHIFT 0xa 277 #define UVD_JPEG_TIER_CNTL2__TIER2_HTBL_CNTLEN__SHIFT 0xe 278 #define UVD_JPEG_TIER_CNTL2__DRI_VAL__SHIFT 0x10 279 #define UVD_JPEG_TIER_CNTL2__TBL_ECS_SEL_MASK 0x00000001L 280 #define UVD_JPEG_TIER_CNTL2__TBL_TYPE_MASK 0x00000002L 281 #define UVD_JPEG_TIER_CNTL2__TQ_MASK 0x0000000CL 282 #define UVD_JPEG_TIER_CNTL2__TH_MASK 0x00000030L 283 #define UVD_JPEG_TIER_CNTL2__TC_MASK 0x00000040L 284 #define UVD_JPEG_TIER_CNTL2__TD_MASK 0x00000380L 285 #define UVD_JPEG_TIER_CNTL2__TA_MASK 0x00001C00L 286 #define UVD_JPEG_TIER_CNTL2__TIER2_HTBL_CNTLEN_MASK 0x00004000L 287 #define UVD_JPEG_TIER_CNTL2__DRI_VAL_MASK 0xFFFF0000L 288 //UVD_JPEG_TIER_STATUS 289 #define UVD_JPEG_TIER_STATUS__BSI_FETCH_DONE__SHIFT 0x0 290 #define UVD_JPEG_TIER_STATUS__DECODE_DONE__SHIFT 0x1 291 #define UVD_JPEG_TIER_STATUS__BSI_FETCH_DONE_MASK 0x00000001L 292 #define UVD_JPEG_TIER_STATUS__DECODE_DONE_MASK 0x00000002L 293 //UVD_JPEG_OUTBUF_CNTL 294 #define UVD_JPEG_OUTBUF_CNTL__OUTBUF_CNT__SHIFT 0x0 295 #define UVD_JPEG_OUTBUF_CNTL__HGT_ALIGN__SHIFT 0x2 296 #define UVD_JPEG_OUTBUF_CNTL__JPEG0_DECODE_DONE_FIX__SHIFT 0x6 297 #define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_MAX_CNT__SHIFT 0x7 298 #define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_TIMER__SHIFT 0x9 299 #define UVD_JPEG_OUTBUF_CNTL__OUTBUF_CNT_MASK 0x00000003L 300 #define UVD_JPEG_OUTBUF_CNTL__HGT_ALIGN_MASK 0x00000004L 301 #define UVD_JPEG_OUTBUF_CNTL__JPEG0_DECODE_DONE_FIX_MASK 0x00000040L 302 #define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_MAX_CNT_MASK 0x00000180L 303 #define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_TIMER_MASK 0x00001E00L 304 //UVD_JPEG_OUTBUF_WPTR 305 #define UVD_JPEG_OUTBUF_WPTR__OUTBUF_WPTR__SHIFT 0x0 306 #define UVD_JPEG_OUTBUF_WPTR__OUTBUF_WPTR_MASK 0xFFFFFFFFL 307 //UVD_JPEG_OUTBUF_RPTR 308 #define UVD_JPEG_OUTBUF_RPTR__OUTBUF_RPTR__SHIFT 0x0 309 #define UVD_JPEG_OUTBUF_RPTR__OUTBUF_RPTR_MASK 0xFFFFFFFFL 310 //UVD_JPEG_PITCH 311 #define UVD_JPEG_PITCH__PITCH__SHIFT 0x0 312 #define UVD_JPEG_PITCH__PITCH_MASK 0xFFFFFFFFL 313 //UVD_JPEG_UV_PITCH 314 #define UVD_JPEG_UV_PITCH__UV_PITCH__SHIFT 0x0 315 #define UVD_JPEG_UV_PITCH__UV_PITCH_MASK 0xFFFFFFFFL 316 //JPEG_DEC_Y_GFX8_TILING_SURFACE 317 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0 318 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2 319 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4 320 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6 321 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8 322 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd 323 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10 324 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L 325 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL 326 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L 327 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L 328 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L 329 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L 330 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L 331 //JPEG_DEC_UV_GFX8_TILING_SURFACE 332 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0 333 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2 334 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4 335 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6 336 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8 337 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd 338 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10 339 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L 340 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL 341 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L 342 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L 343 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L 344 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L 345 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L 346 //JPEG_DEC_GFX8_ADDR_CONFIG 347 #define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 348 #define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L 349 //JPEG_DEC_Y_GFX10_TILING_SURFACE 350 #define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 351 #define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 352 //JPEG_DEC_UV_GFX10_TILING_SURFACE 353 #define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 354 #define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 355 //JPEG_DEC_GFX10_ADDR_CONFIG 356 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 357 #define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 358 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 359 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 360 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 361 #define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 362 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 363 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 364 //JPEG_DEC_ADDR_MODE 365 #define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y__SHIFT 0x0 366 #define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV__SHIFT 0x2 367 #define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL__SHIFT 0xc 368 #define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y_MASK 0x00000003L 369 #define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV_MASK 0x0000000CL 370 #define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL_MASK 0x00007000L 371 //UVD_JPEG_OUTPUT_XY 372 #define UVD_JPEG_OUTPUT_XY__OUTPUT_X__SHIFT 0x0 373 #define UVD_JPEG_OUTPUT_XY__OUTPUT_Y__SHIFT 0x10 374 #define UVD_JPEG_OUTPUT_XY__OUTPUT_X_MASK 0x00003FFFL 375 #define UVD_JPEG_OUTPUT_XY__OUTPUT_Y_MASK 0x3FFF0000L 376 //UVD_JPEG_GPCOM_CMD 377 #define UVD_JPEG_GPCOM_CMD__CMD__SHIFT 0x1 378 #define UVD_JPEG_GPCOM_CMD__CMD_MASK 0x0000000EL 379 //UVD_JPEG_GPCOM_DATA0 380 #define UVD_JPEG_GPCOM_DATA0__DATA0__SHIFT 0x0 381 #define UVD_JPEG_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL 382 //UVD_JPEG_GPCOM_DATA1 383 #define UVD_JPEG_GPCOM_DATA1__DATA1__SHIFT 0x0 384 #define UVD_JPEG_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL 385 //UVD_JPEG_INDEX 386 #define UVD_JPEG_INDEX__INDEX__SHIFT 0x0 387 #define UVD_JPEG_INDEX__INDEX_MASK 0x000001FFL 388 //UVD_JPEG_DATA 389 #define UVD_JPEG_DATA__DATA__SHIFT 0x0 390 #define UVD_JPEG_DATA__DATA_MASK 0xFFFFFFFFL 391 //UVD_JPEG_SCRATCH1 392 #define UVD_JPEG_SCRATCH1__SCRATCH1__SHIFT 0x0 393 #define UVD_JPEG_SCRATCH1__SCRATCH1_MASK 0xFFFFFFFFL 394 //UVD_JPEG_DEC_SOFT_RST 395 #define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET__SHIFT 0x0 396 #define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS__SHIFT 0x10 397 #define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET_MASK 0x00000001L 398 #define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS_MASK 0x00010000L 399 400 401 // addressBlock: uvd0_lmi_adpdec 402 //UVD_LMI_RE_64BIT_BAR_LOW 403 #define UVD_LMI_RE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 404 #define UVD_LMI_RE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 405 //UVD_LMI_RE_64BIT_BAR_HIGH 406 #define UVD_LMI_RE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 407 #define UVD_LMI_RE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 408 //UVD_LMI_IT_64BIT_BAR_LOW 409 #define UVD_LMI_IT_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 410 #define UVD_LMI_IT_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 411 //UVD_LMI_IT_64BIT_BAR_HIGH 412 #define UVD_LMI_IT_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 413 #define UVD_LMI_IT_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 414 //UVD_LMI_MP_64BIT_BAR_LOW 415 #define UVD_LMI_MP_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 416 #define UVD_LMI_MP_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 417 //UVD_LMI_MP_64BIT_BAR_HIGH 418 #define UVD_LMI_MP_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 419 #define UVD_LMI_MP_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 420 //UVD_LMI_CM_64BIT_BAR_LOW 421 #define UVD_LMI_CM_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 422 #define UVD_LMI_CM_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 423 //UVD_LMI_CM_64BIT_BAR_HIGH 424 #define UVD_LMI_CM_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 425 #define UVD_LMI_CM_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 426 //UVD_LMI_DB_64BIT_BAR_LOW 427 #define UVD_LMI_DB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 428 #define UVD_LMI_DB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 429 //UVD_LMI_DB_64BIT_BAR_HIGH 430 #define UVD_LMI_DB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 431 #define UVD_LMI_DB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 432 //UVD_LMI_DBW_64BIT_BAR_LOW 433 #define UVD_LMI_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 434 #define UVD_LMI_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 435 //UVD_LMI_DBW_64BIT_BAR_HIGH 436 #define UVD_LMI_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 437 #define UVD_LMI_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 438 //UVD_LMI_IDCT_64BIT_BAR_LOW 439 #define UVD_LMI_IDCT_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 440 #define UVD_LMI_IDCT_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 441 //UVD_LMI_IDCT_64BIT_BAR_HIGH 442 #define UVD_LMI_IDCT_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 443 #define UVD_LMI_IDCT_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 444 //UVD_LMI_MPRD_S0_64BIT_BAR_LOW 445 #define UVD_LMI_MPRD_S0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 446 #define UVD_LMI_MPRD_S0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 447 //UVD_LMI_MPRD_S0_64BIT_BAR_HIGH 448 #define UVD_LMI_MPRD_S0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 449 #define UVD_LMI_MPRD_S0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 450 //UVD_LMI_MPRD_S1_64BIT_BAR_LOW 451 #define UVD_LMI_MPRD_S1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 452 #define UVD_LMI_MPRD_S1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 453 //UVD_LMI_MPRD_S1_64BIT_BAR_HIGH 454 #define UVD_LMI_MPRD_S1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 455 #define UVD_LMI_MPRD_S1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 456 //UVD_LMI_MPRD_DBW_64BIT_BAR_LOW 457 #define UVD_LMI_MPRD_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 458 #define UVD_LMI_MPRD_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 459 //UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH 460 #define UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 461 #define UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 462 //UVD_LMI_MPC_64BIT_BAR_LOW 463 #define UVD_LMI_MPC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 464 #define UVD_LMI_MPC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 465 //UVD_LMI_MPC_64BIT_BAR_HIGH 466 #define UVD_LMI_MPC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 467 #define UVD_LMI_MPC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 468 //UVD_LMI_RBC_RB_64BIT_BAR_LOW 469 #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 470 #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 471 //UVD_LMI_RBC_RB_64BIT_BAR_HIGH 472 #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 473 #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 474 //UVD_LMI_RBC_IB_64BIT_BAR_LOW 475 #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 476 #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 477 //UVD_LMI_RBC_IB_64BIT_BAR_HIGH 478 #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 479 #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 480 //UVD_LMI_LBSI_64BIT_BAR_LOW 481 #define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 482 #define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 483 //UVD_LMI_LBSI_64BIT_BAR_HIGH 484 #define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 485 #define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 486 //UVD_LMI_VCPU_NC0_64BIT_BAR_LOW 487 #define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 488 #define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 489 //UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH 490 #define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 491 #define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 492 //UVD_LMI_VCPU_NC1_64BIT_BAR_LOW 493 #define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 494 #define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 495 //UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH 496 #define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 497 #define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 498 //UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 499 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 500 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 501 //UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 502 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 503 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 504 //UVD_LMI_CENC_64BIT_BAR_LOW 505 #define UVD_LMI_CENC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 506 #define UVD_LMI_CENC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 507 //UVD_LMI_CENC_64BIT_BAR_HIGH 508 #define UVD_LMI_CENC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 509 #define UVD_LMI_CENC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 510 //UVD_LMI_SRE_64BIT_BAR_LOW 511 #define UVD_LMI_SRE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 512 #define UVD_LMI_SRE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 513 //UVD_LMI_SRE_64BIT_BAR_HIGH 514 #define UVD_LMI_SRE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 515 #define UVD_LMI_SRE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 516 //UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW 517 #define UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 518 #define UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 519 //UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH 520 #define UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 521 #define UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 522 //UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW 523 #define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 524 #define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 525 //UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH 526 #define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 527 #define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 528 //UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW 529 #define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 530 #define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 531 //UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH 532 #define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 533 #define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 534 //UVD_LMI_MIF_REF_64BIT_BAR_LOW 535 #define UVD_LMI_MIF_REF_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 536 #define UVD_LMI_MIF_REF_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 537 //UVD_LMI_MIF_REF_64BIT_BAR_HIGH 538 #define UVD_LMI_MIF_REF_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 539 #define UVD_LMI_MIF_REF_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 540 //UVD_LMI_MIF_DBW_64BIT_BAR_LOW 541 #define UVD_LMI_MIF_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 542 #define UVD_LMI_MIF_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 543 //UVD_LMI_MIF_DBW_64BIT_BAR_HIGH 544 #define UVD_LMI_MIF_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 545 #define UVD_LMI_MIF_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 546 //UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW 547 #define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 548 #define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 549 //UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH 550 #define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 551 #define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 552 //UVD_LMI_MIF_BSP0_64BIT_BAR_LOW 553 #define UVD_LMI_MIF_BSP0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 554 #define UVD_LMI_MIF_BSP0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 555 //UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH 556 #define UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 557 #define UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 558 //UVD_LMI_MIF_BSP1_64BIT_BAR_LOW 559 #define UVD_LMI_MIF_BSP1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 560 #define UVD_LMI_MIF_BSP1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 561 //UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH 562 #define UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 563 #define UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 564 //UVD_LMI_MIF_BSP2_64BIT_BAR_LOW 565 #define UVD_LMI_MIF_BSP2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 566 #define UVD_LMI_MIF_BSP2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 567 //UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH 568 #define UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 569 #define UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 570 //UVD_LMI_MIF_BSP3_64BIT_BAR_LOW 571 #define UVD_LMI_MIF_BSP3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 572 #define UVD_LMI_MIF_BSP3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 573 //UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH 574 #define UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 575 #define UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 576 //UVD_LMI_MIF_BSD0_64BIT_BAR_LOW 577 #define UVD_LMI_MIF_BSD0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 578 #define UVD_LMI_MIF_BSD0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 579 //UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH 580 #define UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 581 #define UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 582 //UVD_LMI_MIF_BSD1_64BIT_BAR_LOW 583 #define UVD_LMI_MIF_BSD1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 584 #define UVD_LMI_MIF_BSD1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 585 //UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH 586 #define UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 587 #define UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 588 //UVD_LMI_MIF_BSD2_64BIT_BAR_LOW 589 #define UVD_LMI_MIF_BSD2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 590 #define UVD_LMI_MIF_BSD2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 591 //UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH 592 #define UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 593 #define UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 594 //UVD_LMI_MIF_BSD3_64BIT_BAR_LOW 595 #define UVD_LMI_MIF_BSD3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 596 #define UVD_LMI_MIF_BSD3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 597 //UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH 598 #define UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 599 #define UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 600 //UVD_LMI_MIF_BSD4_64BIT_BAR_LOW 601 #define UVD_LMI_MIF_BSD4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 602 #define UVD_LMI_MIF_BSD4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 603 //UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH 604 #define UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 605 #define UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 606 //UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 607 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 608 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 609 //UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 610 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 611 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 612 //UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW 613 #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 614 #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 615 //UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH 616 #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 617 #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 618 //UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 619 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 620 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 621 //UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 622 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 623 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 624 //UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW 625 #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 626 #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 627 //UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH 628 #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 629 #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 630 //UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW 631 #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 632 #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 633 //UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH 634 #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 635 #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 636 //UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW 637 #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 638 #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 639 //UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH 640 #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 641 #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 642 //UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW 643 #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 644 #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 645 //UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH 646 #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 647 #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 648 //UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW 649 #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 650 #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 651 //UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH 652 #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 653 #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 654 //UVD_LMI_MIF_SCLR_64BIT_BAR_LOW 655 #define UVD_LMI_MIF_SCLR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 656 #define UVD_LMI_MIF_SCLR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 657 //UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH 658 #define UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 659 #define UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 660 //UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW 661 #define UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 662 #define UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 663 //UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH 664 #define UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 665 #define UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 666 //UVD_LMI_SPH_64BIT_BAR_HIGH 667 #define UVD_LMI_SPH_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 668 #define UVD_LMI_SPH_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 669 //UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW 670 #define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 671 #define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 672 //UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH 673 #define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 674 #define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 675 //UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW 676 #define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 677 #define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 678 //UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH 679 #define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 680 #define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 681 //UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW 682 #define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 683 #define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 684 //UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH 685 #define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 686 #define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 687 //UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW 688 #define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 689 #define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 690 //UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH 691 #define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 692 #define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 693 //UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW 694 #define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 695 #define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 696 //UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH 697 #define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 698 #define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 699 //UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW 700 #define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 701 #define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 702 //UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH 703 #define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 704 #define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 705 //UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW 706 #define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 707 #define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 708 //UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH 709 #define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 710 #define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 711 //UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW 712 #define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 713 #define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 714 //UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH 715 #define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 716 #define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 717 //UVD_LMI_MMSCH_NC_VMID 718 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID__SHIFT 0x0 719 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID__SHIFT 0x4 720 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID__SHIFT 0x8 721 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID__SHIFT 0xc 722 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID__SHIFT 0x10 723 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID__SHIFT 0x14 724 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID__SHIFT 0x18 725 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID__SHIFT 0x1c 726 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID_MASK 0x0000000FL 727 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID_MASK 0x000000F0L 728 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID_MASK 0x00000F00L 729 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID_MASK 0x0000F000L 730 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID_MASK 0x000F0000L 731 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID_MASK 0x00F00000L 732 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID_MASK 0x0F000000L 733 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID_MASK 0xF0000000L 734 //UVD_LMI_MMSCH_CTRL 735 #define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN__SHIFT 0x0 736 #define UVD_LMI_MMSCH_CTRL__MMSCH_VM__SHIFT 0x1 737 #define UVD_LMI_MMSCH_CTRL__PRIV_CLIENT_MMSCH__SHIFT 0x2 738 #define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP__SHIFT 0x3 739 #define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP__SHIFT 0x5 740 #define UVD_LMI_MMSCH_CTRL__MMSCH_RD__SHIFT 0x7 741 #define UVD_LMI_MMSCH_CTRL__MMSCH_WR__SHIFT 0x9 742 #define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP__SHIFT 0xb 743 #define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP__SHIFT 0xc 744 #define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN_MASK 0x00000001L 745 #define UVD_LMI_MMSCH_CTRL__MMSCH_VM_MASK 0x00000002L 746 #define UVD_LMI_MMSCH_CTRL__PRIV_CLIENT_MMSCH_MASK 0x00000004L 747 #define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP_MASK 0x00000018L 748 #define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP_MASK 0x00000060L 749 #define UVD_LMI_MMSCH_CTRL__MMSCH_RD_MASK 0x00000180L 750 #define UVD_LMI_MMSCH_CTRL__MMSCH_WR_MASK 0x00000600L 751 #define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP_MASK 0x00000800L 752 #define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP_MASK 0x00001000L 753 //UVD_MMSCH_LMI_STATUS 754 #define UVD_MMSCH_LMI_STATUS__MMSCH_LMI_WRITE_CLEAN__SHIFT 0x2 755 #define UVD_MMSCH_LMI_STATUS__MMSCH_RD_CLEAN__SHIFT 0xd 756 #define UVD_MMSCH_LMI_STATUS__MMSCH_WR_CLEAN__SHIFT 0xe 757 #define UVD_MMSCH_LMI_STATUS__MMSCH_LMI_WRITE_CLEAN_MASK 0x00000004L 758 #define UVD_MMSCH_LMI_STATUS__MMSCH_RD_CLEAN_MASK 0x00002000L 759 #define UVD_MMSCH_LMI_STATUS__MMSCH_WR_CLEAN_MASK 0x00004000L 760 //UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW 761 #define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 762 #define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 763 //UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH 764 #define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 765 #define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 766 //UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW 767 #define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 768 #define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 769 //UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH 770 #define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 771 #define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 772 //UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW 773 #define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 774 #define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 775 //UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH 776 #define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 777 #define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 778 //UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW 779 #define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 780 #define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 781 //UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH 782 #define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 783 #define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 784 //UVD_ADP_ATOMIC_CONFIG 785 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER0_WR_CACHE__SHIFT 0x0 786 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER1_WR_CACHE__SHIFT 0x4 787 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER2_WR_CACHE__SHIFT 0x8 788 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER3_WR_CACHE__SHIFT 0xc 789 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_RD_URG__SHIFT 0x10 790 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER0_WR_CACHE_MASK 0x0000000FL 791 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER1_WR_CACHE_MASK 0x000000F0L 792 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER2_WR_CACHE_MASK 0x00000F00L 793 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER3_WR_CACHE_MASK 0x0000F000L 794 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_RD_URG_MASK 0x000F0000L 795 //UVD_LMI_ARB_CTRL2 796 #define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN__SHIFT 0x0 797 #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN__SHIFT 0x1 798 #define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST__SHIFT 0x2 799 #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST__SHIFT 0x6 800 #define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX__SHIFT 0xa 801 #define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX__SHIFT 0x14 802 #define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN_MASK 0x00000001L 803 #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN_MASK 0x00000002L 804 #define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST_MASK 0x0000003CL 805 #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST_MASK 0x000003C0L 806 #define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX_MASK 0x000FFC00L 807 #define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX_MASK 0xFFF00000L 808 //UVD_LMI_VCPU_CACHE_VMIDS_MULTI 809 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID__SHIFT 0x0 810 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID__SHIFT 0x4 811 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID__SHIFT 0x8 812 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID__SHIFT 0xc 813 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID__SHIFT 0x10 814 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID__SHIFT 0x14 815 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID__SHIFT 0x18 816 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID__SHIFT 0x1c 817 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID_MASK 0x0000000FL 818 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID_MASK 0x000000F0L 819 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID_MASK 0x00000F00L 820 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID_MASK 0x0000F000L 821 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID_MASK 0x000F0000L 822 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID_MASK 0x00F00000L 823 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID_MASK 0x0F000000L 824 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID_MASK 0xF0000000L 825 //UVD_LMI_VCPU_NC_VMIDS_MULTI 826 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID__SHIFT 0x4 827 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID__SHIFT 0x8 828 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID__SHIFT 0xc 829 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID__SHIFT 0x10 830 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID__SHIFT 0x14 831 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID__SHIFT 0x18 832 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID_MASK 0x000000F0L 833 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID_MASK 0x00000F00L 834 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID_MASK 0x0000F000L 835 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID_MASK 0x000F0000L 836 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID_MASK 0x00F00000L 837 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID_MASK 0x0F000000L 838 //UVD_LMI_LAT_CTRL 839 #define UVD_LMI_LAT_CTRL__SCALE__SHIFT 0x0 840 #define UVD_LMI_LAT_CTRL__MAX_START__SHIFT 0x8 841 #define UVD_LMI_LAT_CTRL__MIN_START__SHIFT 0x9 842 #define UVD_LMI_LAT_CTRL__AVG_START__SHIFT 0xa 843 #define UVD_LMI_LAT_CTRL__PERFMON_SYNC__SHIFT 0xb 844 #define UVD_LMI_LAT_CTRL__SKIP__SHIFT 0x10 845 #define UVD_LMI_LAT_CTRL__SCALE_MASK 0x000000FFL 846 #define UVD_LMI_LAT_CTRL__MAX_START_MASK 0x00000100L 847 #define UVD_LMI_LAT_CTRL__MIN_START_MASK 0x00000200L 848 #define UVD_LMI_LAT_CTRL__AVG_START_MASK 0x00000400L 849 #define UVD_LMI_LAT_CTRL__PERFMON_SYNC_MASK 0x00000800L 850 #define UVD_LMI_LAT_CTRL__SKIP_MASK 0x000F0000L 851 //UVD_LMI_LAT_CNTR 852 #define UVD_LMI_LAT_CNTR__MAX_LAT__SHIFT 0x0 853 #define UVD_LMI_LAT_CNTR__MIN_LAT__SHIFT 0x8 854 #define UVD_LMI_LAT_CNTR__MAX_LAT_MASK 0x000000FFL 855 #define UVD_LMI_LAT_CNTR__MIN_LAT_MASK 0x0000FF00L 856 //UVD_LMI_AVG_LAT_CNTR 857 #define UVD_LMI_AVG_LAT_CNTR__ENV_LOW__SHIFT 0x0 858 #define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT 0x8 859 #define UVD_LMI_AVG_LAT_CNTR__ENV_HIT__SHIFT 0x10 860 #define UVD_LMI_AVG_LAT_CNTR__ENV_LOW_MASK 0x000000FFL 861 #define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH_MASK 0x0000FF00L 862 #define UVD_LMI_AVG_LAT_CNTR__ENV_HIT_MASK 0xFFFF0000L 863 //UVD_LMI_SPH 864 #define UVD_LMI_SPH__ADDR__SHIFT 0x0 865 #define UVD_LMI_SPH__STS__SHIFT 0x1c 866 #define UVD_LMI_SPH__STS_VALID__SHIFT 0x1e 867 #define UVD_LMI_SPH__STS_OVERFLOW__SHIFT 0x1f 868 #define UVD_LMI_SPH__ADDR_MASK 0x0FFFFFFFL 869 #define UVD_LMI_SPH__STS_MASK 0x30000000L 870 #define UVD_LMI_SPH__STS_VALID_MASK 0x40000000L 871 #define UVD_LMI_SPH__STS_OVERFLOW_MASK 0x80000000L 872 //UVD_LMI_VCPU_CACHE_VMID 873 #define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 874 #define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL 875 //UVD_LMI_CTRL2 876 #define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 877 #define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 878 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 879 #define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 880 #define UVD_LMI_CTRL2__CRC1_RESET__SHIFT 0x4 881 #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 882 #define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 883 #define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 884 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb 885 #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd 886 #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe 887 #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf 888 #define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10 889 #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 890 #define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP__SHIFT 0x19 891 #define UVD_LMI_CTRL2__NJ_MIF_GATING__SHIFT 0x1a 892 #define UVD_LMI_CTRL2__CRC1_SEL__SHIFT 0x1b 893 #define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L 894 #define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L 895 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L 896 #define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L 897 #define UVD_LMI_CTRL2__CRC1_RESET_MASK 0x00000010L 898 #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x00000080L 899 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L 900 #define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L 901 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L 902 #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x00002000L 903 #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x00004000L 904 #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L 905 #define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x00010000L 906 #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x01FE0000L 907 #define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP_MASK 0x02000000L 908 #define UVD_LMI_CTRL2__NJ_MIF_GATING_MASK 0x04000000L 909 #define UVD_LMI_CTRL2__CRC1_SEL_MASK 0xF8000000L 910 //UVD_LMI_URGENT_CTRL 911 #define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT 0x0 912 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL__SHIFT 0x1 913 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT 0x2 914 #define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT 0x8 915 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL__SHIFT 0x9 916 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0xa 917 #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL__SHIFT 0x10 918 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL__SHIFT 0x11 919 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT__SHIFT 0x12 920 #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL__SHIFT 0x18 921 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL__SHIFT 0x19 922 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT__SHIFT 0x1a 923 #define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK 0x00000001L 924 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL_MASK 0x00000002L 925 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK 0x0000003CL 926 #define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK 0x00000100L 927 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL_MASK 0x00000200L 928 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK 0x00003C00L 929 #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL_MASK 0x00010000L 930 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL_MASK 0x00020000L 931 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT_MASK 0x003C0000L 932 #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL_MASK 0x01000000L 933 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL_MASK 0x02000000L 934 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT_MASK 0x3C000000L 935 //UVD_LMI_CTRL 936 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 937 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 938 #define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 939 #define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb 940 #define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc 941 #define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd 942 #define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe 943 #define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf 944 #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14 945 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 946 #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 947 #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 948 #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 949 #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 950 #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a 951 #define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ__SHIFT 0x1b 952 #define UVD_LMI_CTRL__MC_BLK_RST__SHIFT 0x1c 953 #define UVD_LMI_CTRL__UMC_BLK_RST__SHIFT 0x1d 954 #define UVD_LMI_CTRL__RFU__SHIFT 0x1e 955 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0x000000FFL 956 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L 957 #define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L 958 #define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L 959 #define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L 960 #define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L 961 #define UVD_LMI_CTRL__CRC_RESET_MASK 0x00004000L 962 #define UVD_LMI_CTRL__CRC_SEL_MASK 0x000F8000L 963 #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x00100000L 964 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L 965 #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x00400000L 966 #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x00800000L 967 #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L 968 #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L 969 #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x04000000L 970 #define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ_MASK 0x08000000L 971 #define UVD_LMI_CTRL__MC_BLK_RST_MASK 0x10000000L 972 #define UVD_LMI_CTRL__UMC_BLK_RST_MASK 0x20000000L 973 #define UVD_LMI_CTRL__RFU_MASK 0xC0000000L 974 //UVD_LMI_STATUS 975 #define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 976 #define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 977 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 978 #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 979 #define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4 980 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5 981 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 982 #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7 983 #define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8 984 #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 985 #define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa 986 #define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb 987 #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc 988 #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd 989 #define UVD_LMI_STATUS__BSP0_WRITE_CLEAN__SHIFT 0x12 990 #define UVD_LMI_STATUS__BSP1_WRITE_CLEAN__SHIFT 0x13 991 #define UVD_LMI_STATUS__BSP2_WRITE_CLEAN__SHIFT 0x14 992 #define UVD_LMI_STATUS__BSP3_WRITE_CLEAN__SHIFT 0x15 993 #define UVD_LMI_STATUS__CENC_READ_CLEAN__SHIFT 0x16 994 #define UVD_LMI_STATUS__READ_CLEAN_MASK 0x00000001L 995 #define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x00000002L 996 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x00000004L 997 #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x00000008L 998 #define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x00000010L 999 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x00000020L 1000 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x00000040L 1001 #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x00000080L 1002 #define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x00000100L 1003 #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x00000200L 1004 #define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x00000400L 1005 #define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x00000800L 1006 #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x00001000L 1007 #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x00002000L 1008 #define UVD_LMI_STATUS__BSP0_WRITE_CLEAN_MASK 0x00040000L 1009 #define UVD_LMI_STATUS__BSP1_WRITE_CLEAN_MASK 0x00080000L 1010 #define UVD_LMI_STATUS__BSP2_WRITE_CLEAN_MASK 0x00100000L 1011 #define UVD_LMI_STATUS__BSP3_WRITE_CLEAN_MASK 0x00200000L 1012 #define UVD_LMI_STATUS__CENC_READ_CLEAN_MASK 0x00400000L 1013 //UVD_LMI_PERFMON_CTRL 1014 #define UVD_LMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0 1015 #define UVD_LMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8 1016 #define UVD_LMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L 1017 #define UVD_LMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00001F00L 1018 //UVD_LMI_PERFMON_COUNT_LO 1019 #define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0 1020 #define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL 1021 //UVD_LMI_PERFMON_COUNT_HI 1022 #define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0 1023 #define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL 1024 //UVD_LMI_ADP_SWAP_CNTL 1025 #define UVD_LMI_ADP_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6 1026 #define UVD_LMI_ADP_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8 1027 #define UVD_LMI_ADP_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa 1028 #define UVD_LMI_ADP_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc 1029 #define UVD_LMI_ADP_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe 1030 #define UVD_LMI_ADP_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10 1031 #define UVD_LMI_ADP_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12 1032 #define UVD_LMI_ADP_SWAP_CNTL__ACAP_MC_SWAP__SHIFT 0x14 1033 #define UVD_LMI_ADP_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18 1034 #define UVD_LMI_ADP_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c 1035 #define UVD_LMI_ADP_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e 1036 #define UVD_LMI_ADP_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0x000000C0L 1037 #define UVD_LMI_ADP_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000300L 1038 #define UVD_LMI_ADP_SWAP_CNTL__CM_MC_SWAP_MASK 0x00000C00L 1039 #define UVD_LMI_ADP_SWAP_CNTL__IT_MC_SWAP_MASK 0x00003000L 1040 #define UVD_LMI_ADP_SWAP_CNTL__DB_R_MC_SWAP_MASK 0x0000C000L 1041 #define UVD_LMI_ADP_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x00030000L 1042 #define UVD_LMI_ADP_SWAP_CNTL__CSM_MC_SWAP_MASK 0x000C0000L 1043 #define UVD_LMI_ADP_SWAP_CNTL__ACAP_MC_SWAP_MASK 0x00300000L 1044 #define UVD_LMI_ADP_SWAP_CNTL__DBW_MC_SWAP_MASK 0x03000000L 1045 #define UVD_LMI_ADP_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L 1046 #define UVD_LMI_ADP_SWAP_CNTL__MP_MC_SWAP_MASK 0xC0000000L 1047 //UVD_LMI_RBC_RB_VMID 1048 #define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0 1049 #define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0x0000000FL 1050 //UVD_LMI_RBC_IB_VMID 1051 #define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0 1052 #define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0x0000000FL 1053 //UVD_LMI_MC_CREDITS 1054 #define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS__SHIFT 0x0 1055 #define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS__SHIFT 0x8 1056 #define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS__SHIFT 0x10 1057 #define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS__SHIFT 0x18 1058 #define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS_MASK 0x0000003FL 1059 #define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS_MASK 0x00003F00L 1060 #define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS_MASK 0x003F0000L 1061 #define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS_MASK 0x3F000000L 1062 //UVD_LMI_ADP_IND_INDEX 1063 #define UVD_LMI_ADP_IND_INDEX__INDEX__SHIFT 0x0 1064 #define UVD_LMI_ADP_IND_INDEX__INDEX_MASK 0x00001FFFL 1065 //UVD_LMI_ADP_IND_DATA 1066 #define UVD_LMI_ADP_IND_DATA__DATA__SHIFT 0x0 1067 #define UVD_LMI_ADP_IND_DATA__DATA_MASK 0xFFFFFFFFL 1068 //VCN_RAS_CNTL 1069 #define VCN_RAS_CNTL__VCPU_VCODEC_IH_EN__SHIFT 0x0 1070 #define VCN_RAS_CNTL__MMSCH_FATAL_ERROR_EN__SHIFT 0x1 1071 #define VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN__SHIFT 0x4 1072 #define VCN_RAS_CNTL__MMSCH_PMI_EN__SHIFT 0x5 1073 #define VCN_RAS_CNTL__VCPU_VCODEC_REARM__SHIFT 0x8 1074 #define VCN_RAS_CNTL__MMSCH_REARM__SHIFT 0x9 1075 #define VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN__SHIFT 0xc 1076 #define VCN_RAS_CNTL__VCPU_VCODEC_READY__SHIFT 0x10 1077 #define VCN_RAS_CNTL__MMSCH_READY__SHIFT 0x11 1078 #define VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK 0x00000001L 1079 #define VCN_RAS_CNTL__MMSCH_FATAL_ERROR_EN_MASK 0x00000002L 1080 #define VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK 0x00000010L 1081 #define VCN_RAS_CNTL__MMSCH_PMI_EN_MASK 0x00000020L 1082 #define VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK 0x00000100L 1083 #define VCN_RAS_CNTL__MMSCH_REARM_MASK 0x00000200L 1084 #define VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK 0x00001000L 1085 #define VCN_RAS_CNTL__VCPU_VCODEC_READY_MASK 0x00010000L 1086 #define VCN_RAS_CNTL__MMSCH_READY_MASK 0x00020000L 1087 1088 1089 // addressBlock: uvd0_mmsch_dec 1090 //MMSCH_UCODE_ADDR 1091 #define MMSCH_UCODE_ADDR__UCODE_ADDR__SHIFT 0x2 1092 #define MMSCH_UCODE_ADDR__UCODE_LOCK__SHIFT 0x1f 1093 #define MMSCH_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFCL 1094 #define MMSCH_UCODE_ADDR__UCODE_LOCK_MASK 0x80000000L 1095 //MMSCH_UCODE_DATA 1096 #define MMSCH_UCODE_DATA__UCODE_DATA__SHIFT 0x0 1097 #define MMSCH_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL 1098 //MMSCH_SRAM_ADDR 1099 #define MMSCH_SRAM_ADDR__SRAM_ADDR__SHIFT 0x2 1100 #define MMSCH_SRAM_ADDR__SRAM_LOCK__SHIFT 0x1f 1101 #define MMSCH_SRAM_ADDR__SRAM_ADDR_MASK 0x00001FFCL 1102 #define MMSCH_SRAM_ADDR__SRAM_LOCK_MASK 0x80000000L 1103 //MMSCH_SRAM_DATA 1104 #define MMSCH_SRAM_DATA__SRAM_DATA__SHIFT 0x0 1105 #define MMSCH_SRAM_DATA__SRAM_DATA_MASK 0xFFFFFFFFL 1106 //MMSCH_VF_SRAM_OFFSET 1107 #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET__SHIFT 0x2 1108 #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF__SHIFT 0x10 1109 #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET_MASK 0x00001FFCL 1110 #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF_MASK 0x00FF0000L 1111 //MMSCH_DB_SRAM_OFFSET 1112 #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET__SHIFT 0x2 1113 #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG__SHIFT 0x10 1114 #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG__SHIFT 0x18 1115 #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET_MASK 0x00001FFCL 1116 #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG_MASK 0x00FF0000L 1117 #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG_MASK 0xFF000000L 1118 //MMSCH_CTX_SRAM_OFFSET 1119 #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET__SHIFT 0x2 1120 #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE__SHIFT 0x10 1121 #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET_MASK 0x00001FFCL 1122 #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE_MASK 0xFFFF0000L 1123 //MMSCH_INTR 1124 #define MMSCH_INTR__INTR__SHIFT 0x0 1125 #define MMSCH_INTR__INTR_MASK 0x00001FFFL 1126 //MMSCH_INTR_ACK 1127 #define MMSCH_INTR_ACK__INTR__SHIFT 0x0 1128 #define MMSCH_INTR_ACK__INTR_MASK 0x00001FFFL 1129 //MMSCH_INTR_STATUS 1130 #define MMSCH_INTR_STATUS__INTR__SHIFT 0x0 1131 #define MMSCH_INTR_STATUS__INTR_MASK 0x00001FFFL 1132 //MMSCH_VF_VMID 1133 #define MMSCH_VF_VMID__VF_CTX_VMID__SHIFT 0x0 1134 #define MMSCH_VF_VMID__VF_GPCOM_VMID__SHIFT 0x5 1135 #define MMSCH_VF_VMID__VF_CTX_VMID_MASK 0x0000001FL 1136 #define MMSCH_VF_VMID__VF_GPCOM_VMID_MASK 0x000003E0L 1137 //MMSCH_VF_CTX_ADDR_LO 1138 #define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO__SHIFT 0x6 1139 #define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO_MASK 0xFFFFFFC0L 1140 //MMSCH_VF_CTX_ADDR_HI 1141 #define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI__SHIFT 0x0 1142 #define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI_MASK 0xFFFFFFFFL 1143 //MMSCH_VF_CTX_SIZE 1144 #define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE__SHIFT 0x0 1145 #define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE_MASK 0xFFFFFFFFL 1146 //MMSCH_VF_GPCOM_ADDR_LO 1147 #define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO__SHIFT 0x6 1148 #define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO_MASK 0xFFFFFFC0L 1149 //MMSCH_VF_GPCOM_ADDR_HI 1150 #define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI__SHIFT 0x0 1151 #define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI_MASK 0xFFFFFFFFL 1152 //MMSCH_VF_GPCOM_SIZE 1153 #define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE__SHIFT 0x0 1154 #define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE_MASK 0xFFFFFFFFL 1155 //MMSCH_VF_MAILBOX_HOST 1156 #define MMSCH_VF_MAILBOX_HOST__DATA__SHIFT 0x0 1157 #define MMSCH_VF_MAILBOX_HOST__DATA_MASK 0xFFFFFFFFL 1158 //MMSCH_VF_MAILBOX_RESP 1159 #define MMSCH_VF_MAILBOX_RESP__RESP__SHIFT 0x0 1160 #define MMSCH_VF_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL 1161 //MMSCH_VF_MAILBOX_0 1162 #define MMSCH_VF_MAILBOX_0__DATA__SHIFT 0x0 1163 #define MMSCH_VF_MAILBOX_0__DATA_MASK 0xFFFFFFFFL 1164 //MMSCH_VF_MAILBOX_0_RESP 1165 #define MMSCH_VF_MAILBOX_0_RESP__RESP__SHIFT 0x0 1166 #define MMSCH_VF_MAILBOX_0_RESP__RESP_MASK 0xFFFFFFFFL 1167 //MMSCH_VF_MAILBOX_1 1168 #define MMSCH_VF_MAILBOX_1__DATA__SHIFT 0x0 1169 #define MMSCH_VF_MAILBOX_1__DATA_MASK 0xFFFFFFFFL 1170 //MMSCH_VF_MAILBOX_1_RESP 1171 #define MMSCH_VF_MAILBOX_1_RESP__RESP__SHIFT 0x0 1172 #define MMSCH_VF_MAILBOX_1_RESP__RESP_MASK 0xFFFFFFFFL 1173 //MMSCH_CNTL 1174 #define MMSCH_CNTL__CLK_EN__SHIFT 0x0 1175 #define MMSCH_CNTL__ED_ENABLE__SHIFT 0x1 1176 #define MMSCH_CNTL__MMSCH_IRQ_ERR__SHIFT 0x5 1177 #define MMSCH_CNTL__MMSCH_NACK_INTR_EN__SHIFT 0x9 1178 #define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN__SHIFT 0xa 1179 #define MMSCH_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 1180 #define MMSCH_CNTL__TIMEOUT_DIS__SHIFT 0x1c 1181 #define MMSCH_CNTL__CLK_EN_MASK 0x00000001L 1182 #define MMSCH_CNTL__ED_ENABLE_MASK 0x00000002L 1183 #define MMSCH_CNTL__MMSCH_IRQ_ERR_MASK 0x000001E0L 1184 #define MMSCH_CNTL__MMSCH_NACK_INTR_EN_MASK 0x00000200L 1185 #define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN_MASK 0x00000400L 1186 #define MMSCH_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L 1187 #define MMSCH_CNTL__TIMEOUT_DIS_MASK 0x10000000L 1188 //MMSCH_NONCACHE_OFFSET0 1189 #define MMSCH_NONCACHE_OFFSET0__OFFSET__SHIFT 0x0 1190 #define MMSCH_NONCACHE_OFFSET0__OFFSET_MASK 0x0FFFFFFFL 1191 //MMSCH_NONCACHE_SIZE0 1192 #define MMSCH_NONCACHE_SIZE0__SIZE__SHIFT 0x0 1193 #define MMSCH_NONCACHE_SIZE0__SIZE_MASK 0x00FFFFFFL 1194 //MMSCH_NONCACHE_OFFSET1 1195 #define MMSCH_NONCACHE_OFFSET1__OFFSET__SHIFT 0x0 1196 #define MMSCH_NONCACHE_OFFSET1__OFFSET_MASK 0x0FFFFFFFL 1197 //MMSCH_NONCACHE_SIZE1 1198 #define MMSCH_NONCACHE_SIZE1__SIZE__SHIFT 0x0 1199 #define MMSCH_NONCACHE_SIZE1__SIZE_MASK 0x00FFFFFFL 1200 //MMSCH_PROC_STATE1 1201 #define MMSCH_PROC_STATE1__PC__SHIFT 0x0 1202 #define MMSCH_PROC_STATE1__PC_MASK 0xFFFFFFFFL 1203 //MMSCH_LAST_MC_ADDR 1204 #define MMSCH_LAST_MC_ADDR__MC_ADDR__SHIFT 0x0 1205 #define MMSCH_LAST_MC_ADDR__RW__SHIFT 0x1f 1206 #define MMSCH_LAST_MC_ADDR__MC_ADDR_MASK 0x0FFFFFFFL 1207 #define MMSCH_LAST_MC_ADDR__RW_MASK 0x80000000L 1208 //MMSCH_LAST_MEM_ACCESS_HI 1209 #define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD__SHIFT 0x0 1210 #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR__SHIFT 0x8 1211 #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR__SHIFT 0xc 1212 #define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD_MASK 0x00000007L 1213 #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR_MASK 0x00000700L 1214 #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR_MASK 0x00007000L 1215 //MMSCH_LAST_MEM_ACCESS_LO 1216 #define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR__SHIFT 0x0 1217 #define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR_MASK 0xFFFFFFFFL 1218 //MMSCH_SCRATCH_0 1219 #define MMSCH_SCRATCH_0__SCRATCH_0__SHIFT 0x0 1220 #define MMSCH_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL 1221 //MMSCH_SCRATCH_1 1222 #define MMSCH_SCRATCH_1__SCRATCH_1__SHIFT 0x0 1223 #define MMSCH_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL 1224 //MMSCH_GPUIOV_SCH_BLOCK_0 1225 #define MMSCH_GPUIOV_SCH_BLOCK_0__ID__SHIFT 0x0 1226 #define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION__SHIFT 0x4 1227 #define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE__SHIFT 0x8 1228 #define MMSCH_GPUIOV_SCH_BLOCK_0__ID_MASK 0x0000000FL 1229 #define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION_MASK 0x000000F0L 1230 #define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE_MASK 0x0000FF00L 1231 //MMSCH_GPUIOV_CMD_CONTROL_0 1232 #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE__SHIFT 0x0 1233 #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE__SHIFT 0x4 1234 #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN__SHIFT 0x5 1235 #define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN__SHIFT 0x6 1236 #define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID__SHIFT 0x8 1237 #define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID__SHIFT 0x10 1238 #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE_MASK 0x0000000FL 1239 #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_MASK 0x00000010L 1240 #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN_MASK 0x00000020L 1241 #define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN_MASK 0x00000040L 1242 #define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID_MASK 0x0000FF00L 1243 #define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID_MASK 0x00FF0000L 1244 //MMSCH_GPUIOV_CMD_STATUS_0 1245 #define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS__SHIFT 0x0 1246 #define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS_MASK 0x0000000FL 1247 //MMSCH_GPUIOV_VM_BUSY_STATUS_0 1248 #define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY__SHIFT 0x0 1249 #define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY_MASK 0xFFFFFFFFL 1250 //MMSCH_GPUIOV_ACTIVE_FCNS_0 1251 #define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS__SHIFT 0x0 1252 #define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS_MASK 0xFFFFFFFFL 1253 //MMSCH_GPUIOV_ACTIVE_FCN_ID_0 1254 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID__SHIFT 0x0 1255 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS__SHIFT 0x8 1256 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_MASK 0x000000FFL 1257 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS_MASK 0x00000F00L 1258 //MMSCH_GPUIOV_DW6_0 1259 #define MMSCH_GPUIOV_DW6_0__DATA__SHIFT 0x0 1260 #define MMSCH_GPUIOV_DW6_0__DATA_MASK 0xFFFFFFFFL 1261 //MMSCH_GPUIOV_DW7_0 1262 #define MMSCH_GPUIOV_DW7_0__DATA__SHIFT 0x0 1263 #define MMSCH_GPUIOV_DW7_0__DATA_MASK 0xFFFFFFFFL 1264 //MMSCH_GPUIOV_DW8_0 1265 #define MMSCH_GPUIOV_DW8_0__DATA__SHIFT 0x0 1266 #define MMSCH_GPUIOV_DW8_0__DATA_MASK 0xFFFFFFFFL 1267 //MMSCH_GPUIOV_SCH_BLOCK_1 1268 #define MMSCH_GPUIOV_SCH_BLOCK_1__ID__SHIFT 0x0 1269 #define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION__SHIFT 0x4 1270 #define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE__SHIFT 0x8 1271 #define MMSCH_GPUIOV_SCH_BLOCK_1__ID_MASK 0x0000000FL 1272 #define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION_MASK 0x000000F0L 1273 #define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE_MASK 0x0000FF00L 1274 //MMSCH_GPUIOV_CMD_CONTROL_1 1275 #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE__SHIFT 0x0 1276 #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE__SHIFT 0x4 1277 #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN__SHIFT 0x5 1278 #define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN__SHIFT 0x6 1279 #define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID__SHIFT 0x8 1280 #define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID__SHIFT 0x10 1281 #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE_MASK 0x0000000FL 1282 #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_MASK 0x00000010L 1283 #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L 1284 #define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN_MASK 0x00000040L 1285 #define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID_MASK 0x0000FF00L 1286 #define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID_MASK 0x00FF0000L 1287 //MMSCH_GPUIOV_CMD_STATUS_1 1288 #define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS__SHIFT 0x0 1289 #define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS_MASK 0x0000000FL 1290 //MMSCH_GPUIOV_VM_BUSY_STATUS_1 1291 #define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY__SHIFT 0x0 1292 #define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY_MASK 0xFFFFFFFFL 1293 //MMSCH_GPUIOV_ACTIVE_FCNS_1 1294 #define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS__SHIFT 0x0 1295 #define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS_MASK 0xFFFFFFFFL 1296 //MMSCH_GPUIOV_ACTIVE_FCN_ID_1 1297 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID__SHIFT 0x0 1298 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS__SHIFT 0x8 1299 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_MASK 0x000000FFL 1300 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS_MASK 0x00000F00L 1301 //MMSCH_GPUIOV_DW6_1 1302 #define MMSCH_GPUIOV_DW6_1__DATA__SHIFT 0x0 1303 #define MMSCH_GPUIOV_DW6_1__DATA_MASK 0xFFFFFFFFL 1304 //MMSCH_GPUIOV_DW7_1 1305 #define MMSCH_GPUIOV_DW7_1__DATA__SHIFT 0x0 1306 #define MMSCH_GPUIOV_DW7_1__DATA_MASK 0xFFFFFFFFL 1307 //MMSCH_GPUIOV_DW8_1 1308 #define MMSCH_GPUIOV_DW8_1__DATA__SHIFT 0x0 1309 #define MMSCH_GPUIOV_DW8_1__DATA_MASK 0xFFFFFFFFL 1310 //MMSCH_GPUIOV_CNTXT 1311 #define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE__SHIFT 0x0 1312 #define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION__SHIFT 0x7 1313 #define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET__SHIFT 0xa 1314 #define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE_MASK 0x0000007FL 1315 #define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION_MASK 0x00000080L 1316 #define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET_MASK 0xFFFFFC00L 1317 //MMSCH_SCRATCH_2 1318 #define MMSCH_SCRATCH_2__SCRATCH_2__SHIFT 0x0 1319 #define MMSCH_SCRATCH_2__SCRATCH_2_MASK 0xFFFFFFFFL 1320 //MMSCH_SCRATCH_3 1321 #define MMSCH_SCRATCH_3__SCRATCH_3__SHIFT 0x0 1322 #define MMSCH_SCRATCH_3__SCRATCH_3_MASK 0xFFFFFFFFL 1323 //MMSCH_SCRATCH_4 1324 #define MMSCH_SCRATCH_4__SCRATCH_4__SHIFT 0x0 1325 #define MMSCH_SCRATCH_4__SCRATCH_4_MASK 0xFFFFFFFFL 1326 //MMSCH_SCRATCH_5 1327 #define MMSCH_SCRATCH_5__SCRATCH_5__SHIFT 0x0 1328 #define MMSCH_SCRATCH_5__SCRATCH_5_MASK 0xFFFFFFFFL 1329 //MMSCH_SCRATCH_6 1330 #define MMSCH_SCRATCH_6__SCRATCH_6__SHIFT 0x0 1331 #define MMSCH_SCRATCH_6__SCRATCH_6_MASK 0xFFFFFFFFL 1332 //MMSCH_SCRATCH_7 1333 #define MMSCH_SCRATCH_7__SCRATCH_7__SHIFT 0x0 1334 #define MMSCH_SCRATCH_7__SCRATCH_7_MASK 0xFFFFFFFFL 1335 //MMSCH_VFID_FIFO_HEAD_0 1336 #define MMSCH_VFID_FIFO_HEAD_0__HEAD__SHIFT 0x0 1337 #define MMSCH_VFID_FIFO_HEAD_0__HEAD_MASK 0x0000003FL 1338 //MMSCH_VFID_FIFO_TAIL_0 1339 #define MMSCH_VFID_FIFO_TAIL_0__TAIL__SHIFT 0x0 1340 #define MMSCH_VFID_FIFO_TAIL_0__TAIL_MASK 0x0000003FL 1341 //MMSCH_VFID_FIFO_HEAD_1 1342 #define MMSCH_VFID_FIFO_HEAD_1__HEAD__SHIFT 0x0 1343 #define MMSCH_VFID_FIFO_HEAD_1__HEAD_MASK 0x0000003FL 1344 //MMSCH_VFID_FIFO_TAIL_1 1345 #define MMSCH_VFID_FIFO_TAIL_1__TAIL__SHIFT 0x0 1346 #define MMSCH_VFID_FIFO_TAIL_1__TAIL_MASK 0x0000003FL 1347 //MMSCH_NACK_STATUS 1348 #define MMSCH_NACK_STATUS__WR_NACK_STATUS__SHIFT 0x0 1349 #define MMSCH_NACK_STATUS__RD_NACK_STATUS__SHIFT 0x2 1350 #define MMSCH_NACK_STATUS__WR_NACK_STATUS_MASK 0x00000003L 1351 #define MMSCH_NACK_STATUS__RD_NACK_STATUS_MASK 0x0000000CL 1352 //MMSCH_VF_MAILBOX0_DATA 1353 #define MMSCH_VF_MAILBOX0_DATA__DATA__SHIFT 0x0 1354 #define MMSCH_VF_MAILBOX0_DATA__DATA_MASK 0xFFFFFFFFL 1355 //MMSCH_VF_MAILBOX1_DATA 1356 #define MMSCH_VF_MAILBOX1_DATA__DATA__SHIFT 0x0 1357 #define MMSCH_VF_MAILBOX1_DATA__DATA_MASK 0xFFFFFFFFL 1358 //MMSCH_GPUIOV_SCH_BLOCK_IP_0 1359 #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID__SHIFT 0x0 1360 #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION__SHIFT 0x4 1361 #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE__SHIFT 0x8 1362 #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID_MASK 0x0000000FL 1363 #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION_MASK 0x000000F0L 1364 #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE_MASK 0x0000FF00L 1365 //MMSCH_GPUIOV_CMD_STATUS_IP_0 1366 #define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS__SHIFT 0x0 1367 #define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS_MASK 0x0000000FL 1368 //MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0 1369 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID__SHIFT 0x0 1370 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS__SHIFT 0x8 1371 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_MASK 0x000000FFL 1372 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS_MASK 0x00000F00L 1373 //MMSCH_GPUIOV_SCH_BLOCK_IP_1 1374 #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID__SHIFT 0x0 1375 #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION__SHIFT 0x4 1376 #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE__SHIFT 0x8 1377 #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID_MASK 0x0000000FL 1378 #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION_MASK 0x000000F0L 1379 #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE_MASK 0x0000FF00L 1380 //MMSCH_GPUIOV_CMD_STATUS_IP_1 1381 #define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS__SHIFT 0x0 1382 #define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS_MASK 0x0000000FL 1383 //MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1 1384 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID__SHIFT 0x0 1385 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS__SHIFT 0x8 1386 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_MASK 0x000000FFL 1387 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS_MASK 0x00000F00L 1388 //MMSCH_GPUIOV_CNTXT_IP 1389 #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE__SHIFT 0x0 1390 #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION__SHIFT 0x7 1391 #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE_MASK 0x0000007FL 1392 #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION_MASK 0x00000080L 1393 //MMSCH_GPUIOV_SCH_BLOCK_2 1394 #define MMSCH_GPUIOV_SCH_BLOCK_2__ID__SHIFT 0x0 1395 #define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION__SHIFT 0x4 1396 #define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE__SHIFT 0x8 1397 #define MMSCH_GPUIOV_SCH_BLOCK_2__ID_MASK 0x0000000FL 1398 #define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION_MASK 0x000000F0L 1399 #define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE_MASK 0x0000FF00L 1400 //MMSCH_GPUIOV_CMD_CONTROL_2 1401 #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE__SHIFT 0x0 1402 #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE__SHIFT 0x4 1403 #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN__SHIFT 0x5 1404 #define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN__SHIFT 0x6 1405 #define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID__SHIFT 0x8 1406 #define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID__SHIFT 0x10 1407 #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE_MASK 0x0000000FL 1408 #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_MASK 0x00000010L 1409 #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN_MASK 0x00000020L 1410 #define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN_MASK 0x00000040L 1411 #define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID_MASK 0x0000FF00L 1412 #define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID_MASK 0x00FF0000L 1413 //MMSCH_GPUIOV_CMD_STATUS_2 1414 #define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS__SHIFT 0x0 1415 #define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS_MASK 0x0000000FL 1416 //MMSCH_GPUIOV_VM_BUSY_STATUS_2 1417 #define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY__SHIFT 0x0 1418 #define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY_MASK 0xFFFFFFFFL 1419 //MMSCH_GPUIOV_ACTIVE_FCNS_2 1420 #define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS__SHIFT 0x0 1421 #define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS_MASK 0xFFFFFFFFL 1422 //MMSCH_GPUIOV_ACTIVE_FCN_ID_2 1423 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID__SHIFT 0x0 1424 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS__SHIFT 0x8 1425 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_MASK 0x000000FFL 1426 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS_MASK 0x00000F00L 1427 //MMSCH_GPUIOV_DW6_2 1428 #define MMSCH_GPUIOV_DW6_2__DATA__SHIFT 0x0 1429 #define MMSCH_GPUIOV_DW6_2__DATA_MASK 0xFFFFFFFFL 1430 //MMSCH_GPUIOV_DW7_2 1431 #define MMSCH_GPUIOV_DW7_2__DATA__SHIFT 0x0 1432 #define MMSCH_GPUIOV_DW7_2__DATA_MASK 0xFFFFFFFFL 1433 //MMSCH_GPUIOV_DW8_2 1434 #define MMSCH_GPUIOV_DW8_2__DATA__SHIFT 0x0 1435 #define MMSCH_GPUIOV_DW8_2__DATA_MASK 0xFFFFFFFFL 1436 //MMSCH_GPUIOV_SCH_BLOCK_IP_2 1437 #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID__SHIFT 0x0 1438 #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION__SHIFT 0x4 1439 #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE__SHIFT 0x8 1440 #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID_MASK 0x0000000FL 1441 #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION_MASK 0x000000F0L 1442 #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE_MASK 0x0000FF00L 1443 //MMSCH_GPUIOV_CMD_STATUS_IP_2 1444 #define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS__SHIFT 0x0 1445 #define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS_MASK 0x0000000FL 1446 //MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2 1447 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID__SHIFT 0x0 1448 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS__SHIFT 0x8 1449 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_MASK 0x000000FFL 1450 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS_MASK 0x00000F00L 1451 //MMSCH_VFID_FIFO_HEAD_2 1452 #define MMSCH_VFID_FIFO_HEAD_2__HEAD__SHIFT 0x0 1453 #define MMSCH_VFID_FIFO_HEAD_2__HEAD_MASK 0x0000003FL 1454 //MMSCH_VFID_FIFO_TAIL_2 1455 #define MMSCH_VFID_FIFO_TAIL_2__TAIL__SHIFT 0x0 1456 #define MMSCH_VFID_FIFO_TAIL_2__TAIL_MASK 0x0000003FL 1457 //MMSCH_VM_BUSY_STATUS_0 1458 #define MMSCH_VM_BUSY_STATUS_0__BUSY__SHIFT 0x0 1459 #define MMSCH_VM_BUSY_STATUS_0__BUSY_MASK 0xFFFFFFFFL 1460 //MMSCH_VM_BUSY_STATUS_1 1461 #define MMSCH_VM_BUSY_STATUS_1__BUSY__SHIFT 0x0 1462 #define MMSCH_VM_BUSY_STATUS_1__BUSY_MASK 0xFFFFFFFFL 1463 //MMSCH_VM_BUSY_STATUS_2 1464 #define MMSCH_VM_BUSY_STATUS_2__BUSY__SHIFT 0x0 1465 #define MMSCH_VM_BUSY_STATUS_2__BUSY_MASK 0xFFFFFFFFL 1466 1467 1468 // addressBlock: uvd0_uvd_jmi_dec 1469 //UVD_JADP_MCIF_URGENT_CTRL 1470 #define UVD_JADP_MCIF_URGENT_CTRL__WR_WATERMARK__SHIFT 0x0 1471 #define UVD_JADP_MCIF_URGENT_CTRL__RD_WATERMARK__SHIFT 0x6 1472 #define UVD_JADP_MCIF_URGENT_CTRL__WR_RD_URGENT_TIMER__SHIFT 0xb 1473 #define UVD_JADP_MCIF_URGENT_CTRL__WR_URGENT_PROG_STEP__SHIFT 0x11 1474 #define UVD_JADP_MCIF_URGENT_CTRL__RD_URGENT_PROG_STEP__SHIFT 0x15 1475 #define UVD_JADP_MCIF_URGENT_CTRL__WR_QOS_EN__SHIFT 0x19 1476 #define UVD_JADP_MCIF_URGENT_CTRL__RD_QOS_EN__SHIFT 0x1a 1477 #define UVD_JADP_MCIF_URGENT_CTRL__WR_WATERMARK_MASK 0x0000003FL 1478 #define UVD_JADP_MCIF_URGENT_CTRL__RD_WATERMARK_MASK 0x000007C0L 1479 #define UVD_JADP_MCIF_URGENT_CTRL__WR_RD_URGENT_TIMER_MASK 0x0001F800L 1480 #define UVD_JADP_MCIF_URGENT_CTRL__WR_URGENT_PROG_STEP_MASK 0x001E0000L 1481 #define UVD_JADP_MCIF_URGENT_CTRL__RD_URGENT_PROG_STEP_MASK 0x01E00000L 1482 #define UVD_JADP_MCIF_URGENT_CTRL__WR_QOS_EN_MASK 0x02000000L 1483 #define UVD_JADP_MCIF_URGENT_CTRL__RD_QOS_EN_MASK 0x04000000L 1484 //UVD_JMI_URGENT_CTRL 1485 #define UVD_JMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT 0x0 1486 #define UVD_JMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT 0x4 1487 #define UVD_JMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT 0x10 1488 #define UVD_JMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0x14 1489 #define UVD_JMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK 0x00000001L 1490 #define UVD_JMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK 0x000000F0L 1491 #define UVD_JMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK 0x00010000L 1492 #define UVD_JMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK 0x00F00000L 1493 //UVD_JPEG_DEC_PF_CTRL 1494 #define UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS__SHIFT 0x0 1495 #define UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING__SHIFT 0x1 1496 #define UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS_MASK 0x00000001L 1497 #define UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING_MASK 0x00000002L 1498 //UVD_JPEG_ENC_PF_CTRL 1499 #define UVD_JPEG_ENC_PF_CTRL__ENC_PF_HANDLING_DIS__SHIFT 0x0 1500 #define UVD_JPEG_ENC_PF_CTRL__ENC_PF_SW_GATING__SHIFT 0x1 1501 #define UVD_JPEG_ENC_PF_CTRL__ENC_PF_HANDLING_DIS_MASK 0x00000001L 1502 #define UVD_JPEG_ENC_PF_CTRL__ENC_PF_SW_GATING_MASK 0x00000002L 1503 //UVD_JMI_CTRL 1504 #define UVD_JMI_CTRL__STALL_MC_ARB__SHIFT 0x0 1505 #define UVD_JMI_CTRL__MASK_MC_URGENT__SHIFT 0x1 1506 #define UVD_JMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x2 1507 #define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER__SHIFT 0x8 1508 #define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER__SHIFT 0x10 1509 #define UVD_JMI_CTRL__CRC_RESET__SHIFT 0x18 1510 #define UVD_JMI_CTRL__CRC_SEL__SHIFT 0x19 1511 #define UVD_JMI_CTRL__STALL_MC_ARB_MASK 0x00000001L 1512 #define UVD_JMI_CTRL__MASK_MC_URGENT_MASK 0x00000002L 1513 #define UVD_JMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000004L 1514 #define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER_MASK 0x0000FF00L 1515 #define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER_MASK 0x00FF0000L 1516 #define UVD_JMI_CTRL__CRC_RESET_MASK 0x01000000L 1517 #define UVD_JMI_CTRL__CRC_SEL_MASK 0x1E000000L 1518 //UVD_LMI_JRBC_CTRL 1519 #define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 1520 #define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 1521 #define UVD_LMI_JRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 1522 #define UVD_LMI_JRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 1523 #define UVD_LMI_JRBC_CTRL__RD_SWAP__SHIFT 0x14 1524 #define UVD_LMI_JRBC_CTRL__WR_SWAP__SHIFT 0x16 1525 #define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 1526 #define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 1527 #define UVD_LMI_JRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L 1528 #define UVD_LMI_JRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L 1529 #define UVD_LMI_JRBC_CTRL__RD_SWAP_MASK 0x00300000L 1530 #define UVD_LMI_JRBC_CTRL__WR_SWAP_MASK 0x00C00000L 1531 //UVD_LMI_JPEG_CTRL 1532 #define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 1533 #define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 1534 #define UVD_LMI_JPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 1535 #define UVD_LMI_JPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 1536 #define UVD_LMI_JPEG_CTRL__RD_SWAP__SHIFT 0x14 1537 #define UVD_LMI_JPEG_CTRL__WR_SWAP__SHIFT 0x16 1538 #define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 1539 #define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 1540 #define UVD_LMI_JPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L 1541 #define UVD_LMI_JPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L 1542 #define UVD_LMI_JPEG_CTRL__RD_SWAP_MASK 0x00300000L 1543 #define UVD_LMI_JPEG_CTRL__WR_SWAP_MASK 0x00C00000L 1544 //UVD_JMI_EJRBC_CTRL 1545 #define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 1546 #define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 1547 #define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 1548 #define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 1549 #define UVD_JMI_EJRBC_CTRL__RD_SWAP__SHIFT 0x14 1550 #define UVD_JMI_EJRBC_CTRL__WR_SWAP__SHIFT 0x16 1551 #define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 1552 #define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 1553 #define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L 1554 #define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L 1555 #define UVD_JMI_EJRBC_CTRL__RD_SWAP_MASK 0x00300000L 1556 #define UVD_JMI_EJRBC_CTRL__WR_SWAP_MASK 0x00C00000L 1557 //UVD_LMI_EJPEG_CTRL 1558 #define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 1559 #define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 1560 #define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 1561 #define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 1562 #define UVD_LMI_EJPEG_CTRL__RD_SWAP__SHIFT 0x14 1563 #define UVD_LMI_EJPEG_CTRL__WR_SWAP__SHIFT 0x16 1564 #define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 1565 #define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 1566 #define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L 1567 #define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L 1568 #define UVD_LMI_EJPEG_CTRL__RD_SWAP_MASK 0x00300000L 1569 #define UVD_LMI_EJPEG_CTRL__WR_SWAP_MASK 0x00C00000L 1570 //UVD_JMI_SCALER_CTRL 1571 #define UVD_JMI_SCALER_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 1572 #define UVD_JMI_SCALER_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 1573 #define UVD_JMI_SCALER_CTRL__RD_MAX_BURST__SHIFT 0x4 1574 #define UVD_JMI_SCALER_CTRL__WR_MAX_BURST__SHIFT 0x8 1575 #define UVD_JMI_SCALER_CTRL__RD_SWAP__SHIFT 0x14 1576 #define UVD_JMI_SCALER_CTRL__WR_SWAP__SHIFT 0x16 1577 #define UVD_JMI_SCALER_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 1578 #define UVD_JMI_SCALER_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 1579 #define UVD_JMI_SCALER_CTRL__RD_MAX_BURST_MASK 0x000000F0L 1580 #define UVD_JMI_SCALER_CTRL__WR_MAX_BURST_MASK 0x00000F00L 1581 #define UVD_JMI_SCALER_CTRL__RD_SWAP_MASK 0x00300000L 1582 #define UVD_JMI_SCALER_CTRL__WR_SWAP_MASK 0x00C00000L 1583 //JPEG_LMI_DROP 1584 #define JPEG_LMI_DROP__JPEG_WR_DROP__SHIFT 0x0 1585 #define JPEG_LMI_DROP__JRBC_WR_DROP__SHIFT 0x1 1586 #define JPEG_LMI_DROP__JPEG_RD_DROP__SHIFT 0x2 1587 #define JPEG_LMI_DROP__JRBC_RD_DROP__SHIFT 0x3 1588 #define JPEG_LMI_DROP__JPEG_WR_DROP_MASK 0x00000001L 1589 #define JPEG_LMI_DROP__JRBC_WR_DROP_MASK 0x00000002L 1590 #define JPEG_LMI_DROP__JPEG_RD_DROP_MASK 0x00000004L 1591 #define JPEG_LMI_DROP__JRBC_RD_DROP_MASK 0x00000008L 1592 //UVD_JMI_EJPEG_DROP 1593 #define UVD_JMI_EJPEG_DROP__EJRBC_RD_DROP__SHIFT 0x0 1594 #define UVD_JMI_EJPEG_DROP__EJRBC_WR_DROP__SHIFT 0x1 1595 #define UVD_JMI_EJPEG_DROP__EJPEG_RD_DROP__SHIFT 0x2 1596 #define UVD_JMI_EJPEG_DROP__EJPEG_WR_DROP__SHIFT 0x3 1597 #define UVD_JMI_EJPEG_DROP__SCALAR_RD_DROP__SHIFT 0x4 1598 #define UVD_JMI_EJPEG_DROP__SCALAR_WR_DROP__SHIFT 0x5 1599 #define UVD_JMI_EJPEG_DROP__EJRBC_RD_DROP_MASK 0x00000001L 1600 #define UVD_JMI_EJPEG_DROP__EJRBC_WR_DROP_MASK 0x00000002L 1601 #define UVD_JMI_EJPEG_DROP__EJPEG_RD_DROP_MASK 0x00000004L 1602 #define UVD_JMI_EJPEG_DROP__EJPEG_WR_DROP_MASK 0x00000008L 1603 #define UVD_JMI_EJPEG_DROP__SCALAR_RD_DROP_MASK 0x00000010L 1604 #define UVD_JMI_EJPEG_DROP__SCALAR_WR_DROP_MASK 0x00000020L 1605 //JPEG_MEMCHECK_CLAMPING 1606 #define JPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN__SHIFT 0xd 1607 #define JPEG_MEMCHECK_CLAMPING__JPEG2_WR_CLAMPING_EN__SHIFT 0xe 1608 #define JPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN__SHIFT 0x16 1609 #define JPEG_MEMCHECK_CLAMPING__JPEG2_RD_CLAMPING_EN__SHIFT 0x17 1610 #define JPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN__SHIFT 0x19 1611 #define JPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN__SHIFT 0x1a 1612 #define JPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN__SHIFT 0x1f 1613 #define JPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN_MASK 0x00002000L 1614 #define JPEG_MEMCHECK_CLAMPING__JPEG2_WR_CLAMPING_EN_MASK 0x00004000L 1615 #define JPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN_MASK 0x00400000L 1616 #define JPEG_MEMCHECK_CLAMPING__JPEG2_RD_CLAMPING_EN_MASK 0x00800000L 1617 #define JPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN_MASK 0x02000000L 1618 #define JPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN_MASK 0x04000000L 1619 #define JPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN_MASK 0x80000000L 1620 //UVD_JMI_EJPEG_MEMCHECK_CLAMPING 1621 #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN__SHIFT 0x0 1622 #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN__SHIFT 0x1 1623 #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN__SHIFT 0x2 1624 #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN__SHIFT 0x3 1625 #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_RD_CLAMPING_EN__SHIFT 0x4 1626 #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_WR_CLAMPING_EN__SHIFT 0x5 1627 #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN__SHIFT 0x1f 1628 #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN_MASK 0x00000001L 1629 #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN_MASK 0x00000002L 1630 #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN_MASK 0x00000004L 1631 #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN_MASK 0x00000008L 1632 #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_RD_CLAMPING_EN_MASK 0x00000010L 1633 #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_WR_CLAMPING_EN_MASK 0x00000020L 1634 #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN_MASK 0x80000000L 1635 //UVD_LMI_JRBC_IB_VMID 1636 #define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 1637 #define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 1638 #define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 1639 #define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL 1640 #define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L 1641 #define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1642 //UVD_LMI_JRBC_RB_VMID 1643 #define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 1644 #define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 1645 #define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 1646 #define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL 1647 #define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L 1648 #define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1649 //UVD_LMI_JPEG_VMID 1650 #define UVD_LMI_JPEG_VMID__JPEG_RD_VMID__SHIFT 0x0 1651 #define UVD_LMI_JPEG_VMID__JPEG_WR_VMID__SHIFT 0x4 1652 #define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID__SHIFT 0x8 1653 #define UVD_LMI_JPEG_VMID__JPEG_RD_VMID_MASK 0x0000000FL 1654 #define UVD_LMI_JPEG_VMID__JPEG_WR_VMID_MASK 0x000000F0L 1655 #define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID_MASK 0x00000F00L 1656 //UVD_JMI_ENC_JRBC_IB_VMID 1657 #define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 1658 #define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 1659 #define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 1660 #define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL 1661 #define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L 1662 #define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1663 //UVD_JMI_ENC_JRBC_RB_VMID 1664 #define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 1665 #define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 1666 #define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 1667 #define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL 1668 #define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L 1669 #define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1670 //UVD_JMI_ENC_JPEG_VMID 1671 #define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID__SHIFT 0x0 1672 #define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID__SHIFT 0x5 1673 #define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID__SHIFT 0xa 1674 #define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID__SHIFT 0xf 1675 #define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID__SHIFT 0x13 1676 #define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID__SHIFT 0x17 1677 #define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID_MASK 0x0000000FL 1678 #define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID_MASK 0x000001E0L 1679 #define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID_MASK 0x00003C00L 1680 #define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID_MASK 0x00078000L 1681 #define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID_MASK 0x00780000L 1682 #define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID_MASK 0x07800000L 1683 //UVD_JMI_EJPEG_RAS_CNTL 1684 #define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_IH_EN__SHIFT 0x0 1685 #define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_PMI_EN__SHIFT 0x1 1686 #define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_REARM__SHIFT 0x2 1687 #define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_STALL_EN__SHIFT 0x3 1688 #define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_READY__SHIFT 0x4 1689 #define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_IH_EN_MASK 0x00000001L 1690 #define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_PMI_EN_MASK 0x00000002L 1691 #define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_REARM_MASK 0x00000004L 1692 #define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_STALL_EN_MASK 0x00000008L 1693 #define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_READY_MASK 0x00000010L 1694 //JPEG_MEMCHECK_SAFE_ADDR 1695 #define JPEG_MEMCHECK_SAFE_ADDR__MEMCHECK_SAFE_ADDR__SHIFT 0x0 1696 #define JPEG_MEMCHECK_SAFE_ADDR__MEMCHECK_SAFE_ADDR_MASK 0xFFFFFFFFL 1697 //JPEG_MEMCHECK_SAFE_ADDR_64BIT 1698 #define JPEG_MEMCHECK_SAFE_ADDR_64BIT__MEMCHECK_SAFE_ADDR_64BIT__SHIFT 0x0 1699 #define JPEG_MEMCHECK_SAFE_ADDR_64BIT__MEMCHECK_SAFE_ADDR_64BIT_MASK 0xFFFFFFFFL 1700 //UVD_JMI_LAT_CTRL 1701 #define UVD_JMI_LAT_CTRL__SCALE__SHIFT 0x0 1702 #define UVD_JMI_LAT_CTRL__MAX_START__SHIFT 0x8 1703 #define UVD_JMI_LAT_CTRL__MIN_START__SHIFT 0x9 1704 #define UVD_JMI_LAT_CTRL__AVG_START__SHIFT 0xa 1705 #define UVD_JMI_LAT_CTRL__PERFMON_SYNC__SHIFT 0xb 1706 #define UVD_JMI_LAT_CTRL__SKIP__SHIFT 0x10 1707 #define UVD_JMI_LAT_CTRL__SCALE_MASK 0x000000FFL 1708 #define UVD_JMI_LAT_CTRL__MAX_START_MASK 0x00000100L 1709 #define UVD_JMI_LAT_CTRL__MIN_START_MASK 0x00000200L 1710 #define UVD_JMI_LAT_CTRL__AVG_START_MASK 0x00000400L 1711 #define UVD_JMI_LAT_CTRL__PERFMON_SYNC_MASK 0x00000800L 1712 #define UVD_JMI_LAT_CTRL__SKIP_MASK 0x000F0000L 1713 //UVD_JMI_LAT_CNTR 1714 #define UVD_JMI_LAT_CNTR__MAX_LAT__SHIFT 0x0 1715 #define UVD_JMI_LAT_CNTR__MIN_LAT__SHIFT 0x8 1716 #define UVD_JMI_LAT_CNTR__MAX_LAT_MASK 0x000000FFL 1717 #define UVD_JMI_LAT_CNTR__MIN_LAT_MASK 0x0000FF00L 1718 //UVD_JMI_AVG_LAT_CNTR 1719 #define UVD_JMI_AVG_LAT_CNTR__ENV_LOW__SHIFT 0x0 1720 #define UVD_JMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT 0x8 1721 #define UVD_JMI_AVG_LAT_CNTR__ENV_HIT__SHIFT 0x10 1722 #define UVD_JMI_AVG_LAT_CNTR__ENV_LOW_MASK 0x000000FFL 1723 #define UVD_JMI_AVG_LAT_CNTR__ENV_HIGH_MASK 0x0000FF00L 1724 #define UVD_JMI_AVG_LAT_CNTR__ENV_HIT_MASK 0xFFFF0000L 1725 //UVD_JMI_PERFMON_CTRL 1726 #define UVD_JMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0 1727 #define UVD_JMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8 1728 #define UVD_JMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L 1729 #define UVD_JMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00000F00L 1730 //UVD_JMI_PERFMON_COUNT_LO 1731 #define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0 1732 #define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL 1733 //UVD_JMI_PERFMON_COUNT_HI 1734 #define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0 1735 #define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL 1736 //UVD_JMI_CLEAN_STATUS 1737 #define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN__SHIFT 0x0 1738 #define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_RAW__SHIFT 0x1 1739 #define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN__SHIFT 0x2 1740 #define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_RAW__SHIFT 0x3 1741 #define UVD_JMI_CLEAN_STATUS__DJRBC_READ_CLEAN__SHIFT 0x4 1742 #define UVD_JMI_CLEAN_STATUS__EJRBC_READ_CLEAN__SHIFT 0x5 1743 #define UVD_JMI_CLEAN_STATUS__JPEG_READ_CLEAN__SHIFT 0x6 1744 #define UVD_JMI_CLEAN_STATUS__PEL_READ_CLEAN__SHIFT 0x7 1745 #define UVD_JMI_CLEAN_STATUS__SCALAR_READ_CLEAN__SHIFT 0x8 1746 #define UVD_JMI_CLEAN_STATUS__DJRBC_WRITE_CLEAN__SHIFT 0x9 1747 #define UVD_JMI_CLEAN_STATUS__EJRBC_WRITE_CLEAN__SHIFT 0xa 1748 #define UVD_JMI_CLEAN_STATUS__BS_WRITE_CLEAN__SHIFT 0xb 1749 #define UVD_JMI_CLEAN_STATUS__JPEG_WRITE_CLEAN__SHIFT 0xc 1750 #define UVD_JMI_CLEAN_STATUS__SCALAR_WRITE_CLEAN__SHIFT 0xd 1751 #define UVD_JMI_CLEAN_STATUS__MC_WRITE_PENDING__SHIFT 0xe 1752 #define UVD_JMI_CLEAN_STATUS__JPEG2_WRITE_CLEAN__SHIFT 0xf 1753 #define UVD_JMI_CLEAN_STATUS__JPEG2_READ_CLEAN__SHIFT 0x10 1754 #define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_MASK 0x00000001L 1755 #define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_RAW_MASK 0x00000002L 1756 #define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_MASK 0x00000004L 1757 #define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_RAW_MASK 0x00000008L 1758 #define UVD_JMI_CLEAN_STATUS__DJRBC_READ_CLEAN_MASK 0x00000010L 1759 #define UVD_JMI_CLEAN_STATUS__EJRBC_READ_CLEAN_MASK 0x00000020L 1760 #define UVD_JMI_CLEAN_STATUS__JPEG_READ_CLEAN_MASK 0x00000040L 1761 #define UVD_JMI_CLEAN_STATUS__PEL_READ_CLEAN_MASK 0x00000080L 1762 #define UVD_JMI_CLEAN_STATUS__SCALAR_READ_CLEAN_MASK 0x00000100L 1763 #define UVD_JMI_CLEAN_STATUS__DJRBC_WRITE_CLEAN_MASK 0x00000200L 1764 #define UVD_JMI_CLEAN_STATUS__EJRBC_WRITE_CLEAN_MASK 0x00000400L 1765 #define UVD_JMI_CLEAN_STATUS__BS_WRITE_CLEAN_MASK 0x00000800L 1766 #define UVD_JMI_CLEAN_STATUS__JPEG_WRITE_CLEAN_MASK 0x00001000L 1767 #define UVD_JMI_CLEAN_STATUS__SCALAR_WRITE_CLEAN_MASK 0x00002000L 1768 #define UVD_JMI_CLEAN_STATUS__MC_WRITE_PENDING_MASK 0x00004000L 1769 #define UVD_JMI_CLEAN_STATUS__JPEG2_WRITE_CLEAN_MASK 0x00008000L 1770 #define UVD_JMI_CLEAN_STATUS__JPEG2_READ_CLEAN_MASK 0x00010000L 1771 //UVD_LMI_JPEG_READ_64BIT_BAR_LOW 1772 #define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1773 #define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1774 //UVD_LMI_JPEG_READ_64BIT_BAR_HIGH 1775 #define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1776 #define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1777 //UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 1778 #define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1779 #define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1780 //UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 1781 #define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1782 #define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1783 //UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 1784 #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1785 #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1786 //UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 1787 #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1788 #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1789 //UVD_LMI_JRBC_RB_64BIT_BAR_LOW 1790 #define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1791 #define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1792 //UVD_LMI_JRBC_RB_64BIT_BAR_HIGH 1793 #define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1794 #define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1795 //UVD_LMI_JRBC_IB_64BIT_BAR_LOW 1796 #define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1797 #define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1798 //UVD_LMI_JRBC_IB_64BIT_BAR_HIGH 1799 #define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1800 #define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1801 //UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 1802 #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1803 #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1804 //UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 1805 #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1806 #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1807 //UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW 1808 #define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1809 #define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1810 //UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH 1811 #define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1812 #define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1813 //UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 1814 #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1815 #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1816 //UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 1817 #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1818 #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1819 //UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW 1820 #define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1821 #define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1822 //UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH 1823 #define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1824 #define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1825 //UVD_JMI_PEL_RD_64BIT_BAR_LOW 1826 #define UVD_JMI_PEL_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1827 #define UVD_JMI_PEL_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1828 //UVD_JMI_PEL_RD_64BIT_BAR_HIGH 1829 #define UVD_JMI_PEL_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1830 #define UVD_JMI_PEL_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1831 //UVD_JMI_BS_WR_64BIT_BAR_LOW 1832 #define UVD_JMI_BS_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1833 #define UVD_JMI_BS_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1834 //UVD_JMI_BS_WR_64BIT_BAR_HIGH 1835 #define UVD_JMI_BS_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1836 #define UVD_JMI_BS_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1837 //UVD_JMI_SCALAR_RD_64BIT_BAR_LOW 1838 #define UVD_JMI_SCALAR_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1839 #define UVD_JMI_SCALAR_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1840 //UVD_JMI_SCALAR_RD_64BIT_BAR_HIGH 1841 #define UVD_JMI_SCALAR_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1842 #define UVD_JMI_SCALAR_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1843 //UVD_JMI_SCALAR_WR_64BIT_BAR_LOW 1844 #define UVD_JMI_SCALAR_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1845 #define UVD_JMI_SCALAR_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1846 //UVD_JMI_SCALAR_WR_64BIT_BAR_HIGH 1847 #define UVD_JMI_SCALAR_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1848 #define UVD_JMI_SCALAR_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1849 //UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW 1850 #define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1851 #define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1852 //UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 1853 #define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1854 #define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1855 //UVD_LMI_EJRBC_RB_64BIT_BAR_LOW 1856 #define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1857 #define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1858 //UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH 1859 #define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1860 #define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1861 //UVD_LMI_EJRBC_IB_64BIT_BAR_LOW 1862 #define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1863 #define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1864 //UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH 1865 #define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1866 #define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1867 //UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW 1868 #define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1869 #define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1870 //UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH 1871 #define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1872 #define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1873 //UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW 1874 #define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1875 #define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1876 //UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH 1877 #define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1878 #define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1879 //UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW 1880 #define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1881 #define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1882 //UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH 1883 #define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1884 #define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1885 //UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW 1886 #define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1887 #define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1888 //UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH 1889 #define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1890 #define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1891 //UVD_LMI_JPEG_PREEMPT_VMID 1892 #define UVD_LMI_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 1893 #define UVD_LMI_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL 1894 //UVD_LMI_ENC_JPEG_PREEMPT_VMID 1895 #define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 1896 #define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL 1897 //UVD_LMI_JPEG2_VMID 1898 #define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID__SHIFT 0x0 1899 #define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID__SHIFT 0x4 1900 #define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID_MASK 0x0000000FL 1901 #define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID_MASK 0x000000F0L 1902 //UVD_LMI_JPEG2_READ_64BIT_BAR_LOW 1903 #define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1904 #define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1905 //UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH 1906 #define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1907 #define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1908 //UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW 1909 #define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1910 #define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1911 //UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH 1912 #define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1913 #define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1914 //UVD_LMI_JPEG_CTRL2 1915 #define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN__SHIFT 0x0 1916 #define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN__SHIFT 0x1 1917 #define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST__SHIFT 0x4 1918 #define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST__SHIFT 0x8 1919 #define UVD_LMI_JPEG_CTRL2__RD_SWAP__SHIFT 0x14 1920 #define UVD_LMI_JPEG_CTRL2__WR_SWAP__SHIFT 0x16 1921 #define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN_MASK 0x00000001L 1922 #define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN_MASK 0x00000002L 1923 #define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST_MASK 0x000000F0L 1924 #define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST_MASK 0x00000F00L 1925 #define UVD_LMI_JPEG_CTRL2__RD_SWAP_MASK 0x00300000L 1926 #define UVD_LMI_JPEG_CTRL2__WR_SWAP_MASK 0x00C00000L 1927 //UVD_JMI_DEC_SWAP_CNTL 1928 #define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 1929 #define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 1930 #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 1931 #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 1932 #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 1933 #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa 1934 #define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc 1935 #define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP__SHIFT 0xe 1936 #define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP__SHIFT 0x10 1937 #define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 1938 #define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 1939 #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L 1940 #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L 1941 #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L 1942 #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L 1943 #define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L 1944 #define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP_MASK 0x0000C000L 1945 #define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP_MASK 0x00030000L 1946 //UVD_JMI_ENC_SWAP_CNTL 1947 #define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 1948 #define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 1949 #define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 1950 #define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 1951 #define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 1952 #define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa 1953 #define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc 1954 #define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP__SHIFT 0xe 1955 #define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP__SHIFT 0x10 1956 #define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP__SHIFT 0x12 1957 #define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP__SHIFT 0x14 1958 #define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP__SHIFT 0x16 1959 #define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 1960 #define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 1961 #define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L 1962 #define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L 1963 #define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L 1964 #define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L 1965 #define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L 1966 #define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP_MASK 0x0000C000L 1967 #define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP_MASK 0x00030000L 1968 #define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP_MASK 0x000C0000L 1969 #define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP_MASK 0x00300000L 1970 #define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP_MASK 0x00C00000L 1971 //UVD_JMI_CNTL 1972 #define UVD_JMI_CNTL__SOFT_RESET__SHIFT 0x0 1973 #define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX__SHIFT 0x8 1974 #define UVD_JMI_CNTL__SOFT_RESET_MASK 0x00000001L 1975 #define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX_MASK 0x0003FF00L 1976 //UVD_JMI_ATOMIC_CNTL 1977 #define UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en__SHIFT 0x0 1978 #define UVD_JMI_ATOMIC_CNTL__atomic_max_burst__SHIFT 0x1 1979 #define UVD_JMI_ATOMIC_CNTL__atomic_wr_drop__SHIFT 0x5 1980 #define UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en__SHIFT 0x6 1981 #define UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG__SHIFT 0x7 1982 #define UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE__SHIFT 0xb 1983 #define UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en_MASK 0x00000001L 1984 #define UVD_JMI_ATOMIC_CNTL__atomic_max_burst_MASK 0x0000001EL 1985 #define UVD_JMI_ATOMIC_CNTL__atomic_wr_drop_MASK 0x00000020L 1986 #define UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en_MASK 0x00000040L 1987 #define UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG_MASK 0x00000780L 1988 #define UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE_MASK 0x00000800L 1989 //UVD_JMI_ATOMIC_CNTL2 1990 #define UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap__SHIFT 0x10 1991 #define UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP__SHIFT 0x18 1992 #define UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap_MASK 0x00FF0000L 1993 #define UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP_MASK 0xFF000000L 1994 //UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 1995 #define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1996 #define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1997 //UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 1998 #define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1999 #define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 2000 //UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW 2001 #define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 2002 #define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 2003 //UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH 2004 #define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 2005 #define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 2006 //JPEG2_LMI_DROP 2007 #define JPEG2_LMI_DROP__JPEG2_WR_DROP__SHIFT 0x0 2008 #define JPEG2_LMI_DROP__JPEG2_RD_DROP__SHIFT 0x1 2009 #define JPEG2_LMI_DROP__JPEG2_WR_DROP_MASK 0x00000001L 2010 #define JPEG2_LMI_DROP__JPEG2_RD_DROP_MASK 0x00000002L 2011 //UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW 2012 #define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 2013 #define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 2014 //UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH 2015 #define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 2016 #define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 2017 //UVD_JMI_DEC_SWAP_CNTL2 2018 #define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP__SHIFT 0x0 2019 #define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP__SHIFT 0x2 2020 #define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP_MASK 0x00000003L 2021 #define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP_MASK 0x0000000CL 2022 //UVD_JMI_DJPEG_RAS_CNTL 2023 #define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_IH_EN__SHIFT 0x0 2024 #define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_PMI_EN__SHIFT 0x1 2025 #define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_REARM__SHIFT 0x2 2026 #define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_STALL_EN__SHIFT 0x3 2027 #define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_READY__SHIFT 0x4 2028 #define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_IH_EN_MASK 0x00000001L 2029 #define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_PMI_EN_MASK 0x00000002L 2030 #define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_REARM_MASK 0x00000004L 2031 #define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_STALL_EN_MASK 0x00000008L 2032 #define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_READY_MASK 0x00000010L 2033 2034 2035 // addressBlock: uvd0_uvd_jpeg_common_dec 2036 //JPEG_SOFT_RESET_STATUS 2037 #define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS__SHIFT 0x0 2038 #define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS__SHIFT 0x1 2039 #define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS__SHIFT 0x2 2040 #define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS__SHIFT 0x3 2041 #define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS__SHIFT 0x4 2042 #define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS__SHIFT 0x5 2043 #define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS_MASK 0x00000001L 2044 #define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS_MASK 0x00000002L 2045 #define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS_MASK 0x00000004L 2046 #define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS_MASK 0x00000008L 2047 #define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS_MASK 0x00000010L 2048 #define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS_MASK 0x00000020L 2049 //JPEG_SYS_INT_EN 2050 #define JPEG_SYS_INT_EN__DJPEG_CORE__SHIFT 0x0 2051 #define JPEG_SYS_INT_EN__DJRBC__SHIFT 0x1 2052 #define JPEG_SYS_INT_EN__DJPEG_PF_RPT__SHIFT 0x2 2053 #define JPEG_SYS_INT_EN__EJPEG_PF_RPT__SHIFT 0x3 2054 #define JPEG_SYS_INT_EN__EJPEG_CORE__SHIFT 0x4 2055 #define JPEG_SYS_INT_EN__EJRBC__SHIFT 0x5 2056 #define JPEG_SYS_INT_EN__DJPEG_CORE2__SHIFT 0x6 2057 #define JPEG_SYS_INT_EN__DJPEG_RAS_CNTL__SHIFT 0x7 2058 #define JPEG_SYS_INT_EN__EJPEG_RAS_CNTL__SHIFT 0x8 2059 #define JPEG_SYS_INT_EN__DJPEG_CORE_MASK 0x00000001L 2060 #define JPEG_SYS_INT_EN__DJRBC_MASK 0x00000002L 2061 #define JPEG_SYS_INT_EN__DJPEG_PF_RPT_MASK 0x00000004L 2062 #define JPEG_SYS_INT_EN__EJPEG_PF_RPT_MASK 0x00000008L 2063 #define JPEG_SYS_INT_EN__EJPEG_CORE_MASK 0x00000010L 2064 #define JPEG_SYS_INT_EN__EJRBC_MASK 0x00000020L 2065 #define JPEG_SYS_INT_EN__DJPEG_CORE2_MASK 0x00000040L 2066 #define JPEG_SYS_INT_EN__DJPEG_RAS_CNTL_MASK 0x00000080L 2067 #define JPEG_SYS_INT_EN__EJPEG_RAS_CNTL_MASK 0x00000100L 2068 //JPEG_SYS_INT_STATUS 2069 #define JPEG_SYS_INT_STATUS__DJPEG_CORE__SHIFT 0x0 2070 #define JPEG_SYS_INT_STATUS__DJRBC__SHIFT 0x1 2071 #define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT__SHIFT 0x2 2072 #define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT__SHIFT 0x3 2073 #define JPEG_SYS_INT_STATUS__EJPEG_CORE__SHIFT 0x4 2074 #define JPEG_SYS_INT_STATUS__EJRBC__SHIFT 0x5 2075 #define JPEG_SYS_INT_STATUS__DJPEG_CORE2__SHIFT 0x6 2076 #define JPEG_SYS_INT_STATUS__DJPEG_RAS_CNTL__SHIFT 0x7 2077 #define JPEG_SYS_INT_STATUS__EJPEG_RAS_CNTL__SHIFT 0x8 2078 #define JPEG_SYS_INT_STATUS__DJPEG_CORE_MASK 0x00000001L 2079 #define JPEG_SYS_INT_STATUS__DJRBC_MASK 0x00000002L 2080 #define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT_MASK 0x00000004L 2081 #define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT_MASK 0x00000008L 2082 #define JPEG_SYS_INT_STATUS__EJPEG_CORE_MASK 0x00000010L 2083 #define JPEG_SYS_INT_STATUS__EJRBC_MASK 0x00000020L 2084 #define JPEG_SYS_INT_STATUS__DJPEG_CORE2_MASK 0x00000040L 2085 #define JPEG_SYS_INT_STATUS__DJPEG_RAS_CNTL_MASK 0x00000080L 2086 #define JPEG_SYS_INT_STATUS__EJPEG_RAS_CNTL_MASK 0x00000100L 2087 //JPEG_SYS_INT_ACK 2088 #define JPEG_SYS_INT_ACK__DJPEG_CORE__SHIFT 0x0 2089 #define JPEG_SYS_INT_ACK__DJRBC__SHIFT 0x1 2090 #define JPEG_SYS_INT_ACK__DJPEG_PF_RPT__SHIFT 0x2 2091 #define JPEG_SYS_INT_ACK__EJPEG_PF_RPT__SHIFT 0x3 2092 #define JPEG_SYS_INT_ACK__EJPEG_CORE__SHIFT 0x4 2093 #define JPEG_SYS_INT_ACK__EJRBC__SHIFT 0x5 2094 #define JPEG_SYS_INT_ACK__DJPEG_CORE2__SHIFT 0x6 2095 #define JPEG_SYS_INT_ACK__DJPEG_RAS_CNTL__SHIFT 0x7 2096 #define JPEG_SYS_INT_ACK__EJPEG_RAS_CNTL__SHIFT 0x8 2097 #define JPEG_SYS_INT_ACK__DJPEG_CORE_MASK 0x00000001L 2098 #define JPEG_SYS_INT_ACK__DJRBC_MASK 0x00000002L 2099 #define JPEG_SYS_INT_ACK__DJPEG_PF_RPT_MASK 0x00000004L 2100 #define JPEG_SYS_INT_ACK__EJPEG_PF_RPT_MASK 0x00000008L 2101 #define JPEG_SYS_INT_ACK__EJPEG_CORE_MASK 0x00000010L 2102 #define JPEG_SYS_INT_ACK__EJRBC_MASK 0x00000020L 2103 #define JPEG_SYS_INT_ACK__DJPEG_CORE2_MASK 0x00000040L 2104 #define JPEG_SYS_INT_ACK__DJPEG_RAS_CNTL_MASK 0x00000080L 2105 #define JPEG_SYS_INT_ACK__EJPEG_RAS_CNTL_MASK 0x00000100L 2106 //JPEG_MEMCHECK_SYS_INT_EN 2107 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_RD_ERR_EN__SHIFT 0x0 2108 #define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_RD_ERR_EN__SHIFT 0x1 2109 #define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH_RD_ERR_EN__SHIFT 0x2 2110 #define JPEG_MEMCHECK_SYS_INT_EN__PELFETCH_RD_ERR_EN__SHIFT 0x3 2111 #define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_RD_ERR_EN__SHIFT 0x4 2112 #define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_RD_ERR_EN__SHIFT 0x5 2113 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_WR_ERR_EN__SHIFT 0x6 2114 #define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_WR_ERR_EN__SHIFT 0x7 2115 #define JPEG_MEMCHECK_SYS_INT_EN__BS_WR_ERR_EN__SHIFT 0x8 2116 #define JPEG_MEMCHECK_SYS_INT_EN__OBUF_WR_ERR_EN__SHIFT 0x9 2117 #define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_WR_ERR_EN__SHIFT 0xa 2118 #define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_WR_ERR_EN__SHIFT 0xb 2119 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_RD_ERR_EN_MASK 0x00000001L 2120 #define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_RD_ERR_EN_MASK 0x00000002L 2121 #define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH_RD_ERR_EN_MASK 0x00000004L 2122 #define JPEG_MEMCHECK_SYS_INT_EN__PELFETCH_RD_ERR_EN_MASK 0x00000008L 2123 #define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_RD_ERR_EN_MASK 0x00000010L 2124 #define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_RD_ERR_EN_MASK 0x00000020L 2125 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_WR_ERR_EN_MASK 0x00000040L 2126 #define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_WR_ERR_EN_MASK 0x00000080L 2127 #define JPEG_MEMCHECK_SYS_INT_EN__BS_WR_ERR_EN_MASK 0x00000100L 2128 #define JPEG_MEMCHECK_SYS_INT_EN__OBUF_WR_ERR_EN_MASK 0x00000200L 2129 #define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_WR_ERR_EN_MASK 0x00000400L 2130 #define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_WR_ERR_EN_MASK 0x00000800L 2131 //JPEG_MEMCHECK_SYS_INT_STAT 2132 #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_HI_ERR__SHIFT 0x0 2133 #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_LO_ERR__SHIFT 0x1 2134 #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_HI_ERR__SHIFT 0x2 2135 #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_LO_ERR__SHIFT 0x3 2136 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_HI_ERR__SHIFT 0x4 2137 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_LO_ERR__SHIFT 0x5 2138 #define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_HI_ERR__SHIFT 0x6 2139 #define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_LO_ERR__SHIFT 0x7 2140 #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_HI_ERR__SHIFT 0x8 2141 #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_LO_ERR__SHIFT 0x9 2142 #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_HI_ERR__SHIFT 0xa 2143 #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_LO_ERR__SHIFT 0xb 2144 #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_HI_ERR__SHIFT 0xc 2145 #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_LO_ERR__SHIFT 0xd 2146 #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_HI_ERR__SHIFT 0xe 2147 #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_LO_ERR__SHIFT 0xf 2148 #define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_HI_ERR__SHIFT 0x10 2149 #define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_LO_ERR__SHIFT 0x11 2150 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_HI_ERR__SHIFT 0x12 2151 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_LO_ERR__SHIFT 0x13 2152 #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_HI_ERR__SHIFT 0x14 2153 #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_LO_ERR__SHIFT 0x15 2154 #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_HI_ERR__SHIFT 0x16 2155 #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_LO_ERR__SHIFT 0x17 2156 #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_HI_ERR_MASK 0x00000001L 2157 #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_LO_ERR_MASK 0x00000002L 2158 #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_HI_ERR_MASK 0x00000004L 2159 #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_LO_ERR_MASK 0x00000008L 2160 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_HI_ERR_MASK 0x00000010L 2161 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_LO_ERR_MASK 0x00000020L 2162 #define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_HI_ERR_MASK 0x00000040L 2163 #define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_LO_ERR_MASK 0x00000080L 2164 #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_HI_ERR_MASK 0x00000100L 2165 #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_LO_ERR_MASK 0x00000200L 2166 #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_HI_ERR_MASK 0x00000400L 2167 #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_LO_ERR_MASK 0x00000800L 2168 #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_HI_ERR_MASK 0x00001000L 2169 #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_LO_ERR_MASK 0x00002000L 2170 #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_HI_ERR_MASK 0x00004000L 2171 #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_LO_ERR_MASK 0x00008000L 2172 #define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_HI_ERR_MASK 0x00010000L 2173 #define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_LO_ERR_MASK 0x00020000L 2174 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_HI_ERR_MASK 0x00040000L 2175 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_LO_ERR_MASK 0x00080000L 2176 #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_HI_ERR_MASK 0x00100000L 2177 #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_LO_ERR_MASK 0x00200000L 2178 #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_HI_ERR_MASK 0x00400000L 2179 #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_LO_ERR_MASK 0x00800000L 2180 //JPEG_MEMCHECK_SYS_INT_ACK 2181 #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_HI_ERR__SHIFT 0x0 2182 #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_LO_ERR__SHIFT 0x1 2183 #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_HI_ERR__SHIFT 0x2 2184 #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_LO_ERR__SHIFT 0x3 2185 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_HI_ERR__SHIFT 0x4 2186 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_LO_ERR__SHIFT 0x5 2187 #define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_HI_ERR__SHIFT 0x6 2188 #define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_LO_ERR__SHIFT 0x7 2189 #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_HI_ERR__SHIFT 0x8 2190 #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_LO_ERR__SHIFT 0x9 2191 #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_HI_ERR__SHIFT 0xa 2192 #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_LO_ERR__SHIFT 0xb 2193 #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_HI_ERR__SHIFT 0xc 2194 #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_LO_ERR__SHIFT 0xd 2195 #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_HI_ERR__SHIFT 0xe 2196 #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_LO_ERR__SHIFT 0xf 2197 #define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_HI_ERR__SHIFT 0x10 2198 #define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_LO_ERR__SHIFT 0x11 2199 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_HI_ERR__SHIFT 0x12 2200 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_LO_ERR__SHIFT 0x13 2201 #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_HI_ERR__SHIFT 0x14 2202 #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_LO_ERR__SHIFT 0x15 2203 #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_HI_ERR__SHIFT 0x16 2204 #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_LO_ERR__SHIFT 0x17 2205 #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_HI_ERR_MASK 0x00000001L 2206 #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_LO_ERR_MASK 0x00000002L 2207 #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_HI_ERR_MASK 0x00000004L 2208 #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_LO_ERR_MASK 0x00000008L 2209 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_HI_ERR_MASK 0x00000010L 2210 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_LO_ERR_MASK 0x00000020L 2211 #define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_HI_ERR_MASK 0x00000040L 2212 #define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_LO_ERR_MASK 0x00000080L 2213 #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_HI_ERR_MASK 0x00000100L 2214 #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_LO_ERR_MASK 0x00000200L 2215 #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_HI_ERR_MASK 0x00000400L 2216 #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_LO_ERR_MASK 0x00000800L 2217 #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_HI_ERR_MASK 0x00001000L 2218 #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_LO_ERR_MASK 0x00002000L 2219 #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_HI_ERR_MASK 0x00004000L 2220 #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_LO_ERR_MASK 0x00008000L 2221 #define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_HI_ERR_MASK 0x00010000L 2222 #define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_LO_ERR_MASK 0x00020000L 2223 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_HI_ERR_MASK 0x00040000L 2224 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_LO_ERR_MASK 0x00080000L 2225 #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_HI_ERR_MASK 0x00100000L 2226 #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_LO_ERR_MASK 0x00200000L 2227 #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_HI_ERR_MASK 0x00400000L 2228 #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_LO_ERR_MASK 0x00800000L 2229 //JPEG_MASTINT_EN 2230 #define JPEG_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 2231 #define JPEG_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 2232 #define JPEG_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L 2233 #define JPEG_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L 2234 //JPEG_IH_CTRL 2235 #define JPEG_IH_CTRL__IH_SOFT_RESET__SHIFT 0x0 2236 #define JPEG_IH_CTRL__IH_STALL_EN__SHIFT 0x1 2237 #define JPEG_IH_CTRL__IH_STATUS_CLEAN__SHIFT 0x2 2238 #define JPEG_IH_CTRL__IH_VMID__SHIFT 0x3 2239 #define JPEG_IH_CTRL__IH_USER_DATA__SHIFT 0x7 2240 #define JPEG_IH_CTRL__IH_RINGID__SHIFT 0x13 2241 #define JPEG_IH_CTRL__IH_SOFT_RESET_MASK 0x00000001L 2242 #define JPEG_IH_CTRL__IH_STALL_EN_MASK 0x00000002L 2243 #define JPEG_IH_CTRL__IH_STATUS_CLEAN_MASK 0x00000004L 2244 #define JPEG_IH_CTRL__IH_VMID_MASK 0x00000078L 2245 #define JPEG_IH_CTRL__IH_USER_DATA_MASK 0x0007FF80L 2246 #define JPEG_IH_CTRL__IH_RINGID_MASK 0x07F80000L 2247 //JRBBM_ARB_CTRL 2248 #define JRBBM_ARB_CTRL__DJRBC_DROP__SHIFT 0x0 2249 #define JRBBM_ARB_CTRL__EJRBC_DROP__SHIFT 0x1 2250 #define JRBBM_ARB_CTRL__SRBM_DROP__SHIFT 0x2 2251 #define JRBBM_ARB_CTRL__DJRBC_DROP_MASK 0x00000001L 2252 #define JRBBM_ARB_CTRL__EJRBC_DROP_MASK 0x00000002L 2253 #define JRBBM_ARB_CTRL__SRBM_DROP_MASK 0x00000004L 2254 2255 2256 // addressBlock: uvd0_uvd_jpeg_common_sclk_dec 2257 //JPEG_CGC_GATE 2258 #define JPEG_CGC_GATE__JPEG_DEC__SHIFT 0x0 2259 #define JPEG_CGC_GATE__JPEG2_DEC__SHIFT 0x1 2260 #define JPEG_CGC_GATE__JPEG_ENC__SHIFT 0x2 2261 #define JPEG_CGC_GATE__JMCIF__SHIFT 0x3 2262 #define JPEG_CGC_GATE__JRBBM__SHIFT 0x4 2263 #define JPEG_CGC_GATE__JPEG_DEC_MASK 0x00000001L 2264 #define JPEG_CGC_GATE__JPEG2_DEC_MASK 0x00000002L 2265 #define JPEG_CGC_GATE__JPEG_ENC_MASK 0x00000004L 2266 #define JPEG_CGC_GATE__JMCIF_MASK 0x00000008L 2267 #define JPEG_CGC_GATE__JRBBM_MASK 0x00000010L 2268 //JPEG_CGC_CTRL 2269 #define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 2270 #define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x1 2271 #define JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x5 2272 #define JPEG_CGC_CTRL__DYN_OCLK_RAMP_EN__SHIFT 0xa 2273 #define JPEG_CGC_CTRL__DYN_RCLK_RAMP_EN__SHIFT 0xb 2274 #define JPEG_CGC_CTRL__GATER_DIV_ID__SHIFT 0xc 2275 #define JPEG_CGC_CTRL__JPEG_DEC_MODE__SHIFT 0x10 2276 #define JPEG_CGC_CTRL__JPEG2_DEC_MODE__SHIFT 0x11 2277 #define JPEG_CGC_CTRL__JPEG_ENC_MODE__SHIFT 0x12 2278 #define JPEG_CGC_CTRL__JMCIF_MODE__SHIFT 0x13 2279 #define JPEG_CGC_CTRL__JRBBM_MODE__SHIFT 0x14 2280 #define JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L 2281 #define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000001EL 2282 #define JPEG_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000003E0L 2283 #define JPEG_CGC_CTRL__DYN_OCLK_RAMP_EN_MASK 0x00000400L 2284 #define JPEG_CGC_CTRL__DYN_RCLK_RAMP_EN_MASK 0x00000800L 2285 #define JPEG_CGC_CTRL__GATER_DIV_ID_MASK 0x00007000L 2286 #define JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK 0x00010000L 2287 #define JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK 0x00020000L 2288 #define JPEG_CGC_CTRL__JPEG_ENC_MODE_MASK 0x00040000L 2289 #define JPEG_CGC_CTRL__JMCIF_MODE_MASK 0x00080000L 2290 #define JPEG_CGC_CTRL__JRBBM_MODE_MASK 0x00100000L 2291 //JPEG_CGC_STATUS 2292 #define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE__SHIFT 0x0 2293 #define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE__SHIFT 0x1 2294 #define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE__SHIFT 0x2 2295 #define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE__SHIFT 0x3 2296 #define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE__SHIFT 0x4 2297 #define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE__SHIFT 0x5 2298 #define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE__SHIFT 0x6 2299 #define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE__SHIFT 0x7 2300 #define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE__SHIFT 0x8 2301 #define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE_MASK 0x00000001L 2302 #define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE_MASK 0x00000002L 2303 #define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE_MASK 0x00000004L 2304 #define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE_MASK 0x00000008L 2305 #define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE_MASK 0x00000010L 2306 #define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE_MASK 0x00000020L 2307 #define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE_MASK 0x00000040L 2308 #define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE_MASK 0x00000080L 2309 #define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE_MASK 0x00000100L 2310 //JPEG_COMN_CGC_MEM_CTRL 2311 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN__SHIFT 0x0 2312 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN__SHIFT 0x1 2313 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN__SHIFT 0x2 2314 #define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 2315 #define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 2316 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN_MASK 0x00000001L 2317 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN_MASK 0x00000002L 2318 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN_MASK 0x00000004L 2319 #define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0x000F0000L 2320 #define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0x00F00000L 2321 //JPEG_DEC_CGC_MEM_CTRL 2322 #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN__SHIFT 0x0 2323 #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN__SHIFT 0x1 2324 #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN__SHIFT 0x2 2325 #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN_MASK 0x00000001L 2326 #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN_MASK 0x00000002L 2327 #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN_MASK 0x00000004L 2328 //JPEG2_DEC_CGC_MEM_CTRL 2329 #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN__SHIFT 0x0 2330 #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN__SHIFT 0x1 2331 #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN__SHIFT 0x2 2332 #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN_MASK 0x00000001L 2333 #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN_MASK 0x00000002L 2334 #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN_MASK 0x00000004L 2335 //JPEG_ENC_CGC_MEM_CTRL 2336 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN__SHIFT 0x0 2337 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN__SHIFT 0x1 2338 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN__SHIFT 0x2 2339 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN_MASK 0x00000001L 2340 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN_MASK 0x00000002L 2341 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN_MASK 0x00000004L 2342 //JPEG_SOFT_RESET2 2343 #define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0 2344 #define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L 2345 //JPEG_PERF_BANK_CONF 2346 #define JPEG_PERF_BANK_CONF__RESET__SHIFT 0x0 2347 #define JPEG_PERF_BANK_CONF__PEEK__SHIFT 0x8 2348 #define JPEG_PERF_BANK_CONF__CONCATENATE__SHIFT 0x10 2349 #define JPEG_PERF_BANK_CONF__RESET_MASK 0x0000000FL 2350 #define JPEG_PERF_BANK_CONF__PEEK_MASK 0x00000F00L 2351 #define JPEG_PERF_BANK_CONF__CONCATENATE_MASK 0x00030000L 2352 //JPEG_PERF_BANK_EVENT_SEL 2353 #define JPEG_PERF_BANK_EVENT_SEL__SEL0__SHIFT 0x0 2354 #define JPEG_PERF_BANK_EVENT_SEL__SEL1__SHIFT 0x8 2355 #define JPEG_PERF_BANK_EVENT_SEL__SEL2__SHIFT 0x10 2356 #define JPEG_PERF_BANK_EVENT_SEL__SEL3__SHIFT 0x18 2357 #define JPEG_PERF_BANK_EVENT_SEL__SEL0_MASK 0x000000FFL 2358 #define JPEG_PERF_BANK_EVENT_SEL__SEL1_MASK 0x0000FF00L 2359 #define JPEG_PERF_BANK_EVENT_SEL__SEL2_MASK 0x00FF0000L 2360 #define JPEG_PERF_BANK_EVENT_SEL__SEL3_MASK 0xFF000000L 2361 //JPEG_PERF_BANK_COUNT0 2362 #define JPEG_PERF_BANK_COUNT0__COUNT__SHIFT 0x0 2363 #define JPEG_PERF_BANK_COUNT0__COUNT_MASK 0xFFFFFFFFL 2364 //JPEG_PERF_BANK_COUNT1 2365 #define JPEG_PERF_BANK_COUNT1__COUNT__SHIFT 0x0 2366 #define JPEG_PERF_BANK_COUNT1__COUNT_MASK 0xFFFFFFFFL 2367 //JPEG_PERF_BANK_COUNT2 2368 #define JPEG_PERF_BANK_COUNT2__COUNT__SHIFT 0x0 2369 #define JPEG_PERF_BANK_COUNT2__COUNT_MASK 0xFFFFFFFFL 2370 //JPEG_PERF_BANK_COUNT3 2371 #define JPEG_PERF_BANK_COUNT3__COUNT__SHIFT 0x0 2372 #define JPEG_PERF_BANK_COUNT3__COUNT_MASK 0xFFFFFFFFL 2373 2374 2375 // addressBlock: uvd0_uvd_jpeg_enc_dec 2376 //UVD_JPEG_ENC_INT_EN 2377 #define UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN__SHIFT 0x0 2378 #define UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN__SHIFT 0x1 2379 #define UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN__SHIFT 0x2 2380 #define UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN__SHIFT 0x3 2381 #define UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN__SHIFT 0x4 2382 #define UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN__SHIFT 0x5 2383 #define UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN__SHIFT 0x6 2384 #define UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN_MASK 0x00000001L 2385 #define UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN_MASK 0x00000002L 2386 #define UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN_MASK 0x00000004L 2387 #define UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN_MASK 0x00000008L 2388 #define UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN_MASK 0x00000010L 2389 #define UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN_MASK 0x00000020L 2390 #define UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN_MASK 0x00000040L 2391 //UVD_JPEG_ENC_INT_STATUS 2392 #define UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS__SHIFT 0x0 2393 #define UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS__SHIFT 0x1 2394 #define UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS__SHIFT 0x2 2395 #define UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS__SHIFT 0x3 2396 #define UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS__SHIFT 0x4 2397 #define UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS__SHIFT 0x5 2398 #define UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS__SHIFT 0x6 2399 #define UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS_MASK 0x00000001L 2400 #define UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS_MASK 0x00000002L 2401 #define UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS_MASK 0x00000004L 2402 #define UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS_MASK 0x00000008L 2403 #define UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS_MASK 0x00000010L 2404 #define UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS_MASK 0x00000020L 2405 #define UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS_MASK 0x00000040L 2406 //UVD_JPEG_ENC_ENGINE_CNTL 2407 #define UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS__SHIFT 0x0 2408 #define UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES__SHIFT 0x1 2409 #define UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN__SHIFT 0x2 2410 #define UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN__SHIFT 0x3 2411 #define UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED__SHIFT 0x4 2412 #define UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN__SHIFT 0x9 2413 #define UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS_MASK 0x00000001L 2414 #define UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES_MASK 0x00000002L 2415 #define UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN_MASK 0x00000004L 2416 #define UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN_MASK 0x00000008L 2417 #define UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED_MASK 0x00000010L 2418 #define UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN_MASK 0x00000200L 2419 //UVD_JPEG_ENC_SCRATCH1 2420 #define UVD_JPEG_ENC_SCRATCH1__SCRATCH1__SHIFT 0x0 2421 #define UVD_JPEG_ENC_SCRATCH1__SCRATCH1_MASK 0xFFFFFFFFL 2422 2423 2424 // addressBlock: uvd0_uvd_jpeg_enc_sclk_dec 2425 //UVD_JPEG_ENC_SPS_INFO 2426 #define UVD_JPEG_ENC_SPS_INFO__SRC_FORMAT__SHIFT 0x0 2427 #define UVD_JPEG_ENC_SPS_INFO__YUY2_SUBFORMAT__SHIFT 0x3 2428 #define UVD_JPEG_ENC_SPS_INFO__OUT_FMT_422__SHIFT 0x4 2429 #define UVD_JPEG_ENC_SPS_INFO__SRC_FORMAT_MASK 0x00000007L 2430 #define UVD_JPEG_ENC_SPS_INFO__YUY2_SUBFORMAT_MASK 0x00000008L 2431 #define UVD_JPEG_ENC_SPS_INFO__OUT_FMT_422_MASK 0x00000010L 2432 //UVD_JPEG_ENC_SPS_INFO1 2433 #define UVD_JPEG_ENC_SPS_INFO1__SRC_WIDTH__SHIFT 0x0 2434 #define UVD_JPEG_ENC_SPS_INFO1__SRC_HEIGHT__SHIFT 0x10 2435 #define UVD_JPEG_ENC_SPS_INFO1__SRC_WIDTH_MASK 0x0000FFFFL 2436 #define UVD_JPEG_ENC_SPS_INFO1__SRC_HEIGHT_MASK 0xFFFF0000L 2437 //UVD_JPEG_ENC_TBL_SIZE 2438 #define UVD_JPEG_ENC_TBL_SIZE__TBL_SIZE__SHIFT 0x6 2439 #define UVD_JPEG_ENC_TBL_SIZE__TBL_SIZE_MASK 0x00000FC0L 2440 //UVD_JPEG_ENC_TBL_CNTL 2441 #define UVD_JPEG_ENC_TBL_CNTL__TBL_PEL_SEL__SHIFT 0x0 2442 #define UVD_JPEG_ENC_TBL_CNTL__TBL_TYPE__SHIFT 0x1 2443 #define UVD_JPEG_ENC_TBL_CNTL__TBL_SUBTYPE__SHIFT 0x2 2444 #define UVD_JPEG_ENC_TBL_CNTL__HTBL_CNTLEN__SHIFT 0x4 2445 #define UVD_JPEG_ENC_TBL_CNTL__TBL_PEL_SEL_MASK 0x00000001L 2446 #define UVD_JPEG_ENC_TBL_CNTL__TBL_TYPE_MASK 0x00000002L 2447 #define UVD_JPEG_ENC_TBL_CNTL__TBL_SUBTYPE_MASK 0x0000000CL 2448 #define UVD_JPEG_ENC_TBL_CNTL__HTBL_CNTLEN_MASK 0x00000010L 2449 //UVD_JPEG_ENC_MC_REQ_CNTL 2450 #define UVD_JPEG_ENC_MC_REQ_CNTL__RD_REQ_PRIORITY_MARK__SHIFT 0x0 2451 #define UVD_JPEG_ENC_MC_REQ_CNTL__RD_REQ_PRIORITY_MARK_MASK 0x0000003FL 2452 //UVD_JPEG_ENC_STATUS 2453 #define UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE__SHIFT 0x0 2454 #define UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE__SHIFT 0x1 2455 #define UVD_JPEG_ENC_STATUS__FDCT_IDLE__SHIFT 0x2 2456 #define UVD_JPEG_ENC_STATUS__SCALAR_IDLE__SHIFT 0x3 2457 #define UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE_MASK 0x00000001L 2458 #define UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE_MASK 0x00000002L 2459 #define UVD_JPEG_ENC_STATUS__FDCT_IDLE_MASK 0x00000004L 2460 #define UVD_JPEG_ENC_STATUS__SCALAR_IDLE_MASK 0x00000008L 2461 //UVD_JPEG_ENC_PITCH 2462 #define UVD_JPEG_ENC_PITCH__PITCH_Y__SHIFT 0x0 2463 #define UVD_JPEG_ENC_PITCH__PITCH_UV__SHIFT 0x10 2464 #define UVD_JPEG_ENC_PITCH__PITCH_Y_MASK 0x00000FFFL 2465 #define UVD_JPEG_ENC_PITCH__PITCH_UV_MASK 0x0FFF0000L 2466 //UVD_JPEG_ENC_LUMA_BASE 2467 #define UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE__SHIFT 0x0 2468 #define UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE_MASK 0xFFFFFFFFL 2469 //UVD_JPEG_ENC_CHROMAU_BASE 2470 #define UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE__SHIFT 0x0 2471 #define UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE_MASK 0xFFFFFFFFL 2472 //UVD_JPEG_ENC_CHROMAV_BASE 2473 #define UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE__SHIFT 0x0 2474 #define UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE_MASK 0xFFFFFFFFL 2475 //JPEG_ENC_Y_GFX10_TILING_SURFACE 2476 #define JPEG_ENC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 2477 #define JPEG_ENC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 2478 //JPEG_ENC_UV_GFX10_TILING_SURFACE 2479 #define JPEG_ENC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 2480 #define JPEG_ENC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 2481 //JPEG_ENC_GFX10_ADDR_CONFIG 2482 #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 2483 #define JPEG_ENC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 2484 #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 2485 #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 2486 #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 2487 #define JPEG_ENC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 2488 #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 2489 #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 2490 //JPEG_ENC_ADDR_MODE 2491 #define JPEG_ENC_ADDR_MODE__ADDR_MODE_Y__SHIFT 0x0 2492 #define JPEG_ENC_ADDR_MODE__ADDR_MODE_UV__SHIFT 0x2 2493 #define JPEG_ENC_ADDR_MODE__ADDR_LIB_SEL__SHIFT 0xc 2494 #define JPEG_ENC_ADDR_MODE__ADDR_MODE_Y_MASK 0x00000003L 2495 #define JPEG_ENC_ADDR_MODE__ADDR_MODE_UV_MASK 0x0000000CL 2496 #define JPEG_ENC_ADDR_MODE__ADDR_LIB_SEL_MASK 0x00007000L 2497 //UVD_JPEG_ENC_GPCOM_CMD 2498 #define UVD_JPEG_ENC_GPCOM_CMD__CMD__SHIFT 0x1 2499 #define UVD_JPEG_ENC_GPCOM_CMD__CMD_MASK 0x0000000EL 2500 //UVD_JPEG_ENC_GPCOM_DATA0 2501 #define UVD_JPEG_ENC_GPCOM_DATA0__DATA0__SHIFT 0x0 2502 #define UVD_JPEG_ENC_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL 2503 //UVD_JPEG_ENC_GPCOM_DATA1 2504 #define UVD_JPEG_ENC_GPCOM_DATA1__DATA1__SHIFT 0x0 2505 #define UVD_JPEG_ENC_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL 2506 //UVD_JPEG_TBL_DAT0 2507 #define UVD_JPEG_TBL_DAT0__TBL_DAT_31_0__SHIFT 0x0 2508 #define UVD_JPEG_TBL_DAT0__TBL_DAT_31_0_MASK 0xFFFFFFFFL 2509 //UVD_JPEG_TBL_DAT1 2510 #define UVD_JPEG_TBL_DAT1__TBL_DAT_63_32__SHIFT 0x0 2511 #define UVD_JPEG_TBL_DAT1__TBL_DAT_63_32_MASK 0xFFFFFFFFL 2512 //UVD_JPEG_TBL_IDX 2513 #define UVD_JPEG_TBL_IDX__TBL_IDX__SHIFT 0x0 2514 #define UVD_JPEG_TBL_IDX__TBL_IDX_MASK 0x000000FFL 2515 //UVD_JPEG_ENC_CGC_CNTL 2516 #define UVD_JPEG_ENC_CGC_CNTL__CGC_EN__SHIFT 0x0 2517 #define UVD_JPEG_ENC_CGC_CNTL__CGC_EN_MASK 0x00000001L 2518 //UVD_JPEG_ENC_SCRATCH0 2519 #define UVD_JPEG_ENC_SCRATCH0__SCRATCH0__SHIFT 0x0 2520 #define UVD_JPEG_ENC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 2521 //UVD_JPEG_ENC_SOFT_RST 2522 #define UVD_JPEG_ENC_SOFT_RST__SOFT_RST__SHIFT 0x0 2523 #define UVD_JPEG_ENC_SOFT_RST__RESET_STATUS__SHIFT 0x10 2524 #define UVD_JPEG_ENC_SOFT_RST__SOFT_RST_MASK 0x00000001L 2525 #define UVD_JPEG_ENC_SOFT_RST__RESET_STATUS_MASK 0x00010000L 2526 2527 2528 // addressBlock: uvd0_uvd_jrbc_dec 2529 //UVD_JRBC_RB_WPTR 2530 #define UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4 2531 #define UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 2532 //UVD_JRBC_RB_CNTL 2533 #define UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 2534 #define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 2535 #define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 2536 #define UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L 2537 #define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L 2538 #define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L 2539 //UVD_JRBC_IB_SIZE 2540 #define UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT 0x4 2541 #define UVD_JRBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 2542 //UVD_JRBC_URGENT_CNTL 2543 #define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 2544 #define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 2545 //UVD_JRBC_RB_REF_DATA 2546 #define UVD_JRBC_RB_REF_DATA__REF_DATA__SHIFT 0x0 2547 #define UVD_JRBC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 2548 //UVD_JRBC_RB_COND_RD_TIMER 2549 #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 2550 #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 2551 #define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 2552 #define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 2553 #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 2554 #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 2555 #define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 2556 #define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 2557 //UVD_JRBC_SOFT_RESET 2558 #define UVD_JRBC_SOFT_RESET__RESET__SHIFT 0x0 2559 #define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 2560 #define UVD_JRBC_SOFT_RESET__RESET_MASK 0x00000001L 2561 #define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L 2562 //UVD_JRBC_STATUS 2563 #define UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT 0x0 2564 #define UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT 0x1 2565 #define UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 2566 #define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 2567 #define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 2568 #define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 2569 #define UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 2570 #define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 2571 #define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 2572 #define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 2573 #define UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa 2574 #define UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT 0xb 2575 #define UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT 0xc 2576 #define UVD_JRBC_STATUS__INT_EN__SHIFT 0x10 2577 #define UVD_JRBC_STATUS__INT_ACK__SHIFT 0x11 2578 #define UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L 2579 #define UVD_JRBC_STATUS__IB_JOB_DONE_MASK 0x00000002L 2580 #define UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L 2581 #define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L 2582 #define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L 2583 #define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L 2584 #define UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L 2585 #define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L 2586 #define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L 2587 #define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L 2588 #define UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L 2589 #define UVD_JRBC_STATUS__PREEMPT_STATUS_MASK 0x00000800L 2590 #define UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L 2591 #define UVD_JRBC_STATUS__INT_EN_MASK 0x00010000L 2592 #define UVD_JRBC_STATUS__INT_ACK_MASK 0x00020000L 2593 //UVD_JRBC_RB_RPTR 2594 #define UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4 2595 #define UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 2596 //UVD_JRBC_RB_BUF_STATUS 2597 #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 2598 #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 2599 #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 2600 #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL 2601 #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L 2602 #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L 2603 //UVD_JRBC_IB_BUF_STATUS 2604 #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 2605 #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 2606 #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 2607 #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL 2608 #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L 2609 #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L 2610 //UVD_JRBC_IB_SIZE_UPDATE 2611 #define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 2612 #define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 2613 //UVD_JRBC_IB_COND_RD_TIMER 2614 #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 2615 #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 2616 #define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 2617 #define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 2618 #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 2619 #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 2620 #define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 2621 #define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 2622 //UVD_JRBC_IB_REF_DATA 2623 #define UVD_JRBC_IB_REF_DATA__REF_DATA__SHIFT 0x0 2624 #define UVD_JRBC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 2625 //UVD_JPEG_PREEMPT_CMD 2626 #define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 2627 #define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 2628 #define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 2629 #define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L 2630 #define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L 2631 #define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L 2632 //UVD_JPEG_PREEMPT_FENCE_DATA0 2633 #define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 2634 #define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL 2635 //UVD_JPEG_PREEMPT_FENCE_DATA1 2636 #define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 2637 #define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL 2638 //UVD_JRBC_RB_SIZE 2639 #define UVD_JRBC_RB_SIZE__RB_SIZE__SHIFT 0x4 2640 #define UVD_JRBC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L 2641 //UVD_JRBC_SCRATCH0 2642 #define UVD_JRBC_SCRATCH0__SCRATCH0__SHIFT 0x0 2643 #define UVD_JRBC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 2644 2645 2646 // addressBlock: uvd0_uvd_jrbc_enc_dec 2647 //UVD_JRBC_ENC_RB_WPTR 2648 #define UVD_JRBC_ENC_RB_WPTR__RB_WPTR__SHIFT 0x4 2649 #define UVD_JRBC_ENC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 2650 //UVD_JRBC_ENC_RB_CNTL 2651 #define UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 2652 #define UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 2653 #define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 2654 #define UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L 2655 #define UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L 2656 #define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L 2657 //UVD_JRBC_ENC_IB_SIZE 2658 #define UVD_JRBC_ENC_IB_SIZE__IB_SIZE__SHIFT 0x4 2659 #define UVD_JRBC_ENC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 2660 //UVD_JRBC_ENC_URGENT_CNTL 2661 #define UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 2662 #define UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 2663 //UVD_JRBC_ENC_RB_REF_DATA 2664 #define UVD_JRBC_ENC_RB_REF_DATA__REF_DATA__SHIFT 0x0 2665 #define UVD_JRBC_ENC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 2666 //UVD_JRBC_ENC_RB_COND_RD_TIMER 2667 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 2668 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 2669 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 2670 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 2671 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 2672 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 2673 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 2674 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 2675 //UVD_JRBC_ENC_SOFT_RESET 2676 #define UVD_JRBC_ENC_SOFT_RESET__RESET__SHIFT 0x0 2677 #define UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 2678 #define UVD_JRBC_ENC_SOFT_RESET__RESET_MASK 0x00000001L 2679 #define UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L 2680 //UVD_JRBC_ENC_STATUS 2681 #define UVD_JRBC_ENC_STATUS__RB_JOB_DONE__SHIFT 0x0 2682 #define UVD_JRBC_ENC_STATUS__IB_JOB_DONE__SHIFT 0x1 2683 #define UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 2684 #define UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 2685 #define UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 2686 #define UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 2687 #define UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 2688 #define UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 2689 #define UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 2690 #define UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 2691 #define UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS__SHIFT 0xa 2692 #define UVD_JRBC_ENC_STATUS__PREEMPT_STATUS__SHIFT 0xb 2693 #define UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS__SHIFT 0xc 2694 #define UVD_JRBC_ENC_STATUS__INT_EN__SHIFT 0x10 2695 #define UVD_JRBC_ENC_STATUS__INT_ACK__SHIFT 0x11 2696 #define UVD_JRBC_ENC_STATUS__RB_JOB_DONE_MASK 0x00000001L 2697 #define UVD_JRBC_ENC_STATUS__IB_JOB_DONE_MASK 0x00000002L 2698 #define UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L 2699 #define UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L 2700 #define UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L 2701 #define UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L 2702 #define UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L 2703 #define UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L 2704 #define UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L 2705 #define UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L 2706 #define UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L 2707 #define UVD_JRBC_ENC_STATUS__PREEMPT_STATUS_MASK 0x00000800L 2708 #define UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L 2709 #define UVD_JRBC_ENC_STATUS__INT_EN_MASK 0x00010000L 2710 #define UVD_JRBC_ENC_STATUS__INT_ACK_MASK 0x00020000L 2711 //UVD_JRBC_ENC_RB_RPTR 2712 #define UVD_JRBC_ENC_RB_RPTR__RB_RPTR__SHIFT 0x4 2713 #define UVD_JRBC_ENC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 2714 //UVD_JRBC_ENC_RB_BUF_STATUS 2715 #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 2716 #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 2717 #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 2718 #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL 2719 #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L 2720 #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L 2721 //UVD_JRBC_ENC_IB_BUF_STATUS 2722 #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 2723 #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 2724 #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 2725 #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL 2726 #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L 2727 #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L 2728 //UVD_JRBC_ENC_IB_SIZE_UPDATE 2729 #define UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 2730 #define UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 2731 //UVD_JRBC_ENC_IB_COND_RD_TIMER 2732 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 2733 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 2734 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 2735 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 2736 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 2737 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 2738 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 2739 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 2740 //UVD_JRBC_ENC_IB_REF_DATA 2741 #define UVD_JRBC_ENC_IB_REF_DATA__REF_DATA__SHIFT 0x0 2742 #define UVD_JRBC_ENC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 2743 //UVD_JPEG_ENC_PREEMPT_CMD 2744 #define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 2745 #define UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 2746 #define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 2747 #define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L 2748 #define UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L 2749 #define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L 2750 //UVD_JPEG_ENC_PREEMPT_FENCE_DATA0 2751 #define UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 2752 #define UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL 2753 //UVD_JPEG_ENC_PREEMPT_FENCE_DATA1 2754 #define UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 2755 #define UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL 2756 //UVD_JRBC_ENC_RB_SIZE 2757 #define UVD_JRBC_ENC_RB_SIZE__RB_SIZE__SHIFT 0x4 2758 #define UVD_JRBC_ENC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L 2759 //UVD_JRBC_ENC_SCRATCH0 2760 #define UVD_JRBC_ENC_SCRATCH0__SCRATCH0__SHIFT 0x0 2761 #define UVD_JRBC_ENC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 2762 2763 2764 // addressBlock: uvd0_uvd_mpcdec 2765 //UVD_MP_SWAP_CNTL 2766 #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0 2767 #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2 2768 #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4 2769 #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6 2770 #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8 2771 #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa 2772 #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc 2773 #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe 2774 #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10 2775 #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12 2776 #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14 2777 #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16 2778 #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18 2779 #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a 2780 #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c 2781 #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e 2782 #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x00000003L 2783 #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0x0000000CL 2784 #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x00000030L 2785 #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0x000000C0L 2786 #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x00000300L 2787 #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0x00000C00L 2788 #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x00003000L 2789 #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0x0000C000L 2790 #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x00030000L 2791 #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0x000C0000L 2792 #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x00300000L 2793 #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0x00C00000L 2794 #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x03000000L 2795 #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0x0C000000L 2796 #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000L 2797 #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xC0000000L 2798 //UVD_MP_SWAP_CNTL2 2799 #define UVD_MP_SWAP_CNTL2__MP_REF16_MC_SWAP__SHIFT 0x0 2800 #define UVD_MP_SWAP_CNTL2__MP_REF16_MC_SWAP_MASK 0x00000003L 2801 //UVD_MPC_LUMA_SRCH 2802 #define UVD_MPC_LUMA_SRCH__CNTR__SHIFT 0x0 2803 #define UVD_MPC_LUMA_SRCH__CNTR_MASK 0xFFFFFFFFL 2804 //UVD_MPC_LUMA_HIT 2805 #define UVD_MPC_LUMA_HIT__CNTR__SHIFT 0x0 2806 #define UVD_MPC_LUMA_HIT__CNTR_MASK 0xFFFFFFFFL 2807 //UVD_MPC_LUMA_HITPEND 2808 #define UVD_MPC_LUMA_HITPEND__CNTR__SHIFT 0x0 2809 #define UVD_MPC_LUMA_HITPEND__CNTR_MASK 0xFFFFFFFFL 2810 //UVD_MPC_CHROMA_SRCH 2811 #define UVD_MPC_CHROMA_SRCH__CNTR__SHIFT 0x0 2812 #define UVD_MPC_CHROMA_SRCH__CNTR_MASK 0xFFFFFFFFL 2813 //UVD_MPC_CHROMA_HIT 2814 #define UVD_MPC_CHROMA_HIT__CNTR__SHIFT 0x0 2815 #define UVD_MPC_CHROMA_HIT__CNTR_MASK 0xFFFFFFFFL 2816 //UVD_MPC_CHROMA_HITPEND 2817 #define UVD_MPC_CHROMA_HITPEND__CNTR__SHIFT 0x0 2818 #define UVD_MPC_CHROMA_HITPEND__CNTR_MASK 0xFFFFFFFFL 2819 //UVD_MPC_CNTL 2820 #define UVD_MPC_CNTL__BLK_RST__SHIFT 0x0 2821 #define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3 2822 #define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6 2823 #define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10 2824 #define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12 2825 #define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP__SHIFT 0x13 2826 #define UVD_MPC_CNTL__TEST_MODE_EN__SHIFT 0x14 2827 #define UVD_MPC_CNTL__BLK_RST_MASK 0x00000001L 2828 #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L 2829 #define UVD_MPC_CNTL__PERF_RST_MASK 0x00000040L 2830 #define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x00030000L 2831 #define UVD_MPC_CNTL__URGENT_EN_MASK 0x00040000L 2832 #define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP_MASK 0x00080000L 2833 #define UVD_MPC_CNTL__TEST_MODE_EN_MASK 0x00100000L 2834 //UVD_MPC_PITCH 2835 #define UVD_MPC_PITCH__LUMA_PITCH__SHIFT 0x0 2836 #define UVD_MPC_PITCH__LUMA_PITCH_MASK 0x000007FFL 2837 //UVD_MPC_SET_MUXA0 2838 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 2839 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 2840 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc 2841 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 2842 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 2843 #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003FL 2844 #define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000FC0L 2845 #define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003F000L 2846 #define UVD_MPC_SET_MUXA0__VARA_3_MASK 0x00FC0000L 2847 #define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3F000000L 2848 //UVD_MPC_SET_MUXA1 2849 #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 2850 #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 2851 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc 2852 #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x0000003FL 2853 #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0x00000FC0L 2854 #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x0003F000L 2855 //UVD_MPC_SET_MUXB0 2856 #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 2857 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 2858 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc 2859 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 2860 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 2861 #define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x0000003FL 2862 #define UVD_MPC_SET_MUXB0__VARB_1_MASK 0x00000FC0L 2863 #define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x0003F000L 2864 #define UVD_MPC_SET_MUXB0__VARB_3_MASK 0x00FC0000L 2865 #define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3F000000L 2866 //UVD_MPC_SET_MUXB1 2867 #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 2868 #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 2869 #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc 2870 #define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x0000003FL 2871 #define UVD_MPC_SET_MUXB1__VARB_6_MASK 0x00000FC0L 2872 #define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x0003F000L 2873 //UVD_MPC_SET_MUX 2874 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 2875 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 2876 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 2877 #define UVD_MPC_SET_MUX__SET_0_MASK 0x00000007L 2878 #define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L 2879 #define UVD_MPC_SET_MUX__SET_2_MASK 0x000001C0L 2880 //UVD_MPC_SET_ALU 2881 #define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0 2882 #define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4 2883 #define UVD_MPC_SET_ALU__FUNCT_MASK 0x00000007L 2884 #define UVD_MPC_SET_ALU__OPERAND_MASK 0x00000FF0L 2885 //UVD_MPC_PERF0 2886 #define UVD_MPC_PERF0__MAX_LAT__SHIFT 0x0 2887 #define UVD_MPC_PERF0__MAX_LAT_MASK 0x000003FFL 2888 //UVD_MPC_PERF1 2889 #define UVD_MPC_PERF1__AVE_LAT__SHIFT 0x0 2890 #define UVD_MPC_PERF1__AVE_LAT_MASK 0x000003FFL 2891 //UVD_MPC_IND_INDEX 2892 #define UVD_MPC_IND_INDEX__INDEX__SHIFT 0x0 2893 #define UVD_MPC_IND_INDEX__INDEX_MASK 0x000001FFL 2894 //UVD_MPC_IND_DATA 2895 #define UVD_MPC_IND_DATA__DATA__SHIFT 0x0 2896 #define UVD_MPC_IND_DATA__DATA_MASK 0xFFFFFFFFL 2897 2898 2899 // addressBlock: uvd0_uvd_pg_dec 2900 //UVD_PGFSM_CONFIG 2901 #define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 0x0 2902 #define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 0x2 2903 #define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 0x4 2904 #define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 0x6 2905 #define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 0x8 2906 #define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 0xa 2907 #define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 0xc 2908 #define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 0xe 2909 #define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 0x10 2910 #define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 0x12 2911 #define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT 0x14 2912 #define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT 0x16 2913 #define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG_MASK 0x00000003L 2914 #define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG_MASK 0x0000000CL 2915 #define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG_MASK 0x00000030L 2916 #define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG_MASK 0x000000C0L 2917 #define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG_MASK 0x00000300L 2918 #define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG_MASK 0x00000C00L 2919 #define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG_MASK 0x00003000L 2920 #define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG_MASK 0x0000C000L 2921 #define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG_MASK 0x00030000L 2922 #define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG_MASK 0x000C0000L 2923 #define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG_MASK 0x00300000L 2924 #define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG_MASK 0x00C00000L 2925 //UVD_PGFSM_STATUS 2926 #define UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 0x0 2927 #define UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 0x2 2928 #define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 0x4 2929 #define UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 0x6 2930 #define UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 0x8 2931 #define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 0xa 2932 #define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 0xc 2933 #define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 0xe 2934 #define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 0x10 2935 #define UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 0x12 2936 #define UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT 0x14 2937 #define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT 0x16 2938 #define UVD_PGFSM_STATUS__UVDM_PWR_STATUS_MASK 0x00000003L 2939 #define UVD_PGFSM_STATUS__UVDU_PWR_STATUS_MASK 0x0000000CL 2940 #define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 0x00000030L 2941 #define UVD_PGFSM_STATUS__UVDC_PWR_STATUS_MASK 0x000000C0L 2942 #define UVD_PGFSM_STATUS__UVDB_PWR_STATUS_MASK 0x00000300L 2943 #define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS_MASK 0x00000C00L 2944 #define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS_MASK 0x00003000L 2945 #define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS_MASK 0x0000C000L 2946 #define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS_MASK 0x00030000L 2947 #define UVD_PGFSM_STATUS__UVDE_PWR_STATUS_MASK 0x000C0000L 2948 #define UVD_PGFSM_STATUS__UVDW_PWR_STATUS_MASK 0x00300000L 2949 #define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK 0x00C00000L 2950 //UVD_POWER_STATUS 2951 #define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 2952 #define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2 2953 #define UVD_POWER_STATUS__UVD_CG_MODE__SHIFT 0x4 2954 #define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8 2955 #define UVD_POWER_STATUS__RBC_SNOOP_DIS__SHIFT 0x9 2956 #define UVD_POWER_STATUS__SW_RB_SNOOP_DIS__SHIFT 0xb 2957 #define UVD_POWER_STATUS__STALL_DPG_POWER_UP__SHIFT 0x1f 2958 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L 2959 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L 2960 #define UVD_POWER_STATUS__UVD_CG_MODE_MASK 0x00000030L 2961 #define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L 2962 #define UVD_POWER_STATUS__RBC_SNOOP_DIS_MASK 0x00000200L 2963 #define UVD_POWER_STATUS__SW_RB_SNOOP_DIS_MASK 0x00000800L 2964 #define UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK 0x80000000L 2965 //UVD_PG_IND_INDEX 2966 #define UVD_PG_IND_INDEX__INDEX__SHIFT 0x0 2967 #define UVD_PG_IND_INDEX__INDEX_MASK 0x0000003FL 2968 //UVD_PG_IND_DATA 2969 #define UVD_PG_IND_DATA__DATA__SHIFT 0x0 2970 #define UVD_PG_IND_DATA__DATA_MASK 0xFFFFFFFFL 2971 //CC_UVD_HARVESTING 2972 #define CC_UVD_HARVESTING__MMSCH_DISABLE__SHIFT 0x0 2973 #define CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1 2974 #define CC_UVD_HARVESTING__MMSCH_DISABLE_MASK 0x00000001L 2975 #define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L 2976 //UVD_JPEG_POWER_STATUS 2977 #define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS__SHIFT 0x0 2978 #define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE__SHIFT 0x4 2979 #define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS__SHIFT 0x8 2980 #define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS__SHIFT 0x9 2981 #define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP__SHIFT 0x1f 2982 #define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK 0x00000001L 2983 #define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK 0x00000010L 2984 #define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS_MASK 0x00000100L 2985 #define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS_MASK 0x00000200L 2986 #define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP_MASK 0x80000000L 2987 //UVD_DPG_LMA_CTL 2988 #define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0 2989 #define UVD_DPG_LMA_CTL__MASK_EN__SHIFT 0x1 2990 #define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT 0x2 2991 #define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT 0x4 2992 #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10 2993 #define UVD_DPG_LMA_CTL__READ_WRITE_MASK 0x00000001L 2994 #define UVD_DPG_LMA_CTL__MASK_EN_MASK 0x00000002L 2995 #define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT_MASK 0x00000004L 2996 #define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L 2997 #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR_MASK 0xFFFF0000L 2998 //UVD_DPG_LMA_DATA 2999 #define UVD_DPG_LMA_DATA__LMA_DATA__SHIFT 0x0 3000 #define UVD_DPG_LMA_DATA__LMA_DATA_MASK 0xFFFFFFFFL 3001 //UVD_DPG_LMA_MASK 3002 #define UVD_DPG_LMA_MASK__LMA_MASK__SHIFT 0x0 3003 #define UVD_DPG_LMA_MASK__LMA_MASK_MASK 0xFFFFFFFFL 3004 //UVD_DPG_PAUSE 3005 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ__SHIFT 0x0 3006 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1 3007 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2 3008 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK__SHIFT 0x3 3009 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK 0x00000001L 3010 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK 0x00000002L 3011 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L 3012 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L 3013 //UVD_SCRATCH1 3014 #define UVD_SCRATCH1__SCRATCH1_DATA__SHIFT 0x0 3015 #define UVD_SCRATCH1__SCRATCH1_DATA_MASK 0xFFFFFFFFL 3016 //UVD_SCRATCH2 3017 #define UVD_SCRATCH2__SCRATCH2_DATA__SHIFT 0x0 3018 #define UVD_SCRATCH2__SCRATCH2_DATA_MASK 0xFFFFFFFFL 3019 //UVD_SCRATCH3 3020 #define UVD_SCRATCH3__SCRATCH3_DATA__SHIFT 0x0 3021 #define UVD_SCRATCH3__SCRATCH3_DATA_MASK 0xFFFFFFFFL 3022 //UVD_SCRATCH4 3023 #define UVD_SCRATCH4__SCRATCH4_DATA__SHIFT 0x0 3024 #define UVD_SCRATCH4__SCRATCH4_DATA_MASK 0xFFFFFFFFL 3025 //UVD_SCRATCH5 3026 #define UVD_SCRATCH5__SCRATCH5_DATA__SHIFT 0x0 3027 #define UVD_SCRATCH5__SCRATCH5_DATA_MASK 0xFFFFFFFFL 3028 //UVD_SCRATCH6 3029 #define UVD_SCRATCH6__SCRATCH6_DATA__SHIFT 0x0 3030 #define UVD_SCRATCH6__SCRATCH6_DATA_MASK 0xFFFFFFFFL 3031 //UVD_SCRATCH7 3032 #define UVD_SCRATCH7__SCRATCH7_DATA__SHIFT 0x0 3033 #define UVD_SCRATCH7__SCRATCH7_DATA_MASK 0xFFFFFFFFL 3034 //UVD_SCRATCH8 3035 #define UVD_SCRATCH8__SCRATCH8_DATA__SHIFT 0x0 3036 #define UVD_SCRATCH8__SCRATCH8_DATA_MASK 0xFFFFFFFFL 3037 //UVD_SCRATCH9 3038 #define UVD_SCRATCH9__SCRATCH9_DATA__SHIFT 0x0 3039 #define UVD_SCRATCH9__SCRATCH9_DATA_MASK 0xFFFFFFFFL 3040 //UVD_SCRATCH10 3041 #define UVD_SCRATCH10__SCRATCH10_DATA__SHIFT 0x0 3042 #define UVD_SCRATCH10__SCRATCH10_DATA_MASK 0xFFFFFFFFL 3043 //UVD_SCRATCH11 3044 #define UVD_SCRATCH11__SCRATCH11_DATA__SHIFT 0x0 3045 #define UVD_SCRATCH11__SCRATCH11_DATA_MASK 0xFFFFFFFFL 3046 //UVD_SCRATCH12 3047 #define UVD_SCRATCH12__SCRATCH12_DATA__SHIFT 0x0 3048 #define UVD_SCRATCH12__SCRATCH12_DATA_MASK 0xFFFFFFFFL 3049 //UVD_SCRATCH13 3050 #define UVD_SCRATCH13__SCRATCH13_DATA__SHIFT 0x0 3051 #define UVD_SCRATCH13__SCRATCH13_DATA_MASK 0xFFFFFFFFL 3052 //UVD_SCRATCH14 3053 #define UVD_SCRATCH14__SCRATCH14_DATA__SHIFT 0x0 3054 #define UVD_SCRATCH14__SCRATCH14_DATA_MASK 0xFFFFFFFFL 3055 //UVD_FREE_COUNTER_REG 3056 #define UVD_FREE_COUNTER_REG__FREE_COUNTER__SHIFT 0x0 3057 #define UVD_FREE_COUNTER_REG__FREE_COUNTER_MASK 0xFFFFFFFFL 3058 //UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 3059 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3060 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3061 //UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 3062 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3063 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3064 //UVD_DPG_VCPU_CACHE_OFFSET0 3065 #define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 3066 #define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01FFFFFFL 3067 //UVD_DPG_LMI_VCPU_CACHE_VMID 3068 #define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 3069 #define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL 3070 //UVD_PF_STATUS 3071 #define UVD_PF_STATUS__JPEG_PF_OCCURED__SHIFT 0x0 3072 #define UVD_PF_STATUS__NJ_PF_OCCURED__SHIFT 0x1 3073 #define UVD_PF_STATUS__ENCODER0_PF_OCCURED__SHIFT 0x2 3074 #define UVD_PF_STATUS__ENCODER1_PF_OCCURED__SHIFT 0x3 3075 #define UVD_PF_STATUS__ENCODER2_PF_OCCURED__SHIFT 0x4 3076 #define UVD_PF_STATUS__ENCODER3_PF_OCCURED__SHIFT 0x5 3077 #define UVD_PF_STATUS__ENCODER4_PF_OCCURED__SHIFT 0x6 3078 #define UVD_PF_STATUS__EJPEG_PF_OCCURED__SHIFT 0x7 3079 #define UVD_PF_STATUS__JPEG_PF_CLEAR__SHIFT 0x8 3080 #define UVD_PF_STATUS__NJ_PF_CLEAR__SHIFT 0x9 3081 #define UVD_PF_STATUS__ENCODER0_PF_CLEAR__SHIFT 0xa 3082 #define UVD_PF_STATUS__ENCODER1_PF_CLEAR__SHIFT 0xb 3083 #define UVD_PF_STATUS__ENCODER2_PF_CLEAR__SHIFT 0xc 3084 #define UVD_PF_STATUS__ENCODER3_PF_CLEAR__SHIFT 0xd 3085 #define UVD_PF_STATUS__ENCODER4_PF_CLEAR__SHIFT 0xe 3086 #define UVD_PF_STATUS__EJPEG_PF_CLEAR__SHIFT 0xf 3087 #define UVD_PF_STATUS__NJ_ATM_PF_OCCURED__SHIFT 0x10 3088 #define UVD_PF_STATUS__DJ_ATM_PF_OCCURED__SHIFT 0x11 3089 #define UVD_PF_STATUS__EJ_ATM_PF_OCCURED__SHIFT 0x12 3090 #define UVD_PF_STATUS__JPEG_PF_OCCURED_MASK 0x00000001L 3091 #define UVD_PF_STATUS__NJ_PF_OCCURED_MASK 0x00000002L 3092 #define UVD_PF_STATUS__ENCODER0_PF_OCCURED_MASK 0x00000004L 3093 #define UVD_PF_STATUS__ENCODER1_PF_OCCURED_MASK 0x00000008L 3094 #define UVD_PF_STATUS__ENCODER2_PF_OCCURED_MASK 0x00000010L 3095 #define UVD_PF_STATUS__ENCODER3_PF_OCCURED_MASK 0x00000020L 3096 #define UVD_PF_STATUS__ENCODER4_PF_OCCURED_MASK 0x00000040L 3097 #define UVD_PF_STATUS__EJPEG_PF_OCCURED_MASK 0x00000080L 3098 #define UVD_PF_STATUS__JPEG_PF_CLEAR_MASK 0x00000100L 3099 #define UVD_PF_STATUS__NJ_PF_CLEAR_MASK 0x00000200L 3100 #define UVD_PF_STATUS__ENCODER0_PF_CLEAR_MASK 0x00000400L 3101 #define UVD_PF_STATUS__ENCODER1_PF_CLEAR_MASK 0x00000800L 3102 #define UVD_PF_STATUS__ENCODER2_PF_CLEAR_MASK 0x00001000L 3103 #define UVD_PF_STATUS__ENCODER3_PF_CLEAR_MASK 0x00002000L 3104 #define UVD_PF_STATUS__ENCODER4_PF_CLEAR_MASK 0x00004000L 3105 #define UVD_PF_STATUS__EJPEG_PF_CLEAR_MASK 0x00008000L 3106 #define UVD_PF_STATUS__NJ_ATM_PF_OCCURED_MASK 0x00010000L 3107 #define UVD_PF_STATUS__DJ_ATM_PF_OCCURED_MASK 0x00020000L 3108 #define UVD_PF_STATUS__EJ_ATM_PF_OCCURED_MASK 0x00040000L 3109 //UVD_FW_VERSION 3110 #define UVD_FW_VERSION__FW_VERSION__SHIFT 0x0 3111 #define UVD_FW_VERSION__FW_VERSION_MASK 0xFFFFFFFFL 3112 //UVD_DPG_CLK_EN_VCPU_REPORT 3113 #define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN__SHIFT 0x0 3114 #define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT__SHIFT 0x1 3115 #define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN_MASK 0x00000001L 3116 #define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT_MASK 0x000000FEL 3117 //UVD_GFX8_ADDR_CONFIG 3118 #define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 3119 #define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L 3120 //UVD_GFX10_ADDR_CONFIG 3121 #define UVD_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 3122 #define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 3123 #define UVD_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 3124 #define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 3125 #define UVD_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 3126 #define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 3127 #define UVD_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 3128 #define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 3129 //UVD_GPCNT2_CNTL 3130 #define UVD_GPCNT2_CNTL__CLR__SHIFT 0x0 3131 #define UVD_GPCNT2_CNTL__START__SHIFT 0x1 3132 #define UVD_GPCNT2_CNTL__COUNTUP__SHIFT 0x2 3133 #define UVD_GPCNT2_CNTL__CLR_MASK 0x00000001L 3134 #define UVD_GPCNT2_CNTL__START_MASK 0x00000002L 3135 #define UVD_GPCNT2_CNTL__COUNTUP_MASK 0x00000004L 3136 //UVD_GPCNT2_TARGET_LOWER 3137 #define UVD_GPCNT2_TARGET_LOWER__TARGET__SHIFT 0x0 3138 #define UVD_GPCNT2_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL 3139 //UVD_GPCNT2_STATUS_LOWER 3140 #define UVD_GPCNT2_STATUS_LOWER__COUNT__SHIFT 0x0 3141 #define UVD_GPCNT2_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL 3142 //UVD_GPCNT2_TARGET_UPPER 3143 #define UVD_GPCNT2_TARGET_UPPER__TARGET__SHIFT 0x0 3144 #define UVD_GPCNT2_TARGET_UPPER__TARGET_MASK 0x0000FFFFL 3145 //UVD_GPCNT2_STATUS_UPPER 3146 #define UVD_GPCNT2_STATUS_UPPER__COUNT__SHIFT 0x0 3147 #define UVD_GPCNT2_STATUS_UPPER__COUNT_MASK 0x0000FFFFL 3148 //UVD_GPCNT3_CNTL 3149 #define UVD_GPCNT3_CNTL__CLR__SHIFT 0x0 3150 #define UVD_GPCNT3_CNTL__START__SHIFT 0x1 3151 #define UVD_GPCNT3_CNTL__COUNTUP__SHIFT 0x2 3152 #define UVD_GPCNT3_CNTL__FREQ__SHIFT 0x3 3153 #define UVD_GPCNT3_CNTL__DIV__SHIFT 0xa 3154 #define UVD_GPCNT3_CNTL__CLR_MASK 0x00000001L 3155 #define UVD_GPCNT3_CNTL__START_MASK 0x00000002L 3156 #define UVD_GPCNT3_CNTL__COUNTUP_MASK 0x00000004L 3157 #define UVD_GPCNT3_CNTL__FREQ_MASK 0x000003F8L 3158 #define UVD_GPCNT3_CNTL__DIV_MASK 0x0001FC00L 3159 //UVD_GPCNT3_TARGET_LOWER 3160 #define UVD_GPCNT3_TARGET_LOWER__TARGET__SHIFT 0x0 3161 #define UVD_GPCNT3_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL 3162 //UVD_GPCNT3_STATUS_LOWER 3163 #define UVD_GPCNT3_STATUS_LOWER__COUNT__SHIFT 0x0 3164 #define UVD_GPCNT3_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL 3165 //UVD_GPCNT3_TARGET_UPPER 3166 #define UVD_GPCNT3_TARGET_UPPER__TARGET__SHIFT 0x0 3167 #define UVD_GPCNT3_TARGET_UPPER__TARGET_MASK 0x0000FFFFL 3168 //UVD_GPCNT3_STATUS_UPPER 3169 #define UVD_GPCNT3_STATUS_UPPER__COUNT__SHIFT 0x0 3170 #define UVD_GPCNT3_STATUS_UPPER__COUNT_MASK 0x0000FFFFL 3171 //UVD_VCLK_DS_CNTL 3172 #define UVD_VCLK_DS_CNTL__VCLK_DS_EN__SHIFT 0x0 3173 #define UVD_VCLK_DS_CNTL__VCLK_DS_STATUS__SHIFT 0x4 3174 #define UVD_VCLK_DS_CNTL__VCLK_DS_HYSTERESIS_CNT__SHIFT 0x10 3175 #define UVD_VCLK_DS_CNTL__VCLK_DS_EN_MASK 0x00000001L 3176 #define UVD_VCLK_DS_CNTL__VCLK_DS_STATUS_MASK 0x00000010L 3177 #define UVD_VCLK_DS_CNTL__VCLK_DS_HYSTERESIS_CNT_MASK 0xFFFF0000L 3178 //UVD_DCLK_DS_CNTL 3179 #define UVD_DCLK_DS_CNTL__DCLK_DS_EN__SHIFT 0x0 3180 #define UVD_DCLK_DS_CNTL__DCLK_DS_STATUS__SHIFT 0x4 3181 #define UVD_DCLK_DS_CNTL__DCLK_DS_HYSTERESIS_CNT__SHIFT 0x10 3182 #define UVD_DCLK_DS_CNTL__DCLK_DS_EN_MASK 0x00000001L 3183 #define UVD_DCLK_DS_CNTL__DCLK_DS_STATUS_MASK 0x00000010L 3184 #define UVD_DCLK_DS_CNTL__DCLK_DS_HYSTERESIS_CNT_MASK 0xFFFF0000L 3185 //UVD_RAS_VCPU_VCODEC_STATUS 3186 #define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_VF__SHIFT 0x0 3187 #define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_PF__SHIFT 0x1f 3188 #define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_VF_MASK 0x7FFFFFFFL 3189 #define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_PF_MASK 0x80000000L 3190 //UVD_RAS_MMSCH_FATAL_ERROR 3191 #define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_VF__SHIFT 0x0 3192 #define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_PF__SHIFT 0x1f 3193 #define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_VF_MASK 0x7FFFFFFFL 3194 #define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_PF_MASK 0x80000000L 3195 //UVD_RAS_JPEG0_STATUS 3196 #define UVD_RAS_JPEG0_STATUS__POISONED_VF__SHIFT 0x0 3197 #define UVD_RAS_JPEG0_STATUS__POISONED_PF__SHIFT 0x1f 3198 #define UVD_RAS_JPEG0_STATUS__POISONED_VF_MASK 0x7FFFFFFFL 3199 #define UVD_RAS_JPEG0_STATUS__POISONED_PF_MASK 0x80000000L 3200 //UVD_RAS_JPEG1_STATUS 3201 #define UVD_RAS_JPEG1_STATUS__POISONED_VF__SHIFT 0x0 3202 #define UVD_RAS_JPEG1_STATUS__POISONED_PF__SHIFT 0x1f 3203 #define UVD_RAS_JPEG1_STATUS__POISONED_VF_MASK 0x7FFFFFFFL 3204 #define UVD_RAS_JPEG1_STATUS__POISONED_PF_MASK 0x80000000L 3205 //UVD_RAS_CNTL_PMI_ARB 3206 #define UVD_RAS_CNTL_PMI_ARB__STAT_VCPU_VCODEC__SHIFT 0x0 3207 #define UVD_RAS_CNTL_PMI_ARB__ACK_VCPU_VCODEC__SHIFT 0x1 3208 #define UVD_RAS_CNTL_PMI_ARB__STAT_MMSCH__SHIFT 0x2 3209 #define UVD_RAS_CNTL_PMI_ARB__ACK_MMSCH__SHIFT 0x3 3210 #define UVD_RAS_CNTL_PMI_ARB__STAT_JPEG0__SHIFT 0x4 3211 #define UVD_RAS_CNTL_PMI_ARB__ACK_JPEG0__SHIFT 0x5 3212 #define UVD_RAS_CNTL_PMI_ARB__STAT_JPEG1__SHIFT 0x6 3213 #define UVD_RAS_CNTL_PMI_ARB__ACK_JPEG1__SHIFT 0x7 3214 #define UVD_RAS_CNTL_PMI_ARB__STAT_VCPU_VCODEC_MASK 0x00000001L 3215 #define UVD_RAS_CNTL_PMI_ARB__ACK_VCPU_VCODEC_MASK 0x00000002L 3216 #define UVD_RAS_CNTL_PMI_ARB__STAT_MMSCH_MASK 0x00000004L 3217 #define UVD_RAS_CNTL_PMI_ARB__ACK_MMSCH_MASK 0x00000008L 3218 #define UVD_RAS_CNTL_PMI_ARB__STAT_JPEG0_MASK 0x00000010L 3219 #define UVD_RAS_CNTL_PMI_ARB__ACK_JPEG0_MASK 0x00000020L 3220 #define UVD_RAS_CNTL_PMI_ARB__STAT_JPEG1_MASK 0x00000040L 3221 #define UVD_RAS_CNTL_PMI_ARB__ACK_JPEG1_MASK 0x00000080L 3222 3223 3224 // addressBlock: uvd0_uvd_rbcdec 3225 //UVD_RBC_IB_SIZE 3226 #define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4 3227 #define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 3228 //UVD_RBC_IB_SIZE_UPDATE 3229 #define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 3230 #define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 3231 //UVD_RBC_RB_CNTL 3232 #define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 3233 #define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 3234 #define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 3235 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 3236 #define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 3237 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c 3238 #define UVD_RBC_RB_CNTL__BLK_RST__SHIFT 0x1d 3239 #define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x0000001FL 3240 #define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x00001F00L 3241 #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L 3242 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x00100000L 3243 #define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x01000000L 3244 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L 3245 #define UVD_RBC_RB_CNTL__BLK_RST_MASK 0x20000000L 3246 //UVD_RBC_RB_RPTR_ADDR 3247 #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 3248 #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFFL 3249 //UVD_RBC_RB_RPTR 3250 #define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 3251 #define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 3252 //UVD_RBC_RB_WPTR 3253 #define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 3254 #define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 3255 //UVD_RBC_VCPU_ACCESS 3256 #define UVD_RBC_VCPU_ACCESS__ENABLE_RBC__SHIFT 0x0 3257 #define UVD_RBC_VCPU_ACCESS__ENABLE_RBC_MASK 0x00000001L 3258 //UVD_FW_SEMAPHORE_CNTL 3259 #define UVD_FW_SEMAPHORE_CNTL__START__SHIFT 0x0 3260 #define UVD_FW_SEMAPHORE_CNTL__BUSY__SHIFT 0x8 3261 #define UVD_FW_SEMAPHORE_CNTL__PASS__SHIFT 0x9 3262 #define UVD_FW_SEMAPHORE_CNTL__START_MASK 0x00000001L 3263 #define UVD_FW_SEMAPHORE_CNTL__BUSY_MASK 0x00000100L 3264 #define UVD_FW_SEMAPHORE_CNTL__PASS_MASK 0x00000200L 3265 //UVD_RBC_READ_REQ_URGENT_CNTL 3266 #define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 3267 #define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 3268 //UVD_RBC_RB_WPTR_CNTL 3269 #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x0 3270 #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK 0x00007FFFL 3271 //UVD_RBC_WPTR_STATUS 3272 #define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE__SHIFT 0x4 3273 #define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE_MASK 0x007FFFF0L 3274 //UVD_RBC_WPTR_POLL_CNTL 3275 #define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ__SHIFT 0x0 3276 #define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 3277 #define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ_MASK 0x0000FFFFL 3278 #define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 3279 //UVD_RBC_WPTR_POLL_ADDR 3280 #define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR__SHIFT 0x2 3281 #define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR_MASK 0xFFFFFFFCL 3282 //UVD_SEMA_CMD 3283 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 3284 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 3285 #define UVD_SEMA_CMD__MODE__SHIFT 0x6 3286 #define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7 3287 #define UVD_SEMA_CMD__VMID__SHIFT 0x8 3288 #define UVD_SEMA_CMD__REQ_CMD_MASK 0x0000000FL 3289 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x00000030L 3290 #define UVD_SEMA_CMD__MODE_MASK 0x00000040L 3291 #define UVD_SEMA_CMD__VMID_EN_MASK 0x00000080L 3292 #define UVD_SEMA_CMD__VMID_MASK 0x00000F00L 3293 //UVD_SEMA_ADDR_LOW 3294 #define UVD_SEMA_ADDR_LOW__ADDR_26_3__SHIFT 0x0 3295 #define UVD_SEMA_ADDR_LOW__ADDR_26_3_MASK 0x00FFFFFFL 3296 //UVD_SEMA_ADDR_HIGH 3297 #define UVD_SEMA_ADDR_HIGH__ADDR_47_27__SHIFT 0x0 3298 #define UVD_SEMA_ADDR_HIGH__ADDR_47_27_MASK 0x001FFFFFL 3299 //UVD_ENGINE_CNTL 3300 #define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0 3301 #define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 3302 #define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE__SHIFT 0x2 3303 #define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x00000001L 3304 #define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x00000002L 3305 #define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE_MASK 0x00000004L 3306 //UVD_SEMA_TIMEOUT_STATUS 3307 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0 3308 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1 3309 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2 3310 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3 3311 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000001L 3312 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x00000002L 3313 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000004L 3314 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x00000008L 3315 //UVD_SEMA_CNTL 3316 #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 3317 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 3318 #define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x00000001L 3319 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x00000002L 3320 //UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 3321 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0 3322 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1 3323 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 3324 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x00000001L 3325 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x001FFFFEL 3326 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 3327 //UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 3328 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0 3329 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1 3330 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 3331 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x00000001L 3332 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x001FFFFEL 3333 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 3334 //UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 3335 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0 3336 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1 3337 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 3338 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x00000001L 3339 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x001FFFFEL 3340 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 3341 //UVD_JOB_START 3342 #define UVD_JOB_START__JOB_START__SHIFT 0x0 3343 #define UVD_JOB_START__JOB_START_MASK 0x00000001L 3344 //UVD_RBC_BUF_STATUS 3345 #define UVD_RBC_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 3346 #define UVD_RBC_BUF_STATUS__IB_BUF_VALID__SHIFT 0x8 3347 #define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 3348 #define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x13 3349 #define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x16 3350 #define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x19 3351 #define UVD_RBC_BUF_STATUS__RB_BUF_VALID_MASK 0x000000FFL 3352 #define UVD_RBC_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FF00L 3353 #define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x00070000L 3354 #define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x00380000L 3355 #define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x01C00000L 3356 #define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x0E000000L 3357 //UVD_RBC_SWAP_CNTL 3358 #define UVD_RBC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 3359 #define UVD_RBC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 3360 #define UVD_RBC_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4 3361 #define UVD_RBC_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a 3362 #define UVD_RBC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 3363 #define UVD_RBC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 3364 #define UVD_RBC_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x00000030L 3365 #define UVD_RBC_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0C000000L 3366 3367 3368 // addressBlock: uvd0_uvddec 3369 //UVD_STATUS 3370 #define UVD_STATUS__RBC_BUSY__SHIFT 0x0 3371 #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 3372 #define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10 3373 #define UVD_STATUS__SYS_GPCOM_REQ__SHIFT 0x1f 3374 #define UVD_STATUS__RBC_BUSY_MASK 0x00000001L 3375 #define UVD_STATUS__VCPU_REPORT_MASK 0x000000FEL 3376 #define UVD_STATUS__RBC_ACCESS_GPCOM_MASK 0x00010000L 3377 #define UVD_STATUS__SYS_GPCOM_REQ_MASK 0x80000000L 3378 //UVD_ENC_PIPE_BUSY 3379 #define UVD_ENC_PIPE_BUSY__IME_BUSY__SHIFT 0x0 3380 #define UVD_ENC_PIPE_BUSY__SMP_BUSY__SHIFT 0x1 3381 #define UVD_ENC_PIPE_BUSY__SIT_BUSY__SHIFT 0x2 3382 #define UVD_ENC_PIPE_BUSY__SDB_BUSY__SHIFT 0x3 3383 #define UVD_ENC_PIPE_BUSY__ENT_BUSY__SHIFT 0x4 3384 #define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY__SHIFT 0x5 3385 #define UVD_ENC_PIPE_BUSY__LCM_BUSY__SHIFT 0x6 3386 #define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT 0x7 3387 #define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT 0x8 3388 #define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT 0xa 3389 #define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT 0x10 3390 #define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT 0x11 3391 #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT 0x12 3392 #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT 0x13 3393 #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT 0x14 3394 #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT 0x15 3395 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT 0x16 3396 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT 0x17 3397 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT 0x18 3398 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT 0x19 3399 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT 0x1a 3400 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT 0x1b 3401 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT 0x1c 3402 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY__SHIFT 0x1d 3403 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY__SHIFT 0x1e 3404 #define UVD_ENC_PIPE_BUSY__IME_BUSY_MASK 0x00000001L 3405 #define UVD_ENC_PIPE_BUSY__SMP_BUSY_MASK 0x00000002L 3406 #define UVD_ENC_PIPE_BUSY__SIT_BUSY_MASK 0x00000004L 3407 #define UVD_ENC_PIPE_BUSY__SDB_BUSY_MASK 0x00000008L 3408 #define UVD_ENC_PIPE_BUSY__ENT_BUSY_MASK 0x00000010L 3409 #define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY_MASK 0x00000020L 3410 #define UVD_ENC_PIPE_BUSY__LCM_BUSY_MASK 0x00000040L 3411 #define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK 0x00000080L 3412 #define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY_MASK 0x00000100L 3413 #define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK 0x00000400L 3414 #define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK 0x00010000L 3415 #define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK 0x00020000L 3416 #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK 0x00040000L 3417 #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK 0x00080000L 3418 #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK 0x00100000L 3419 #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK 0x00200000L 3420 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK 0x00400000L 3421 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK 0x00800000L 3422 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK 0x01000000L 3423 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK 0x02000000L 3424 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK 0x04000000L 3425 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK 0x08000000L 3426 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK 0x10000000L 3427 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY_MASK 0x20000000L 3428 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY_MASK 0x40000000L 3429 //UVD_FW_POWER_STATUS 3430 #define UVD_FW_POWER_STATUS__UVDF_PWR_OFF__SHIFT 0x0 3431 #define UVD_FW_POWER_STATUS__UVDC_PWR_OFF__SHIFT 0x1 3432 #define UVD_FW_POWER_STATUS__UVDB_PWR_OFF__SHIFT 0x2 3433 #define UVD_FW_POWER_STATUS__UVDIL_PWR_OFF__SHIFT 0x3 3434 #define UVD_FW_POWER_STATUS__UVDIR_PWR_OFF__SHIFT 0x4 3435 #define UVD_FW_POWER_STATUS__UVDTD_PWR_OFF__SHIFT 0x5 3436 #define UVD_FW_POWER_STATUS__UVDTE_PWR_OFF__SHIFT 0x6 3437 #define UVD_FW_POWER_STATUS__UVDE_PWR_OFF__SHIFT 0x7 3438 #define UVD_FW_POWER_STATUS__UVDW_PWR_OFF__SHIFT 0x8 3439 #define UVD_FW_POWER_STATUS__UVDF_PWR_OFF_MASK 0x00000001L 3440 #define UVD_FW_POWER_STATUS__UVDC_PWR_OFF_MASK 0x00000002L 3441 #define UVD_FW_POWER_STATUS__UVDB_PWR_OFF_MASK 0x00000004L 3442 #define UVD_FW_POWER_STATUS__UVDIL_PWR_OFF_MASK 0x00000008L 3443 #define UVD_FW_POWER_STATUS__UVDIR_PWR_OFF_MASK 0x00000010L 3444 #define UVD_FW_POWER_STATUS__UVDTD_PWR_OFF_MASK 0x00000020L 3445 #define UVD_FW_POWER_STATUS__UVDTE_PWR_OFF_MASK 0x00000040L 3446 #define UVD_FW_POWER_STATUS__UVDE_PWR_OFF_MASK 0x00000080L 3447 #define UVD_FW_POWER_STATUS__UVDW_PWR_OFF_MASK 0x00000100L 3448 //UVD_CNTL 3449 #define UVD_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11 3450 #define UVD_CNTL__SUVD_EN__SHIFT 0x13 3451 #define UVD_CNTL__CABAC_MB_ACC__SHIFT 0x1c 3452 #define UVD_CNTL__LRBBM_SAFE_SYNC_DIS__SHIFT 0x1f 3453 #define UVD_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x00020000L 3454 #define UVD_CNTL__SUVD_EN_MASK 0x00080000L 3455 #define UVD_CNTL__CABAC_MB_ACC_MASK 0x10000000L 3456 #define UVD_CNTL__LRBBM_SAFE_SYNC_DIS_MASK 0x80000000L 3457 //UVD_SOFT_RESET 3458 #define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 3459 #define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 3460 #define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 3461 #define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 3462 #define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 3463 #define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 3464 #define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 3465 #define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 3466 #define UVD_SOFT_RESET__EFC_SOFT_RESET__SHIFT 0x9 3467 #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa 3468 #define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb 3469 #define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc 3470 #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd 3471 #define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe 3472 #define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf 3473 #define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 3474 #define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11 3475 #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12 3476 #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13 3477 #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14 3478 #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15 3479 #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16 3480 #define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17 3481 #define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18 3482 #define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19 3483 #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a 3484 #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b 3485 #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c 3486 #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d 3487 #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e 3488 #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f 3489 #define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x00000001L 3490 #define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x00000002L 3491 #define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00000004L 3492 #define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x00000008L 3493 #define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x00000010L 3494 #define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x00000040L 3495 #define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000080L 3496 #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x00000100L 3497 #define UVD_SOFT_RESET__EFC_SOFT_RESET_MASK 0x00000200L 3498 #define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L 3499 #define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x00000800L 3500 #define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x00001000L 3501 #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00002000L 3502 #define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x00004000L 3503 #define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00008000L 3504 #define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00010000L 3505 #define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x00020000L 3506 #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x00040000L 3507 #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x00080000L 3508 #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x00100000L 3509 #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x00200000L 3510 #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x00400000L 3511 #define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x00800000L 3512 #define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x01000000L 3513 #define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x02000000L 3514 #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x04000000L 3515 #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x08000000L 3516 #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L 3517 #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000L 3518 #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000L 3519 #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000L 3520 //UVD_SOFT_RESET2 3521 #define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0 3522 #define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS__SHIFT 0x10 3523 #define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS__SHIFT 0x11 3524 #define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L 3525 #define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS_MASK 0x00010000L 3526 #define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS_MASK 0x00020000L 3527 //UVD_MMSCH_SOFT_RESET 3528 #define UVD_MMSCH_SOFT_RESET__MMSCH_RESET__SHIFT 0x0 3529 #define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x1 3530 #define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK__SHIFT 0x1f 3531 #define UVD_MMSCH_SOFT_RESET__MMSCH_RESET_MASK 0x00000001L 3532 #define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000002L 3533 #define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK_MASK 0x80000000L 3534 //UVD_WIG_CTRL 3535 #define UVD_WIG_CTRL__AVM_SOFT_RESET__SHIFT 0x0 3536 #define UVD_WIG_CTRL__ACAP_SOFT_RESET__SHIFT 0x1 3537 #define UVD_WIG_CTRL__WIG_SOFT_RESET__SHIFT 0x2 3538 #define UVD_WIG_CTRL__WIG_REGCLK_FORCE_ON__SHIFT 0x3 3539 #define UVD_WIG_CTRL__AVM_REGCLK_FORCE_ON__SHIFT 0x4 3540 #define UVD_WIG_CTRL__AVM_SOFT_RESET_MASK 0x00000001L 3541 #define UVD_WIG_CTRL__ACAP_SOFT_RESET_MASK 0x00000002L 3542 #define UVD_WIG_CTRL__WIG_SOFT_RESET_MASK 0x00000004L 3543 #define UVD_WIG_CTRL__WIG_REGCLK_FORCE_ON_MASK 0x00000008L 3544 #define UVD_WIG_CTRL__AVM_REGCLK_FORCE_ON_MASK 0x00000010L 3545 //UVD_CGC_GATE 3546 #define UVD_CGC_GATE__SYS__SHIFT 0x0 3547 #define UVD_CGC_GATE__UDEC__SHIFT 0x1 3548 #define UVD_CGC_GATE__MPEG2__SHIFT 0x2 3549 #define UVD_CGC_GATE__REGS__SHIFT 0x3 3550 #define UVD_CGC_GATE__RBC__SHIFT 0x4 3551 #define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 3552 #define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 3553 #define UVD_CGC_GATE__IDCT__SHIFT 0x7 3554 #define UVD_CGC_GATE__MPRD__SHIFT 0x8 3555 #define UVD_CGC_GATE__MPC__SHIFT 0x9 3556 #define UVD_CGC_GATE__LBSI__SHIFT 0xa 3557 #define UVD_CGC_GATE__LRBBM__SHIFT 0xb 3558 #define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc 3559 #define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd 3560 #define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe 3561 #define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf 3562 #define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 3563 #define UVD_CGC_GATE__WCB__SHIFT 0x11 3564 #define UVD_CGC_GATE__VCPU__SHIFT 0x12 3565 #define UVD_CGC_GATE__MMSCH__SHIFT 0x14 3566 #define UVD_CGC_GATE__SYS_MASK 0x00000001L 3567 #define UVD_CGC_GATE__UDEC_MASK 0x00000002L 3568 #define UVD_CGC_GATE__MPEG2_MASK 0x00000004L 3569 #define UVD_CGC_GATE__REGS_MASK 0x00000008L 3570 #define UVD_CGC_GATE__RBC_MASK 0x00000010L 3571 #define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L 3572 #define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L 3573 #define UVD_CGC_GATE__IDCT_MASK 0x00000080L 3574 #define UVD_CGC_GATE__MPRD_MASK 0x00000100L 3575 #define UVD_CGC_GATE__MPC_MASK 0x00000200L 3576 #define UVD_CGC_GATE__LBSI_MASK 0x00000400L 3577 #define UVD_CGC_GATE__LRBBM_MASK 0x00000800L 3578 #define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L 3579 #define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L 3580 #define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L 3581 #define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L 3582 #define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L 3583 #define UVD_CGC_GATE__WCB_MASK 0x00020000L 3584 #define UVD_CGC_GATE__VCPU_MASK 0x00040000L 3585 #define UVD_CGC_GATE__MMSCH_MASK 0x00100000L 3586 //UVD_CGC_STATUS 3587 #define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0 3588 #define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 3589 #define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2 3590 #define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3 3591 #define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4 3592 #define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 3593 #define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6 3594 #define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7 3595 #define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8 3596 #define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9 3597 #define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa 3598 #define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb 3599 #define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc 3600 #define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd 3601 #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe 3602 #define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf 3603 #define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10 3604 #define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11 3605 #define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12 3606 #define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 3607 #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14 3608 #define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15 3609 #define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16 3610 #define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17 3611 #define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18 3612 #define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19 3613 #define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a 3614 #define UVD_CGC_STATUS__MMSCH_SCLK__SHIFT 0x1b 3615 #define UVD_CGC_STATUS__MMSCH_VCLK__SHIFT 0x1c 3616 #define UVD_CGC_STATUS__ALL_ENC_ACTIVE__SHIFT 0x1d 3617 #define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f 3618 #define UVD_CGC_STATUS__SYS_SCLK_MASK 0x00000001L 3619 #define UVD_CGC_STATUS__SYS_DCLK_MASK 0x00000002L 3620 #define UVD_CGC_STATUS__SYS_VCLK_MASK 0x00000004L 3621 #define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x00000008L 3622 #define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x00000010L 3623 #define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x00000020L 3624 #define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x00000040L 3625 #define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x00000080L 3626 #define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x00000100L 3627 #define UVD_CGC_STATUS__REGS_SCLK_MASK 0x00000200L 3628 #define UVD_CGC_STATUS__REGS_VCLK_MASK 0x00000400L 3629 #define UVD_CGC_STATUS__RBC_SCLK_MASK 0x00000800L 3630 #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x00001000L 3631 #define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x00002000L 3632 #define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x00004000L 3633 #define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x00008000L 3634 #define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x00010000L 3635 #define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x00020000L 3636 #define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x00040000L 3637 #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L 3638 #define UVD_CGC_STATUS__MPC_DCLK_MASK 0x00100000L 3639 #define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x00200000L 3640 #define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x00400000L 3641 #define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x00800000L 3642 #define UVD_CGC_STATUS__WCB_SCLK_MASK 0x01000000L 3643 #define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x02000000L 3644 #define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x04000000L 3645 #define UVD_CGC_STATUS__MMSCH_SCLK_MASK 0x08000000L 3646 #define UVD_CGC_STATUS__MMSCH_VCLK_MASK 0x10000000L 3647 #define UVD_CGC_STATUS__ALL_ENC_ACTIVE_MASK 0x20000000L 3648 #define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000L 3649 //UVD_CGC_CTRL 3650 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 3651 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 3652 #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 3653 #define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb 3654 #define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc 3655 #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd 3656 #define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe 3657 #define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf 3658 #define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 3659 #define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 3660 #define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 3661 #define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 3662 #define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 3663 #define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 3664 #define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 3665 #define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 3666 #define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 3667 #define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 3668 #define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a 3669 #define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b 3670 #define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c 3671 #define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d 3672 #define UVD_CGC_CTRL__MMSCH_MODE__SHIFT 0x1f 3673 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L 3674 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL 3675 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L 3676 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L 3677 #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L 3678 #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L 3679 #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L 3680 #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L 3681 #define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L 3682 #define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L 3683 #define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L 3684 #define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L 3685 #define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L 3686 #define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L 3687 #define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L 3688 #define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L 3689 #define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L 3690 #define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L 3691 #define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L 3692 #define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L 3693 #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L 3694 #define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L 3695 #define UVD_CGC_CTRL__MMSCH_MODE_MASK 0x80000000L 3696 //UVD_CGC_UDEC_STATUS 3697 #define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0 3698 #define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1 3699 #define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2 3700 #define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3 3701 #define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 3702 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 3703 #define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6 3704 #define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7 3705 #define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8 3706 #define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9 3707 #define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa 3708 #define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb 3709 #define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc 3710 #define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd 3711 #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe 3712 #define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x00000001L 3713 #define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x00000002L 3714 #define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x00000004L 3715 #define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x00000008L 3716 #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x00000010L 3717 #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x00000020L 3718 #define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x00000040L 3719 #define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x00000080L 3720 #define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x00000100L 3721 #define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x00000200L 3722 #define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x00000400L 3723 #define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x00000800L 3724 #define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x00001000L 3725 #define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L 3726 #define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x00004000L 3727 //UVD_SUVD_CGC_GATE 3728 #define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0 3729 #define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1 3730 #define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2 3731 #define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3 3732 #define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4 3733 #define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 3734 #define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 3735 #define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 3736 #define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 3737 #define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 3738 #define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 3739 #define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 3740 #define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 3741 #define UVD_SUVD_CGC_GATE__SCLR__SHIFT 0xd 3742 #define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 3743 #define UVD_SUVD_CGC_GATE__ENT__SHIFT 0xf 3744 #define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10 3745 #define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 3746 #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 3747 #define UVD_SUVD_CGC_GATE__SITE__SHIFT 0x13 3748 #define UVD_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 3749 #define UVD_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 3750 #define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 3751 #define UVD_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 3752 #define UVD_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 3753 #define UVD_SUVD_CGC_GATE__EFC__SHIFT 0x19 3754 #define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L 3755 #define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L 3756 #define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L 3757 #define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L 3758 #define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L 3759 #define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 3760 #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 3761 #define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 3762 #define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 3763 #define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 3764 #define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 3765 #define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 3766 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 3767 #define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 3768 #define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 3769 #define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L 3770 #define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L 3771 #define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 3772 #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 3773 #define UVD_SUVD_CGC_GATE__SITE_MASK 0x00080000L 3774 #define UVD_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 3775 #define UVD_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 3776 #define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 3777 #define UVD_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 3778 #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 3779 #define UVD_SUVD_CGC_GATE__EFC_MASK 0x02000000L 3780 //UVD_SUVD_CGC_STATUS 3781 #define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0 3782 #define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1 3783 #define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2 3784 #define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3 3785 #define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4 3786 #define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5 3787 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6 3788 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7 3789 #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8 3790 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9 3791 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa 3792 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb 3793 #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc 3794 #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd 3795 #define UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT 0xe 3796 #define UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT 0xf 3797 #define UVD_SUVD_CGC_STATUS__ENT_DCLK__SHIFT 0x10 3798 #define UVD_SUVD_CGC_STATUS__IME_DCLK__SHIFT 0x11 3799 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK__SHIFT 0x12 3800 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK__SHIFT 0x13 3801 #define UVD_SUVD_CGC_STATUS__SITE_DCLK__SHIFT 0x14 3802 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK__SHIFT 0x15 3803 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT 0x16 3804 #define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK__SHIFT 0x17 3805 #define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK__SHIFT 0x18 3806 #define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK__SHIFT 0x19 3807 #define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK__SHIFT 0x1a 3808 #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT 0x1b 3809 #define UVD_SUVD_CGC_STATUS__EFC_DCLK__SHIFT 0x1c 3810 #define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x00000001L 3811 #define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x00000002L 3812 #define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x00000004L 3813 #define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x00000008L 3814 #define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x00000010L 3815 #define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x00000020L 3816 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x00000040L 3817 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L 3818 #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x00000100L 3819 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x00000200L 3820 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x00000400L 3821 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x00000800L 3822 #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x00001000L 3823 #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x00002000L 3824 #define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK 0x00004000L 3825 #define UVD_SUVD_CGC_STATUS__UVD_SC_MASK 0x00008000L 3826 #define UVD_SUVD_CGC_STATUS__ENT_DCLK_MASK 0x00010000L 3827 #define UVD_SUVD_CGC_STATUS__IME_DCLK_MASK 0x00020000L 3828 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK_MASK 0x00040000L 3829 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK_MASK 0x00080000L 3830 #define UVD_SUVD_CGC_STATUS__SITE_DCLK_MASK 0x00100000L 3831 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK_MASK 0x00200000L 3832 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK_MASK 0x00400000L 3833 #define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK_MASK 0x00800000L 3834 #define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK_MASK 0x01000000L 3835 #define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK_MASK 0x02000000L 3836 #define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK_MASK 0x04000000L 3837 #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK 0x08000000L 3838 #define UVD_SUVD_CGC_STATUS__EFC_DCLK_MASK 0x10000000L 3839 //UVD_SUVD_CGC_CTRL 3840 #define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 3841 #define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 3842 #define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 3843 #define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 3844 #define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 3845 #define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 3846 #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 3847 #define UVD_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 3848 #define UVD_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 3849 #define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 3850 #define UVD_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 3851 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 3852 #define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 3853 #define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 3854 #define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 3855 #define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 3856 #define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 3857 #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 3858 #define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 3859 #define UVD_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 3860 #define UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 3861 #define UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 3862 //UVD_GPCOM_VCPU_CMD 3863 #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 3864 #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 3865 #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f 3866 #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x00000001L 3867 #define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7FFFFFFEL 3868 #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000L 3869 //UVD_GPCOM_VCPU_DATA0 3870 #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 3871 #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xFFFFFFFFL 3872 //UVD_GPCOM_VCPU_DATA1 3873 #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 3874 #define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xFFFFFFFFL 3875 //UVD_GPCOM_SYS_CMD 3876 #define UVD_GPCOM_SYS_CMD__CMD_SEND__SHIFT 0x0 3877 #define UVD_GPCOM_SYS_CMD__CMD__SHIFT 0x1 3878 #define UVD_GPCOM_SYS_CMD__CMD_SOURCE__SHIFT 0x1f 3879 #define UVD_GPCOM_SYS_CMD__CMD_SEND_MASK 0x00000001L 3880 #define UVD_GPCOM_SYS_CMD__CMD_MASK 0x7FFFFFFEL 3881 #define UVD_GPCOM_SYS_CMD__CMD_SOURCE_MASK 0x80000000L 3882 //UVD_GPCOM_SYS_DATA0 3883 #define UVD_GPCOM_SYS_DATA0__DATA0__SHIFT 0x0 3884 #define UVD_GPCOM_SYS_DATA0__DATA0_MASK 0xFFFFFFFFL 3885 //UVD_GPCOM_SYS_DATA1 3886 #define UVD_GPCOM_SYS_DATA1__DATA1__SHIFT 0x0 3887 #define UVD_GPCOM_SYS_DATA1__DATA1_MASK 0xFFFFFFFFL 3888 //UVD_VCPU_INT_EN 3889 #define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0 3890 #define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1 3891 #define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2 3892 #define UVD_VCPU_INT_EN__NJ_PF_RPT_EN__SHIFT 0x3 3893 #define UVD_VCPU_INT_EN__SW_RB1_INT_EN__SHIFT 0x4 3894 #define UVD_VCPU_INT_EN__SW_RB2_INT_EN__SHIFT 0x5 3895 #define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6 3896 #define UVD_VCPU_INT_EN__SW_RB3_INT_EN__SHIFT 0x7 3897 #define UVD_VCPU_INT_EN__SW_RB4_INT_EN__SHIFT 0x9 3898 #define UVD_VCPU_INT_EN__SW_RB5_INT_EN__SHIFT 0xa 3899 #define UVD_VCPU_INT_EN__LBSI_EN__SHIFT 0xb 3900 #define UVD_VCPU_INT_EN__UDEC_EN__SHIFT 0xc 3901 #define UVD_VCPU_INT_EN__SUVD_EN__SHIFT 0xf 3902 #define UVD_VCPU_INT_EN__RPTR_WR_EN__SHIFT 0x10 3903 #define UVD_VCPU_INT_EN__JOB_START_EN__SHIFT 0x11 3904 #define UVD_VCPU_INT_EN__NJ_PF_EN__SHIFT 0x12 3905 #define UVD_VCPU_INT_EN__RASCNTL_VCPU_VCODEC_EN__SHIFT 0x16 3906 #define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17 3907 #define UVD_VCPU_INT_EN__IDCT_EN__SHIFT 0x18 3908 #define UVD_VCPU_INT_EN__MPRD_EN__SHIFT 0x19 3909 #define UVD_VCPU_INT_EN__AVM_INT_EN__SHIFT 0x1a 3910 #define UVD_VCPU_INT_EN__CLK_SWT_EN__SHIFT 0x1b 3911 #define UVD_VCPU_INT_EN__MIF_HWINT_EN__SHIFT 0x1c 3912 #define UVD_VCPU_INT_EN__MPRD_ERR_EN__SHIFT 0x1d 3913 #define UVD_VCPU_INT_EN__DRV_FW_REQ_EN__SHIFT 0x1e 3914 #define UVD_VCPU_INT_EN__DRV_FW_ACK_EN__SHIFT 0x1f 3915 #define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L 3916 #define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L 3917 #define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L 3918 #define UVD_VCPU_INT_EN__NJ_PF_RPT_EN_MASK 0x00000008L 3919 #define UVD_VCPU_INT_EN__SW_RB1_INT_EN_MASK 0x00000010L 3920 #define UVD_VCPU_INT_EN__SW_RB2_INT_EN_MASK 0x00000020L 3921 #define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L 3922 #define UVD_VCPU_INT_EN__SW_RB3_INT_EN_MASK 0x00000080L 3923 #define UVD_VCPU_INT_EN__SW_RB4_INT_EN_MASK 0x00000200L 3924 #define UVD_VCPU_INT_EN__SW_RB5_INT_EN_MASK 0x00000400L 3925 #define UVD_VCPU_INT_EN__LBSI_EN_MASK 0x00000800L 3926 #define UVD_VCPU_INT_EN__UDEC_EN_MASK 0x00001000L 3927 #define UVD_VCPU_INT_EN__SUVD_EN_MASK 0x00008000L 3928 #define UVD_VCPU_INT_EN__RPTR_WR_EN_MASK 0x00010000L 3929 #define UVD_VCPU_INT_EN__JOB_START_EN_MASK 0x00020000L 3930 #define UVD_VCPU_INT_EN__NJ_PF_EN_MASK 0x00040000L 3931 #define UVD_VCPU_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK 0x00400000L 3932 #define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L 3933 #define UVD_VCPU_INT_EN__IDCT_EN_MASK 0x01000000L 3934 #define UVD_VCPU_INT_EN__MPRD_EN_MASK 0x02000000L 3935 #define UVD_VCPU_INT_EN__AVM_INT_EN_MASK 0x04000000L 3936 #define UVD_VCPU_INT_EN__CLK_SWT_EN_MASK 0x08000000L 3937 #define UVD_VCPU_INT_EN__MIF_HWINT_EN_MASK 0x10000000L 3938 #define UVD_VCPU_INT_EN__MPRD_ERR_EN_MASK 0x20000000L 3939 #define UVD_VCPU_INT_EN__DRV_FW_REQ_EN_MASK 0x40000000L 3940 #define UVD_VCPU_INT_EN__DRV_FW_ACK_EN_MASK 0x80000000L 3941 //UVD_VCPU_INT_STATUS 3942 #define UVD_VCPU_INT_STATUS__PIF_ADDR_ERR_INT__SHIFT 0x0 3943 #define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT 0x1 3944 #define UVD_VCPU_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT 0x2 3945 #define UVD_VCPU_INT_STATUS__NJ_PF_RPT_INT__SHIFT 0x3 3946 #define UVD_VCPU_INT_STATUS__SW_RB1_INT__SHIFT 0x4 3947 #define UVD_VCPU_INT_STATUS__SW_RB2_INT__SHIFT 0x5 3948 #define UVD_VCPU_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT 0x6 3949 #define UVD_VCPU_INT_STATUS__SW_RB3_INT__SHIFT 0x7 3950 #define UVD_VCPU_INT_STATUS__SW_RB4_INT__SHIFT 0x9 3951 #define UVD_VCPU_INT_STATUS__SW_RB5_INT__SHIFT 0xa 3952 #define UVD_VCPU_INT_STATUS__LBSI_INT__SHIFT 0xb 3953 #define UVD_VCPU_INT_STATUS__UDEC_INT__SHIFT 0xc 3954 #define UVD_VCPU_INT_STATUS__SUVD_INT__SHIFT 0xf 3955 #define UVD_VCPU_INT_STATUS__RPTR_WR_INT__SHIFT 0x10 3956 #define UVD_VCPU_INT_STATUS__JOB_START_INT__SHIFT 0x11 3957 #define UVD_VCPU_INT_STATUS__NJ_PF_INT__SHIFT 0x12 3958 #define UVD_VCPU_INT_STATUS__GPCOM_INT__SHIFT 0x14 3959 #define UVD_VCPU_INT_STATUS__RASCNTL_VCPU_VCODEC_INT__SHIFT 0x15 3960 #define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT 0x17 3961 #define UVD_VCPU_INT_STATUS__IDCT_INT__SHIFT 0x18 3962 #define UVD_VCPU_INT_STATUS__MPRD_INT__SHIFT 0x19 3963 #define UVD_VCPU_INT_STATUS__AVM_INT__SHIFT 0x1a 3964 #define UVD_VCPU_INT_STATUS__CLK_SWT_INT__SHIFT 0x1b 3965 #define UVD_VCPU_INT_STATUS__MIF_HWINT__SHIFT 0x1c 3966 #define UVD_VCPU_INT_STATUS__MPRD_ERR_INT__SHIFT 0x1d 3967 #define UVD_VCPU_INT_STATUS__DRV_FW_REQ_INT__SHIFT 0x1e 3968 #define UVD_VCPU_INT_STATUS__DRV_FW_ACK_INT__SHIFT 0x1f 3969 #define UVD_VCPU_INT_STATUS__PIF_ADDR_ERR_INT_MASK 0x00000001L 3970 #define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK 0x00000002L 3971 #define UVD_VCPU_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK 0x00000004L 3972 #define UVD_VCPU_INT_STATUS__NJ_PF_RPT_INT_MASK 0x00000008L 3973 #define UVD_VCPU_INT_STATUS__SW_RB1_INT_MASK 0x00000010L 3974 #define UVD_VCPU_INT_STATUS__SW_RB2_INT_MASK 0x00000020L 3975 #define UVD_VCPU_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK 0x00000040L 3976 #define UVD_VCPU_INT_STATUS__SW_RB3_INT_MASK 0x00000080L 3977 #define UVD_VCPU_INT_STATUS__SW_RB4_INT_MASK 0x00000200L 3978 #define UVD_VCPU_INT_STATUS__SW_RB5_INT_MASK 0x00000400L 3979 #define UVD_VCPU_INT_STATUS__LBSI_INT_MASK 0x00000800L 3980 #define UVD_VCPU_INT_STATUS__UDEC_INT_MASK 0x00001000L 3981 #define UVD_VCPU_INT_STATUS__SUVD_INT_MASK 0x00008000L 3982 #define UVD_VCPU_INT_STATUS__RPTR_WR_INT_MASK 0x00010000L 3983 #define UVD_VCPU_INT_STATUS__JOB_START_INT_MASK 0x00020000L 3984 #define UVD_VCPU_INT_STATUS__NJ_PF_INT_MASK 0x00040000L 3985 #define UVD_VCPU_INT_STATUS__GPCOM_INT_MASK 0x00100000L 3986 #define UVD_VCPU_INT_STATUS__RASCNTL_VCPU_VCODEC_INT_MASK 0x00200000L 3987 #define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK 0x00800000L 3988 #define UVD_VCPU_INT_STATUS__IDCT_INT_MASK 0x01000000L 3989 #define UVD_VCPU_INT_STATUS__MPRD_INT_MASK 0x02000000L 3990 #define UVD_VCPU_INT_STATUS__AVM_INT_MASK 0x04000000L 3991 #define UVD_VCPU_INT_STATUS__CLK_SWT_INT_MASK 0x08000000L 3992 #define UVD_VCPU_INT_STATUS__MIF_HWINT_MASK 0x10000000L 3993 #define UVD_VCPU_INT_STATUS__MPRD_ERR_INT_MASK 0x20000000L 3994 #define UVD_VCPU_INT_STATUS__DRV_FW_REQ_INT_MASK 0x40000000L 3995 #define UVD_VCPU_INT_STATUS__DRV_FW_ACK_INT_MASK 0x80000000L 3996 //UVD_VCPU_INT_ACK 3997 #define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0 3998 #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1 3999 #define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2 4000 #define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK__SHIFT 0x3 4001 #define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK__SHIFT 0x4 4002 #define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK__SHIFT 0x5 4003 #define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6 4004 #define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK__SHIFT 0x7 4005 #define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK__SHIFT 0x9 4006 #define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK__SHIFT 0xa 4007 #define UVD_VCPU_INT_ACK__LBSI_ACK__SHIFT 0xb 4008 #define UVD_VCPU_INT_ACK__UDEC_ACK__SHIFT 0xc 4009 #define UVD_VCPU_INT_ACK__SUVD_ACK__SHIFT 0xf 4010 #define UVD_VCPU_INT_ACK__RPTR_WR_ACK__SHIFT 0x10 4011 #define UVD_VCPU_INT_ACK__JOB_START_ACK__SHIFT 0x11 4012 #define UVD_VCPU_INT_ACK__NJ_PF_ACK__SHIFT 0x12 4013 #define UVD_VCPU_INT_ACK__RASCNTL_VCPU_VCODEC_ACK__SHIFT 0x16 4014 #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17 4015 #define UVD_VCPU_INT_ACK__IDCT_ACK__SHIFT 0x18 4016 #define UVD_VCPU_INT_ACK__MPRD_ACK__SHIFT 0x19 4017 #define UVD_VCPU_INT_ACK__AVM_INT_ACK__SHIFT 0x1a 4018 #define UVD_VCPU_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b 4019 #define UVD_VCPU_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c 4020 #define UVD_VCPU_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d 4021 #define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK__SHIFT 0x1e 4022 #define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK__SHIFT 0x1f 4023 #define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L 4024 #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L 4025 #define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L 4026 #define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK_MASK 0x00000008L 4027 #define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK_MASK 0x00000010L 4028 #define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK_MASK 0x00000020L 4029 #define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L 4030 #define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK_MASK 0x00000080L 4031 #define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK_MASK 0x00000200L 4032 #define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK_MASK 0x00000400L 4033 #define UVD_VCPU_INT_ACK__LBSI_ACK_MASK 0x00000800L 4034 #define UVD_VCPU_INT_ACK__UDEC_ACK_MASK 0x00001000L 4035 #define UVD_VCPU_INT_ACK__SUVD_ACK_MASK 0x00008000L 4036 #define UVD_VCPU_INT_ACK__RPTR_WR_ACK_MASK 0x00010000L 4037 #define UVD_VCPU_INT_ACK__JOB_START_ACK_MASK 0x00020000L 4038 #define UVD_VCPU_INT_ACK__NJ_PF_ACK_MASK 0x00040000L 4039 #define UVD_VCPU_INT_ACK__RASCNTL_VCPU_VCODEC_ACK_MASK 0x00400000L 4040 #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L 4041 #define UVD_VCPU_INT_ACK__IDCT_ACK_MASK 0x01000000L 4042 #define UVD_VCPU_INT_ACK__MPRD_ACK_MASK 0x02000000L 4043 #define UVD_VCPU_INT_ACK__AVM_INT_ACK_MASK 0x04000000L 4044 #define UVD_VCPU_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L 4045 #define UVD_VCPU_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L 4046 #define UVD_VCPU_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L 4047 #define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK_MASK 0x40000000L 4048 #define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK_MASK 0x80000000L 4049 //UVD_VCPU_INT_ROUTE 4050 #define UVD_VCPU_INT_ROUTE__DRV_FW_MSG__SHIFT 0x0 4051 #define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK__SHIFT 0x1 4052 #define UVD_VCPU_INT_ROUTE__VCPU_GPCOM__SHIFT 0x2 4053 #define UVD_VCPU_INT_ROUTE__DRV_FW_MSG_MASK 0x00000001L 4054 #define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK_MASK 0x00000002L 4055 #define UVD_VCPU_INT_ROUTE__VCPU_GPCOM_MASK 0x00000004L 4056 //UVD_DRV_FW_MSG 4057 #define UVD_DRV_FW_MSG__MSG__SHIFT 0x0 4058 #define UVD_DRV_FW_MSG__MSG_MASK 0xFFFFFFFFL 4059 //UVD_FW_DRV_MSG_ACK 4060 #define UVD_FW_DRV_MSG_ACK__ACK__SHIFT 0x0 4061 #define UVD_FW_DRV_MSG_ACK__ACK_MASK 0x00000001L 4062 //UVD_SUVD_INT_EN 4063 #define UVD_SUVD_INT_EN__SRE_FUNC_INT_EN__SHIFT 0x0 4064 #define UVD_SUVD_INT_EN__SRE_ERR_INT_EN__SHIFT 0x5 4065 #define UVD_SUVD_INT_EN__SIT_FUNC_INT_EN__SHIFT 0x6 4066 #define UVD_SUVD_INT_EN__SIT_ERR_INT_EN__SHIFT 0xb 4067 #define UVD_SUVD_INT_EN__SMP_FUNC_INT_EN__SHIFT 0xc 4068 #define UVD_SUVD_INT_EN__SMP_ERR_INT_EN__SHIFT 0x11 4069 #define UVD_SUVD_INT_EN__SCM_FUNC_INT_EN__SHIFT 0x12 4070 #define UVD_SUVD_INT_EN__SCM_ERR_INT_EN__SHIFT 0x17 4071 #define UVD_SUVD_INT_EN__SDB_FUNC_INT_EN__SHIFT 0x18 4072 #define UVD_SUVD_INT_EN__SDB_ERR_INT_EN__SHIFT 0x1d 4073 #define UVD_SUVD_INT_EN__SRE_FUNC_INT_EN_MASK 0x0000001FL 4074 #define UVD_SUVD_INT_EN__SRE_ERR_INT_EN_MASK 0x00000020L 4075 #define UVD_SUVD_INT_EN__SIT_FUNC_INT_EN_MASK 0x000007C0L 4076 #define UVD_SUVD_INT_EN__SIT_ERR_INT_EN_MASK 0x00000800L 4077 #define UVD_SUVD_INT_EN__SMP_FUNC_INT_EN_MASK 0x0001F000L 4078 #define UVD_SUVD_INT_EN__SMP_ERR_INT_EN_MASK 0x00020000L 4079 #define UVD_SUVD_INT_EN__SCM_FUNC_INT_EN_MASK 0x007C0000L 4080 #define UVD_SUVD_INT_EN__SCM_ERR_INT_EN_MASK 0x00800000L 4081 #define UVD_SUVD_INT_EN__SDB_FUNC_INT_EN_MASK 0x1F000000L 4082 #define UVD_SUVD_INT_EN__SDB_ERR_INT_EN_MASK 0x20000000L 4083 //UVD_SUVD_INT_STATUS 4084 #define UVD_SUVD_INT_STATUS__SRE_FUNC_INT__SHIFT 0x0 4085 #define UVD_SUVD_INT_STATUS__SRE_ERR_INT__SHIFT 0x5 4086 #define UVD_SUVD_INT_STATUS__SIT_FUNC_INT__SHIFT 0x6 4087 #define UVD_SUVD_INT_STATUS__SIT_ERR_INT__SHIFT 0xb 4088 #define UVD_SUVD_INT_STATUS__SMP_FUNC_INT__SHIFT 0xc 4089 #define UVD_SUVD_INT_STATUS__SMP_ERR_INT__SHIFT 0x11 4090 #define UVD_SUVD_INT_STATUS__SCM_FUNC_INT__SHIFT 0x12 4091 #define UVD_SUVD_INT_STATUS__SCM_ERR_INT__SHIFT 0x17 4092 #define UVD_SUVD_INT_STATUS__SDB_FUNC_INT__SHIFT 0x18 4093 #define UVD_SUVD_INT_STATUS__SDB_ERR_INT__SHIFT 0x1d 4094 #define UVD_SUVD_INT_STATUS__SRE_FUNC_INT_MASK 0x0000001FL 4095 #define UVD_SUVD_INT_STATUS__SRE_ERR_INT_MASK 0x00000020L 4096 #define UVD_SUVD_INT_STATUS__SIT_FUNC_INT_MASK 0x000007C0L 4097 #define UVD_SUVD_INT_STATUS__SIT_ERR_INT_MASK 0x00000800L 4098 #define UVD_SUVD_INT_STATUS__SMP_FUNC_INT_MASK 0x0001F000L 4099 #define UVD_SUVD_INT_STATUS__SMP_ERR_INT_MASK 0x00020000L 4100 #define UVD_SUVD_INT_STATUS__SCM_FUNC_INT_MASK 0x007C0000L 4101 #define UVD_SUVD_INT_STATUS__SCM_ERR_INT_MASK 0x00800000L 4102 #define UVD_SUVD_INT_STATUS__SDB_FUNC_INT_MASK 0x1F000000L 4103 #define UVD_SUVD_INT_STATUS__SDB_ERR_INT_MASK 0x20000000L 4104 //UVD_SUVD_INT_ACK 4105 #define UVD_SUVD_INT_ACK__SRE_FUNC_INT_ACK__SHIFT 0x0 4106 #define UVD_SUVD_INT_ACK__SRE_ERR_INT_ACK__SHIFT 0x5 4107 #define UVD_SUVD_INT_ACK__SIT_FUNC_INT_ACK__SHIFT 0x6 4108 #define UVD_SUVD_INT_ACK__SIT_ERR_INT_ACK__SHIFT 0xb 4109 #define UVD_SUVD_INT_ACK__SMP_FUNC_INT_ACK__SHIFT 0xc 4110 #define UVD_SUVD_INT_ACK__SMP_ERR_INT_ACK__SHIFT 0x11 4111 #define UVD_SUVD_INT_ACK__SCM_FUNC_INT_ACK__SHIFT 0x12 4112 #define UVD_SUVD_INT_ACK__SCM_ERR_INT_ACK__SHIFT 0x17 4113 #define UVD_SUVD_INT_ACK__SDB_FUNC_INT_ACK__SHIFT 0x18 4114 #define UVD_SUVD_INT_ACK__SDB_ERR_INT_ACK__SHIFT 0x1d 4115 #define UVD_SUVD_INT_ACK__SRE_FUNC_INT_ACK_MASK 0x0000001FL 4116 #define UVD_SUVD_INT_ACK__SRE_ERR_INT_ACK_MASK 0x00000020L 4117 #define UVD_SUVD_INT_ACK__SIT_FUNC_INT_ACK_MASK 0x000007C0L 4118 #define UVD_SUVD_INT_ACK__SIT_ERR_INT_ACK_MASK 0x00000800L 4119 #define UVD_SUVD_INT_ACK__SMP_FUNC_INT_ACK_MASK 0x0001F000L 4120 #define UVD_SUVD_INT_ACK__SMP_ERR_INT_ACK_MASK 0x00020000L 4121 #define UVD_SUVD_INT_ACK__SCM_FUNC_INT_ACK_MASK 0x007C0000L 4122 #define UVD_SUVD_INT_ACK__SCM_ERR_INT_ACK_MASK 0x00800000L 4123 #define UVD_SUVD_INT_ACK__SDB_FUNC_INT_ACK_MASK 0x1F000000L 4124 #define UVD_SUVD_INT_ACK__SDB_ERR_INT_ACK_MASK 0x20000000L 4125 //UVD_ENC_VCPU_INT_EN 4126 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN__SHIFT 0x0 4127 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN__SHIFT 0x1 4128 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN__SHIFT 0x2 4129 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN_MASK 0x00000001L 4130 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN_MASK 0x00000002L 4131 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN_MASK 0x00000004L 4132 //UVD_ENC_VCPU_INT_STATUS 4133 #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR_INT__SHIFT 0x0 4134 #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR2_INT__SHIFT 0x1 4135 #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR3_INT__SHIFT 0x2 4136 #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR_INT_MASK 0x00000001L 4137 #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR2_INT_MASK 0x00000002L 4138 #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR3_INT_MASK 0x00000004L 4139 //UVD_ENC_VCPU_INT_ACK 4140 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK__SHIFT 0x0 4141 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK__SHIFT 0x1 4142 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK__SHIFT 0x2 4143 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK_MASK 0x00000001L 4144 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK_MASK 0x00000002L 4145 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK_MASK 0x00000004L 4146 //UVD_MASTINT_EN 4147 #define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 4148 #define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 4149 #define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 4150 #define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 4151 #define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L 4152 #define UVD_MASTINT_EN__VCPU_EN_MASK 0x00000002L 4153 #define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L 4154 #define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x00FFFFF0L 4155 //UVD_SYS_INT_EN 4156 #define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0 4157 #define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1 4158 #define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2 4159 #define UVD_SYS_INT_EN__CXW_WR_EN__SHIFT 0x3 4160 #define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6 4161 #define UVD_SYS_INT_EN__LBSI_EN__SHIFT 0xb 4162 #define UVD_SYS_INT_EN__UDEC_EN__SHIFT 0xc 4163 #define UVD_SYS_INT_EN__SUVD_EN__SHIFT 0xf 4164 #define UVD_SYS_INT_EN__JOB_DONE_EN__SHIFT 0x10 4165 #define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17 4166 #define UVD_SYS_INT_EN__IDCT_EN__SHIFT 0x18 4167 #define UVD_SYS_INT_EN__MPRD_EN__SHIFT 0x19 4168 #define UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN__SHIFT 0x1a 4169 #define UVD_SYS_INT_EN__CLK_SWT_EN__SHIFT 0x1b 4170 #define UVD_SYS_INT_EN__MIF_HWINT_EN__SHIFT 0x1c 4171 #define UVD_SYS_INT_EN__MPRD_ERR_EN__SHIFT 0x1d 4172 #define UVD_SYS_INT_EN__AVM_INT_EN__SHIFT 0x1f 4173 #define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L 4174 #define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L 4175 #define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L 4176 #define UVD_SYS_INT_EN__CXW_WR_EN_MASK 0x00000008L 4177 #define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L 4178 #define UVD_SYS_INT_EN__LBSI_EN_MASK 0x00000800L 4179 #define UVD_SYS_INT_EN__UDEC_EN_MASK 0x00001000L 4180 #define UVD_SYS_INT_EN__SUVD_EN_MASK 0x00008000L 4181 #define UVD_SYS_INT_EN__JOB_DONE_EN_MASK 0x00010000L 4182 #define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L 4183 #define UVD_SYS_INT_EN__IDCT_EN_MASK 0x01000000L 4184 #define UVD_SYS_INT_EN__MPRD_EN_MASK 0x02000000L 4185 #define UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK 0x04000000L 4186 #define UVD_SYS_INT_EN__CLK_SWT_EN_MASK 0x08000000L 4187 #define UVD_SYS_INT_EN__MIF_HWINT_EN_MASK 0x10000000L 4188 #define UVD_SYS_INT_EN__MPRD_ERR_EN_MASK 0x20000000L 4189 #define UVD_SYS_INT_EN__AVM_INT_EN_MASK 0x80000000L 4190 //UVD_SYS_INT_STATUS 4191 #define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT__SHIFT 0x0 4192 #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT 0x1 4193 #define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT 0x2 4194 #define UVD_SYS_INT_STATUS__CXW_WR_INT__SHIFT 0x3 4195 #define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT 0x6 4196 #define UVD_SYS_INT_STATUS__LBSI_INT__SHIFT 0xb 4197 #define UVD_SYS_INT_STATUS__UDEC_INT__SHIFT 0xc 4198 #define UVD_SYS_INT_STATUS__SUVD_INT__SHIFT 0xf 4199 #define UVD_SYS_INT_STATUS__JOB_DONE_INT__SHIFT 0x10 4200 #define UVD_SYS_INT_STATUS__GPCOM_INT__SHIFT 0x12 4201 #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT 0x17 4202 #define UVD_SYS_INT_STATUS__IDCT_INT__SHIFT 0x18 4203 #define UVD_SYS_INT_STATUS__MPRD_INT__SHIFT 0x19 4204 #define UVD_SYS_INT_STATUS__CLK_SWT_INT__SHIFT 0x1b 4205 #define UVD_SYS_INT_STATUS__MIF_HWINT__SHIFT 0x1c 4206 #define UVD_SYS_INT_STATUS__MPRD_ERR_INT__SHIFT 0x1d 4207 #define UVD_SYS_INT_STATUS__RASCNTL_VCPU_VCODEC_INT__SHIFT 0x1e 4208 #define UVD_SYS_INT_STATUS__AVM_INT__SHIFT 0x1f 4209 #define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT_MASK 0x00000001L 4210 #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK 0x00000002L 4211 #define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK 0x00000004L 4212 #define UVD_SYS_INT_STATUS__CXW_WR_INT_MASK 0x00000008L 4213 #define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK 0x00000040L 4214 #define UVD_SYS_INT_STATUS__LBSI_INT_MASK 0x00000800L 4215 #define UVD_SYS_INT_STATUS__UDEC_INT_MASK 0x00001000L 4216 #define UVD_SYS_INT_STATUS__SUVD_INT_MASK 0x00008000L 4217 #define UVD_SYS_INT_STATUS__JOB_DONE_INT_MASK 0x00010000L 4218 #define UVD_SYS_INT_STATUS__GPCOM_INT_MASK 0x00040000L 4219 #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK 0x00800000L 4220 #define UVD_SYS_INT_STATUS__IDCT_INT_MASK 0x01000000L 4221 #define UVD_SYS_INT_STATUS__MPRD_INT_MASK 0x02000000L 4222 #define UVD_SYS_INT_STATUS__CLK_SWT_INT_MASK 0x08000000L 4223 #define UVD_SYS_INT_STATUS__MIF_HWINT_MASK 0x10000000L 4224 #define UVD_SYS_INT_STATUS__MPRD_ERR_INT_MASK 0x20000000L 4225 #define UVD_SYS_INT_STATUS__RASCNTL_VCPU_VCODEC_INT_MASK 0x40000000L 4226 #define UVD_SYS_INT_STATUS__AVM_INT_MASK 0x80000000L 4227 //UVD_SYS_INT_ACK 4228 #define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0 4229 #define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1 4230 #define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2 4231 #define UVD_SYS_INT_ACK__CXW_WR_ACK__SHIFT 0x3 4232 #define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6 4233 #define UVD_SYS_INT_ACK__LBSI_ACK__SHIFT 0xb 4234 #define UVD_SYS_INT_ACK__UDEC_ACK__SHIFT 0xc 4235 #define UVD_SYS_INT_ACK__SUVD_ACK__SHIFT 0xf 4236 #define UVD_SYS_INT_ACK__JOB_DONE_ACK__SHIFT 0x10 4237 #define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17 4238 #define UVD_SYS_INT_ACK__IDCT_ACK__SHIFT 0x18 4239 #define UVD_SYS_INT_ACK__MPRD_ACK__SHIFT 0x19 4240 #define UVD_SYS_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b 4241 #define UVD_SYS_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c 4242 #define UVD_SYS_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d 4243 #define UVD_SYS_INT_ACK__RASCNTL_VCPU_VCODEC_ACK__SHIFT 0x1e 4244 #define UVD_SYS_INT_ACK__AVM_INT_ACK__SHIFT 0x1f 4245 #define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L 4246 #define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L 4247 #define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L 4248 #define UVD_SYS_INT_ACK__CXW_WR_ACK_MASK 0x00000008L 4249 #define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L 4250 #define UVD_SYS_INT_ACK__LBSI_ACK_MASK 0x00000800L 4251 #define UVD_SYS_INT_ACK__UDEC_ACK_MASK 0x00001000L 4252 #define UVD_SYS_INT_ACK__SUVD_ACK_MASK 0x00008000L 4253 #define UVD_SYS_INT_ACK__JOB_DONE_ACK_MASK 0x00010000L 4254 #define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L 4255 #define UVD_SYS_INT_ACK__IDCT_ACK_MASK 0x01000000L 4256 #define UVD_SYS_INT_ACK__MPRD_ACK_MASK 0x02000000L 4257 #define UVD_SYS_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L 4258 #define UVD_SYS_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L 4259 #define UVD_SYS_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L 4260 #define UVD_SYS_INT_ACK__RASCNTL_VCPU_VCODEC_ACK_MASK 0x40000000L 4261 #define UVD_SYS_INT_ACK__AVM_INT_ACK_MASK 0x80000000L 4262 //UVD_JOB_DONE 4263 #define UVD_JOB_DONE__JOB_DONE__SHIFT 0x0 4264 #define UVD_JOB_DONE__JOB_DONE_MASK 0x00000003L 4265 //UVD_CBUF_ID 4266 #define UVD_CBUF_ID__CBUF_ID__SHIFT 0x0 4267 #define UVD_CBUF_ID__CBUF_ID_MASK 0xFFFFFFFFL 4268 //UVD_CONTEXT_ID 4269 #define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 4270 #define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xFFFFFFFFL 4271 //UVD_CONTEXT_ID2 4272 #define UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT 0x0 4273 #define UVD_CONTEXT_ID2__CONTEXT_ID2_MASK 0xFFFFFFFFL 4274 //UVD_NO_OP 4275 #define UVD_NO_OP__NO_OP__SHIFT 0x0 4276 #define UVD_NO_OP__NO_OP_MASK 0xFFFFFFFFL 4277 //UVD_RB_BASE_LO 4278 #define UVD_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 4279 #define UVD_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 4280 //UVD_RB_BASE_HI 4281 #define UVD_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 4282 #define UVD_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 4283 //UVD_RB_SIZE 4284 #define UVD_RB_SIZE__RB_SIZE__SHIFT 0x4 4285 #define UVD_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L 4286 //UVD_RB_RPTR 4287 #define UVD_RB_RPTR__RB_RPTR__SHIFT 0x4 4288 #define UVD_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 4289 //UVD_RB_WPTR 4290 #define UVD_RB_WPTR__RB_WPTR__SHIFT 0x4 4291 #define UVD_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 4292 //UVD_RB_BASE_LO2 4293 #define UVD_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6 4294 #define UVD_RB_BASE_LO2__RB_BASE_LO_MASK 0xFFFFFFC0L 4295 //UVD_RB_BASE_HI2 4296 #define UVD_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0 4297 #define UVD_RB_BASE_HI2__RB_BASE_HI_MASK 0xFFFFFFFFL 4298 //UVD_RB_SIZE2 4299 #define UVD_RB_SIZE2__RB_SIZE__SHIFT 0x4 4300 #define UVD_RB_SIZE2__RB_SIZE_MASK 0x007FFFF0L 4301 //UVD_RB_RPTR2 4302 #define UVD_RB_RPTR2__RB_RPTR__SHIFT 0x4 4303 #define UVD_RB_RPTR2__RB_RPTR_MASK 0x007FFFF0L 4304 //UVD_RB_WPTR2 4305 #define UVD_RB_WPTR2__RB_WPTR__SHIFT 0x4 4306 #define UVD_RB_WPTR2__RB_WPTR_MASK 0x007FFFF0L 4307 //UVD_RB_BASE_LO3 4308 #define UVD_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6 4309 #define UVD_RB_BASE_LO3__RB_BASE_LO_MASK 0xFFFFFFC0L 4310 //UVD_RB_BASE_HI3 4311 #define UVD_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0 4312 #define UVD_RB_BASE_HI3__RB_BASE_HI_MASK 0xFFFFFFFFL 4313 //UVD_RB_SIZE3 4314 #define UVD_RB_SIZE3__RB_SIZE__SHIFT 0x4 4315 #define UVD_RB_SIZE3__RB_SIZE_MASK 0x007FFFF0L 4316 //UVD_RB_RPTR3 4317 #define UVD_RB_RPTR3__RB_RPTR__SHIFT 0x4 4318 #define UVD_RB_RPTR3__RB_RPTR_MASK 0x007FFFF0L 4319 //UVD_RB_WPTR3 4320 #define UVD_RB_WPTR3__RB_WPTR__SHIFT 0x4 4321 #define UVD_RB_WPTR3__RB_WPTR_MASK 0x007FFFF0L 4322 //UVD_RB_BASE_LO4 4323 #define UVD_RB_BASE_LO4__RB_BASE_LO__SHIFT 0x6 4324 #define UVD_RB_BASE_LO4__RB_BASE_LO_MASK 0xFFFFFFC0L 4325 //UVD_RB_BASE_HI4 4326 #define UVD_RB_BASE_HI4__RB_BASE_HI__SHIFT 0x0 4327 #define UVD_RB_BASE_HI4__RB_BASE_HI_MASK 0xFFFFFFFFL 4328 //UVD_RB_SIZE4 4329 #define UVD_RB_SIZE4__RB_SIZE__SHIFT 0x4 4330 #define UVD_RB_SIZE4__RB_SIZE_MASK 0x007FFFF0L 4331 //UVD_RB_RPTR4 4332 #define UVD_RB_RPTR4__RB_RPTR__SHIFT 0x4 4333 #define UVD_RB_RPTR4__RB_RPTR_MASK 0x007FFFF0L 4334 //UVD_RB_WPTR4 4335 #define UVD_RB_WPTR4__RB_WPTR__SHIFT 0x4 4336 #define UVD_RB_WPTR4__RB_WPTR_MASK 0x007FFFF0L 4337 //UVD_OUT_RB_BASE_LO 4338 #define UVD_OUT_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 4339 #define UVD_OUT_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 4340 //UVD_OUT_RB_BASE_HI 4341 #define UVD_OUT_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 4342 #define UVD_OUT_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 4343 //UVD_OUT_RB_SIZE 4344 #define UVD_OUT_RB_SIZE__RB_SIZE__SHIFT 0x4 4345 #define UVD_OUT_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L 4346 //UVD_OUT_RB_RPTR 4347 #define UVD_OUT_RB_RPTR__RB_RPTR__SHIFT 0x4 4348 #define UVD_OUT_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 4349 //UVD_OUT_RB_WPTR 4350 #define UVD_OUT_RB_WPTR__RB_WPTR__SHIFT 0x4 4351 #define UVD_OUT_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 4352 //UVD_IOV_MAILBOX 4353 #define UVD_IOV_MAILBOX__MAILBOX__SHIFT 0x0 4354 #define UVD_IOV_MAILBOX__MAILBOX_MASK 0xFFFFFFFFL 4355 //UVD_IOV_MAILBOX_RESP 4356 #define UVD_IOV_MAILBOX_RESP__RESP__SHIFT 0x0 4357 #define UVD_IOV_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL 4358 //UVD_RB_ARB_CTRL 4359 #define UVD_RB_ARB_CTRL__SRBM_DROP__SHIFT 0x0 4360 #define UVD_RB_ARB_CTRL__SRBM_DIS__SHIFT 0x1 4361 #define UVD_RB_ARB_CTRL__VCPU_DROP__SHIFT 0x2 4362 #define UVD_RB_ARB_CTRL__VCPU_DIS__SHIFT 0x3 4363 #define UVD_RB_ARB_CTRL__RBC_DROP__SHIFT 0x4 4364 #define UVD_RB_ARB_CTRL__RBC_DIS__SHIFT 0x5 4365 #define UVD_RB_ARB_CTRL__FWOFLD_DROP__SHIFT 0x6 4366 #define UVD_RB_ARB_CTRL__FWOFLD_DIS__SHIFT 0x7 4367 #define UVD_RB_ARB_CTRL__FAST_PATH_EN__SHIFT 0x8 4368 #define UVD_RB_ARB_CTRL__SRBM_DROP_MASK 0x00000001L 4369 #define UVD_RB_ARB_CTRL__SRBM_DIS_MASK 0x00000002L 4370 #define UVD_RB_ARB_CTRL__VCPU_DROP_MASK 0x00000004L 4371 #define UVD_RB_ARB_CTRL__VCPU_DIS_MASK 0x00000008L 4372 #define UVD_RB_ARB_CTRL__RBC_DROP_MASK 0x00000010L 4373 #define UVD_RB_ARB_CTRL__RBC_DIS_MASK 0x00000020L 4374 #define UVD_RB_ARB_CTRL__FWOFLD_DROP_MASK 0x00000040L 4375 #define UVD_RB_ARB_CTRL__FWOFLD_DIS_MASK 0x00000080L 4376 #define UVD_RB_ARB_CTRL__FAST_PATH_EN_MASK 0x00000100L 4377 //UVD_CTX_INDEX 4378 #define UVD_CTX_INDEX__INDEX__SHIFT 0x0 4379 #define UVD_CTX_INDEX__INDEX_MASK 0x000001FFL 4380 //UVD_CTX_DATA 4381 #define UVD_CTX_DATA__DATA__SHIFT 0x0 4382 #define UVD_CTX_DATA__DATA_MASK 0xFFFFFFFFL 4383 //UVD_CXW_WR 4384 #define UVD_CXW_WR__DAT__SHIFT 0x0 4385 #define UVD_CXW_WR__STAT__SHIFT 0x1f 4386 #define UVD_CXW_WR__DAT_MASK 0x0FFFFFFFL 4387 #define UVD_CXW_WR__STAT_MASK 0x80000000L 4388 //UVD_CXW_WR_INT_ID 4389 #define UVD_CXW_WR_INT_ID__ID__SHIFT 0x0 4390 #define UVD_CXW_WR_INT_ID__ID_MASK 0x000000FFL 4391 //UVD_CXW_WR_INT_CTX_ID 4392 #define UVD_CXW_WR_INT_CTX_ID__ID__SHIFT 0x0 4393 #define UVD_CXW_WR_INT_CTX_ID__ID_MASK 0x0FFFFFFFL 4394 //UVD_CXW_INT_ID 4395 #define UVD_CXW_INT_ID__ID__SHIFT 0x0 4396 #define UVD_CXW_INT_ID__ID_MASK 0x000000FFL 4397 //UVD_MPEG2_ERROR 4398 #define UVD_MPEG2_ERROR__STATUS__SHIFT 0x0 4399 #define UVD_MPEG2_ERROR__STATUS_MASK 0xFFFFFFFFL 4400 //UVD_TOP_CTRL 4401 #define UVD_TOP_CTRL__STANDARD__SHIFT 0x0 4402 #define UVD_TOP_CTRL__STD_VERSION__SHIFT 0x4 4403 #define UVD_TOP_CTRL__STANDARD_MASK 0x0000000FL 4404 #define UVD_TOP_CTRL__STD_VERSION_MASK 0x000000F0L 4405 //UVD_YBASE 4406 #define UVD_YBASE__DUM__SHIFT 0x0 4407 #define UVD_YBASE__DUM_MASK 0xFFFFFFFFL 4408 //UVD_UVBASE 4409 #define UVD_UVBASE__DUM__SHIFT 0x0 4410 #define UVD_UVBASE__DUM_MASK 0xFFFFFFFFL 4411 //UVD_PITCH 4412 #define UVD_PITCH__DUM__SHIFT 0x0 4413 #define UVD_PITCH__DUM_MASK 0xFFFFFFFFL 4414 //UVD_WIDTH 4415 #define UVD_WIDTH__DUM__SHIFT 0x0 4416 #define UVD_WIDTH__DUM_MASK 0xFFFFFFFFL 4417 //UVD_HEIGHT 4418 #define UVD_HEIGHT__DUM__SHIFT 0x0 4419 #define UVD_HEIGHT__DUM_MASK 0xFFFFFFFFL 4420 //UVD_PICCOUNT 4421 #define UVD_PICCOUNT__DUM__SHIFT 0x0 4422 #define UVD_PICCOUNT__DUM_MASK 0xFFFFFFFFL 4423 //UVD_MPRD_INITIAL_XY 4424 #define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_X__SHIFT 0x0 4425 #define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_Y__SHIFT 0x10 4426 #define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_X_MASK 0x00000FFFL 4427 #define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_Y_MASK 0x0FFF0000L 4428 //UVD_MPEG2_CTRL 4429 #define UVD_MPEG2_CTRL__EN__SHIFT 0x0 4430 #define UVD_MPEG2_CTRL__TRICK_MODE__SHIFT 0x1 4431 #define UVD_MPEG2_CTRL__NUM_MB_PER_JOB__SHIFT 0x10 4432 #define UVD_MPEG2_CTRL__EN_MASK 0x00000001L 4433 #define UVD_MPEG2_CTRL__TRICK_MODE_MASK 0x00000002L 4434 #define UVD_MPEG2_CTRL__NUM_MB_PER_JOB_MASK 0xFFFF0000L 4435 //UVD_MB_CTL_BUF_BASE 4436 #define UVD_MB_CTL_BUF_BASE__BASE__SHIFT 0x0 4437 #define UVD_MB_CTL_BUF_BASE__BASE_MASK 0xFFFFFFFFL 4438 //UVD_PIC_CTL_BUF_BASE 4439 #define UVD_PIC_CTL_BUF_BASE__BASE__SHIFT 0x0 4440 #define UVD_PIC_CTL_BUF_BASE__BASE_MASK 0xFFFFFFFFL 4441 //UVD_DXVA_BUF_SIZE 4442 #define UVD_DXVA_BUF_SIZE__PIC_SIZE__SHIFT 0x0 4443 #define UVD_DXVA_BUF_SIZE__MB_SIZE__SHIFT 0x10 4444 #define UVD_DXVA_BUF_SIZE__PIC_SIZE_MASK 0x0000FFFFL 4445 #define UVD_DXVA_BUF_SIZE__MB_SIZE_MASK 0xFFFF0000L 4446 //UVD_SCRATCH_NP 4447 #define UVD_SCRATCH_NP__DATA__SHIFT 0x0 4448 #define UVD_SCRATCH_NP__DATA_MASK 0xFFFFFFFFL 4449 //UVD_CLK_SWT_HANDSHAKE 4450 #define UVD_CLK_SWT_HANDSHAKE__CLK_SWT_TYPE__SHIFT 0x0 4451 #define UVD_CLK_SWT_HANDSHAKE__CLK_DOMAIN_SWT__SHIFT 0x8 4452 #define UVD_CLK_SWT_HANDSHAKE__CLK_SWT_TYPE_MASK 0x00000003L 4453 #define UVD_CLK_SWT_HANDSHAKE__CLK_DOMAIN_SWT_MASK 0x00000300L 4454 //UVD_VERSION 4455 #define UVD_VERSION__MINOR_VERSION__SHIFT 0x0 4456 #define UVD_VERSION__MAJOR_VERSION__SHIFT 0x10 4457 #define UVD_VERSION__INSTANCE_ID__SHIFT 0x1c 4458 #define UVD_VERSION__MINOR_VERSION_MASK 0x0000FFFFL 4459 #define UVD_VERSION__MAJOR_VERSION_MASK 0x0FFF0000L 4460 #define UVD_VERSION__INSTANCE_ID_MASK 0xF0000000L 4461 //UVD_GP_SCRATCH0 4462 #define UVD_GP_SCRATCH0__DATA__SHIFT 0x0 4463 #define UVD_GP_SCRATCH0__DATA_MASK 0xFFFFFFFFL 4464 //UVD_GP_SCRATCH1 4465 #define UVD_GP_SCRATCH1__DATA__SHIFT 0x0 4466 #define UVD_GP_SCRATCH1__DATA_MASK 0xFFFFFFFFL 4467 //UVD_GP_SCRATCH2 4468 #define UVD_GP_SCRATCH2__DATA__SHIFT 0x0 4469 #define UVD_GP_SCRATCH2__DATA_MASK 0xFFFFFFFFL 4470 //UVD_GP_SCRATCH3 4471 #define UVD_GP_SCRATCH3__DATA__SHIFT 0x0 4472 #define UVD_GP_SCRATCH3__DATA_MASK 0xFFFFFFFFL 4473 //UVD_GP_SCRATCH4 4474 #define UVD_GP_SCRATCH4__DATA__SHIFT 0x0 4475 #define UVD_GP_SCRATCH4__DATA_MASK 0xFFFFFFFFL 4476 //UVD_GP_SCRATCH5 4477 #define UVD_GP_SCRATCH5__DATA__SHIFT 0x0 4478 #define UVD_GP_SCRATCH5__DATA_MASK 0xFFFFFFFFL 4479 //UVD_GP_SCRATCH6 4480 #define UVD_GP_SCRATCH6__DATA__SHIFT 0x0 4481 #define UVD_GP_SCRATCH6__DATA_MASK 0xFFFFFFFFL 4482 //UVD_GP_SCRATCH7 4483 #define UVD_GP_SCRATCH7__DATA__SHIFT 0x0 4484 #define UVD_GP_SCRATCH7__DATA_MASK 0xFFFFFFFFL 4485 //UVD_GP_SCRATCH8 4486 #define UVD_GP_SCRATCH8__DATA__SHIFT 0x0 4487 #define UVD_GP_SCRATCH8__DATA_MASK 0xFFFFFFFFL 4488 //UVD_GP_SCRATCH9 4489 #define UVD_GP_SCRATCH9__DATA__SHIFT 0x0 4490 #define UVD_GP_SCRATCH9__DATA_MASK 0xFFFFFFFFL 4491 //UVD_GP_SCRATCH10 4492 #define UVD_GP_SCRATCH10__DATA__SHIFT 0x0 4493 #define UVD_GP_SCRATCH10__DATA_MASK 0xFFFFFFFFL 4494 //UVD_GP_SCRATCH11 4495 #define UVD_GP_SCRATCH11__DATA__SHIFT 0x0 4496 #define UVD_GP_SCRATCH11__DATA_MASK 0xFFFFFFFFL 4497 //UVD_GP_SCRATCH12 4498 #define UVD_GP_SCRATCH12__DATA__SHIFT 0x0 4499 #define UVD_GP_SCRATCH12__DATA_MASK 0xFFFFFFFFL 4500 //UVD_GP_SCRATCH13 4501 #define UVD_GP_SCRATCH13__DATA__SHIFT 0x0 4502 #define UVD_GP_SCRATCH13__DATA_MASK 0xFFFFFFFFL 4503 //UVD_GP_SCRATCH14 4504 #define UVD_GP_SCRATCH14__DATA__SHIFT 0x0 4505 #define UVD_GP_SCRATCH14__DATA_MASK 0xFFFFFFFFL 4506 //UVD_GP_SCRATCH15 4507 #define UVD_GP_SCRATCH15__DATA__SHIFT 0x0 4508 #define UVD_GP_SCRATCH15__DATA_MASK 0xFFFFFFFFL 4509 //UVD_GP_SCRATCH16 4510 #define UVD_GP_SCRATCH16__DATA__SHIFT 0x0 4511 #define UVD_GP_SCRATCH16__DATA_MASK 0xFFFFFFFFL 4512 //UVD_GP_SCRATCH17 4513 #define UVD_GP_SCRATCH17__DATA__SHIFT 0x0 4514 #define UVD_GP_SCRATCH17__DATA_MASK 0xFFFFFFFFL 4515 //UVD_GP_SCRATCH18 4516 #define UVD_GP_SCRATCH18__DATA__SHIFT 0x0 4517 #define UVD_GP_SCRATCH18__DATA_MASK 0xFFFFFFFFL 4518 //UVD_GP_SCRATCH19 4519 #define UVD_GP_SCRATCH19__DATA__SHIFT 0x0 4520 #define UVD_GP_SCRATCH19__DATA_MASK 0xFFFFFFFFL 4521 //UVD_GP_SCRATCH20 4522 #define UVD_GP_SCRATCH20__DATA__SHIFT 0x0 4523 #define UVD_GP_SCRATCH20__DATA_MASK 0xFFFFFFFFL 4524 //UVD_GP_SCRATCH21 4525 #define UVD_GP_SCRATCH21__DATA__SHIFT 0x0 4526 #define UVD_GP_SCRATCH21__DATA_MASK 0xFFFFFFFFL 4527 //UVD_GP_SCRATCH22 4528 #define UVD_GP_SCRATCH22__DATA__SHIFT 0x0 4529 #define UVD_GP_SCRATCH22__DATA_MASK 0xFFFFFFFFL 4530 //UVD_GP_SCRATCH23 4531 #define UVD_GP_SCRATCH23__DATA__SHIFT 0x0 4532 #define UVD_GP_SCRATCH23__DATA_MASK 0xFFFFFFFFL 4533 4534 4535 #endif 4536