/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 230 VADDLVps, // Same as VADDLV[su] but with a v4i1 predicate mask enumerator
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H A D | ARMISelLowering.cpp | 1730 case ARMISD::VADDLVps: return "ARMISD::VADDLVps"; in getTargetNodeName() 12438 if (SDValue M = MakeVecReduce(ARMISD::VADDLVps, ARMISD::VADDLVAps, N0, N1)) in PerformADDVecReduce() 12442 if (SDValue M = MakeVecReduce(ARMISD::VADDLVps, ARMISD::VADDLVAps, N1, N0)) in PerformADDVecReduce() 15051 return Create64bitNode(ARMISD::VADDLVps, {A, Mask}); in PerformVECREDUCE_ADDCombine() 15401 (Unsigned ? ARMISD::VADDLVpu : ARMISD::VADDLVps); in PerformIntrinsicCombine()
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 226 VADDLVps, // same as VADDLVs but with a v4i1 predicate mask enumerator
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H A D | ARMISelLowering.cpp | 1725 case ARMISD::VADDLVps: return "ARMISD::VADDLVps"; in getTargetNodeName() 12243 if (SDValue M = MakeVecReduce(ARMISD::VADDLVps, ARMISD::VADDLVAps, N0, N1)) in PerformADDVecReduce() 12247 if (SDValue M = MakeVecReduce(ARMISD::VADDLVps, ARMISD::VADDLVAps, N1, N0)) in PerformADDVecReduce() 15058 (Unsigned ? ARMISD::VADDLVpu : ARMISD::VADDLVps); in PerformIntrinsicCombine()
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 230 VADDLVps, // Same as VADDLV[su] but with a v4i1 predicate mask enumerator
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H A D | ARMISelLowering.cpp | 1737 case ARMISD::VADDLVps: return "ARMISD::VADDLVps"; in getTargetNodeName() 12443 if (SDValue M = MakeVecReduce(ARMISD::VADDLVps, ARMISD::VADDLVAps, N0, N1)) in PerformADDVecReduce() 12447 if (SDValue M = MakeVecReduce(ARMISD::VADDLVps, ARMISD::VADDLVAps, N1, N0)) in PerformADDVecReduce() 15098 return Create64bitNode(ARMISD::VADDLVps, {A, Mask}); in PerformVECREDUCE_ADDCombine() 15455 (Unsigned ? ARMISD::VADDLVpu : ARMISD::VADDLVps); in PerformIntrinsicCombine()
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/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 226 VADDLVps, // same as VADDLVs but with a v4i1 predicate mask enumerator
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H A D | ARMISelLowering.cpp | 1725 case ARMISD::VADDLVps: return "ARMISD::VADDLVps"; in getTargetNodeName() 12246 if (SDValue M = MakeVecReduce(ARMISD::VADDLVps, ARMISD::VADDLVAps, N0, N1)) in PerformADDVecReduce() 12250 if (SDValue M = MakeVecReduce(ARMISD::VADDLVps, ARMISD::VADDLVAps, N1, N0)) in PerformADDVecReduce() 15061 (Unsigned ? ARMISD::VADDLVpu : ARMISD::VADDLVps); in PerformIntrinsicCombine()
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 230 VADDLVps, // Same as VADDLV[su] but with a v4i1 predicate mask enumerator
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H A D | ARMISelLowering.cpp | 1737 case ARMISD::VADDLVps: return "ARMISD::VADDLVps"; in getTargetNodeName() 12443 if (SDValue M = MakeVecReduce(ARMISD::VADDLVps, ARMISD::VADDLVAps, N0, N1)) in PerformADDVecReduce() 12447 if (SDValue M = MakeVecReduce(ARMISD::VADDLVps, ARMISD::VADDLVAps, N1, N0)) in PerformADDVecReduce() 15098 return Create64bitNode(ARMISD::VADDLVps, {A, Mask}); in PerformVECREDUCE_ADDCombine() 15455 (Unsigned ? ARMISD::VADDLVpu : ARMISD::VADDLVps); in PerformIntrinsicCombine()
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 240 VADDLVps, // Same as VADDLV[su] but with a v4i1 predicate mask enumerator
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H A D | ARMISelLowering.cpp | 1741 MAKE_CASE(ARMISD::VADDLVps) in getTargetNodeName() 13123 if (SDValue M = MakeVecReduce(ARMISD::VADDLVps, ARMISD::VADDLVAps, N0, N1)) in PerformADDVecReduce() 13127 if (SDValue M = MakeVecReduce(ARMISD::VADDLVps, ARMISD::VADDLVAps, N1, N0)) in PerformADDVecReduce() 16148 return Create64bitNode(ARMISD::VADDLVps, {A, Mask}); in PerformVECREDUCE_ADDCombine() 16512 (Unsigned ? ARMISD::VADDLVpu : ARMISD::VADDLVps); in PerformIntrinsicCombine()
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 240 VADDLVps, // Same as VADDLV[su] but with a v4i1 predicate mask enumerator
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H A D | ARMISelLowering.cpp | 1741 MAKE_CASE(ARMISD::VADDLVps) in getTargetNodeName() 13123 if (SDValue M = MakeVecReduce(ARMISD::VADDLVps, ARMISD::VADDLVAps, N0, N1)) in PerformADDVecReduce() 13127 if (SDValue M = MakeVecReduce(ARMISD::VADDLVps, ARMISD::VADDLVAps, N1, N0)) in PerformADDVecReduce() 16148 return Create64bitNode(ARMISD::VADDLVps, {A, Mask}); in PerformVECREDUCE_ADDCombine() 16512 (Unsigned ? ARMISD::VADDLVpu : ARMISD::VADDLVps); in PerformIntrinsicCombine()
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 240 VADDLVps, // Same as VADDLV[su] but with a v4i1 predicate mask enumerator
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H A D | ARMISelLowering.cpp | 1741 MAKE_CASE(ARMISD::VADDLVps) in getTargetNodeName() 13123 if (SDValue M = MakeVecReduce(ARMISD::VADDLVps, ARMISD::VADDLVAps, N0, N1)) in PerformADDVecReduce() 13127 if (SDValue M = MakeVecReduce(ARMISD::VADDLVps, ARMISD::VADDLVAps, N1, N0)) in PerformADDVecReduce() 16148 return Create64bitNode(ARMISD::VADDLVps, {A, Mask}); in PerformVECREDUCE_ADDCombine() 16512 (Unsigned ? ARMISD::VADDLVpu : ARMISD::VADDLVps); in PerformIntrinsicCombine()
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 240 VADDLVps, // Same as VADDLV[su] but with a v4i1 predicate mask enumerator
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H A D | ARMISelLowering.cpp | 1754 MAKE_CASE(ARMISD::VADDLVps) in getTargetNodeName() 13359 if (SDValue M = MakeVecReduce(ARMISD::VADDLVps, ARMISD::VADDLVAps, N0, N1)) in PerformADDVecReduce() 13363 if (SDValue M = MakeVecReduce(ARMISD::VADDLVps, ARMISD::VADDLVAps, N1, N0)) in PerformADDVecReduce() 16474 return Create64bitNode(ARMISD::VADDLVps, {A, Mask}); in PerformVECREDUCE_ADDCombine() 16801 (Unsigned ? ARMISD::VADDLVpu : ARMISD::VADDLVps); in PerformIntrinsicCombine()
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 240 VADDLVps, // Same as VADDLV[su] but with a v4i1 predicate mask enumerator
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H A D | ARMISelLowering.cpp | 1741 MAKE_CASE(ARMISD::VADDLVps) in getTargetNodeName() 13123 if (SDValue M = MakeVecReduce(ARMISD::VADDLVps, ARMISD::VADDLVAps, N0, N1)) in PerformADDVecReduce() 13127 if (SDValue M = MakeVecReduce(ARMISD::VADDLVps, ARMISD::VADDLVAps, N1, N0)) in PerformADDVecReduce() 16148 return Create64bitNode(ARMISD::VADDLVps, {A, Mask}); in PerformVECREDUCE_ADDCombine() 16512 (Unsigned ? ARMISD::VADDLVpu : ARMISD::VADDLVps); in PerformIntrinsicCombine()
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 240 VADDLVps, // Same as VADDLV[su] but with a v4i1 predicate mask enumerator
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H A D | ARMISelLowering.cpp | 1741 MAKE_CASE(ARMISD::VADDLVps) in getTargetNodeName() 13123 if (SDValue M = MakeVecReduce(ARMISD::VADDLVps, ARMISD::VADDLVAps, N0, N1)) in PerformADDVecReduce() 13127 if (SDValue M = MakeVecReduce(ARMISD::VADDLVps, ARMISD::VADDLVAps, N1, N0)) in PerformADDVecReduce() 16148 return Create64bitNode(ARMISD::VADDLVps, {A, Mask}); in PerformVECREDUCE_ADDCombine() 16512 (Unsigned ? ARMISD::VADDLVpu : ARMISD::VADDLVps); in PerformIntrinsicCombine()
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