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Searched refs:VADDLVs (Results 1 – 22 of 22) sorted by relevance

/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/ARM/
H A DARMISelLowering.h226 VADDLVs, // sign- or zero-extend elements to i64 and sum, returning enumerator
H A DARMISelLowering.cpp1726 case ARMISD::VADDLVs: return "ARMISD::VADDLVs"; in getTargetNodeName()
12430 if (SDValue M = MakeVecReduce(ARMISD::VADDLVs, ARMISD::VADDLVAs, N0, N1)) in PerformADDVecReduce()
12434 if (SDValue M = MakeVecReduce(ARMISD::VADDLVs, ARMISD::VADDLVAs, N1, N0)) in PerformADDVecReduce()
15035 return Create64bitNode(ARMISD::VADDLVs, {A}); in PerformVECREDUCE_ADDCombine()
15400 (Unsigned ? ARMISD::VADDLVu : ARMISD::VADDLVs) : in PerformIntrinsicCombine()
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/ARM/
H A DARMISelLowering.h222 VADDLVs, // sign- or zero-extend elements to i64 and sum, returning enumerator
H A DARMISelLowering.cpp1721 case ARMISD::VADDLVs: return "ARMISD::VADDLVs"; in getTargetNodeName()
12235 if (SDValue M = MakeVecReduce(ARMISD::VADDLVs, ARMISD::VADDLVAs, N0, N1)) in PerformADDVecReduce()
12239 if (SDValue M = MakeVecReduce(ARMISD::VADDLVs, ARMISD::VADDLVAs, N1, N0)) in PerformADDVecReduce()
14755 return Create64bitNode(ARMISD::VADDLVs, {A}); in PerformVECREDUCE_ADDCombine()
15057 (Unsigned ? ARMISD::VADDLVu : ARMISD::VADDLVs) : in PerformIntrinsicCombine()
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/
H A DARMISelLowering.h226 VADDLVs, // sign- or zero-extend elements to i64 and sum, returning enumerator
H A DARMISelLowering.cpp1733 case ARMISD::VADDLVs: return "ARMISD::VADDLVs"; in getTargetNodeName()
12435 if (SDValue M = MakeVecReduce(ARMISD::VADDLVs, ARMISD::VADDLVAs, N0, N1)) in PerformADDVecReduce()
12439 if (SDValue M = MakeVecReduce(ARMISD::VADDLVs, ARMISD::VADDLVAs, N1, N0)) in PerformADDVecReduce()
15080 return Create64bitNode(ARMISD::VADDLVs, {A}); in PerformVECREDUCE_ADDCombine()
15454 (Unsigned ? ARMISD::VADDLVu : ARMISD::VADDLVs) : in PerformIntrinsicCombine()
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/ARM/
H A DARMISelLowering.h222 VADDLVs, // sign- or zero-extend elements to i64 and sum, returning enumerator
H A DARMISelLowering.cpp1721 case ARMISD::VADDLVs: return "ARMISD::VADDLVs"; in getTargetNodeName()
12238 if (SDValue M = MakeVecReduce(ARMISD::VADDLVs, ARMISD::VADDLVAs, N0, N1)) in PerformADDVecReduce()
12242 if (SDValue M = MakeVecReduce(ARMISD::VADDLVs, ARMISD::VADDLVAs, N1, N0)) in PerformADDVecReduce()
14758 return Create64bitNode(ARMISD::VADDLVs, {A}); in PerformVECREDUCE_ADDCombine()
15060 (Unsigned ? ARMISD::VADDLVu : ARMISD::VADDLVs) : in PerformIntrinsicCombine()
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/
H A DARMISelLowering.h226 VADDLVs, // sign- or zero-extend elements to i64 and sum, returning enumerator
H A DARMISelLowering.cpp1733 case ARMISD::VADDLVs: return "ARMISD::VADDLVs"; in getTargetNodeName()
12435 if (SDValue M = MakeVecReduce(ARMISD::VADDLVs, ARMISD::VADDLVAs, N0, N1)) in PerformADDVecReduce()
12439 if (SDValue M = MakeVecReduce(ARMISD::VADDLVs, ARMISD::VADDLVAs, N1, N0)) in PerformADDVecReduce()
15080 return Create64bitNode(ARMISD::VADDLVs, {A}); in PerformVECREDUCE_ADDCombine()
15454 (Unsigned ? ARMISD::VADDLVu : ARMISD::VADDLVs) : in PerformIntrinsicCombine()
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/ARM/
H A DARMISelLowering.h236 VADDLVs, // sign- or zero-extend elements to i64 and sum, returning enumerator
H A DARMISelLowering.cpp1737 MAKE_CASE(ARMISD::VADDLVs) in getTargetNodeName()
13115 if (SDValue M = MakeVecReduce(ARMISD::VADDLVs, ARMISD::VADDLVAs, N0, N1)) in PerformADDVecReduce()
13119 if (SDValue M = MakeVecReduce(ARMISD::VADDLVs, ARMISD::VADDLVAs, N1, N0)) in PerformADDVecReduce()
16132 return Create64bitNode(ARMISD::VADDLVs, {A}); in PerformVECREDUCE_ADDCombine()
16511 (Unsigned ? ARMISD::VADDLVu : ARMISD::VADDLVs) : in PerformIntrinsicCombine()
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/ARM/
H A DARMISelLowering.h236 VADDLVs, // sign- or zero-extend elements to i64 and sum, returning enumerator
H A DARMISelLowering.cpp1737 MAKE_CASE(ARMISD::VADDLVs) in getTargetNodeName()
13115 if (SDValue M = MakeVecReduce(ARMISD::VADDLVs, ARMISD::VADDLVAs, N0, N1)) in PerformADDVecReduce()
13119 if (SDValue M = MakeVecReduce(ARMISD::VADDLVs, ARMISD::VADDLVAs, N1, N0)) in PerformADDVecReduce()
16132 return Create64bitNode(ARMISD::VADDLVs, {A}); in PerformVECREDUCE_ADDCombine()
16511 (Unsigned ? ARMISD::VADDLVu : ARMISD::VADDLVs) : in PerformIntrinsicCombine()
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.h236 VADDLVs, // sign- or zero-extend elements to i64 and sum, returning enumerator
H A DARMISelLowering.cpp1737 MAKE_CASE(ARMISD::VADDLVs) in getTargetNodeName()
13115 if (SDValue M = MakeVecReduce(ARMISD::VADDLVs, ARMISD::VADDLVAs, N0, N1)) in PerformADDVecReduce()
13119 if (SDValue M = MakeVecReduce(ARMISD::VADDLVs, ARMISD::VADDLVAs, N1, N0)) in PerformADDVecReduce()
16132 return Create64bitNode(ARMISD::VADDLVs, {A}); in PerformVECREDUCE_ADDCombine()
16511 (Unsigned ? ARMISD::VADDLVu : ARMISD::VADDLVs) : in PerformIntrinsicCombine()
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/ARM/
H A DARMISelLowering.h236 VADDLVs, // sign- or zero-extend elements to i64 and sum, returning enumerator
H A DARMISelLowering.cpp1750 MAKE_CASE(ARMISD::VADDLVs) in getTargetNodeName()
13351 if (SDValue M = MakeVecReduce(ARMISD::VADDLVs, ARMISD::VADDLVAs, N0, N1)) in PerformADDVecReduce()
13355 if (SDValue M = MakeVecReduce(ARMISD::VADDLVs, ARMISD::VADDLVAs, N1, N0)) in PerformADDVecReduce()
16459 return Create64bitNode(ARMISD::VADDLVs, {A}); in PerformVECREDUCE_ADDCombine()
16800 (Unsigned ? ARMISD::VADDLVu : ARMISD::VADDLVs) : in PerformIntrinsicCombine()
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/
H A DARMISelLowering.h236 VADDLVs, // sign- or zero-extend elements to i64 and sum, returning enumerator
H A DARMISelLowering.cpp1737 MAKE_CASE(ARMISD::VADDLVs) in getTargetNodeName()
13115 if (SDValue M = MakeVecReduce(ARMISD::VADDLVs, ARMISD::VADDLVAs, N0, N1)) in PerformADDVecReduce()
13119 if (SDValue M = MakeVecReduce(ARMISD::VADDLVs, ARMISD::VADDLVAs, N1, N0)) in PerformADDVecReduce()
16132 return Create64bitNode(ARMISD::VADDLVs, {A}); in PerformVECREDUCE_ADDCombine()
16511 (Unsigned ? ARMISD::VADDLVu : ARMISD::VADDLVs) : in PerformIntrinsicCombine()
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/
H A DARMISelLowering.h236 VADDLVs, // sign- or zero-extend elements to i64 and sum, returning enumerator
H A DARMISelLowering.cpp1737 MAKE_CASE(ARMISD::VADDLVs) in getTargetNodeName()
13115 if (SDValue M = MakeVecReduce(ARMISD::VADDLVs, ARMISD::VADDLVAs, N0, N1)) in PerformADDVecReduce()
13119 if (SDValue M = MakeVecReduce(ARMISD::VADDLVs, ARMISD::VADDLVAs, N1, N0)) in PerformADDVecReduce()
16132 return Create64bitNode(ARMISD::VADDLVs, {A}); in PerformVECREDUCE_ADDCombine()
16511 (Unsigned ? ARMISD::VADDLVu : ARMISD::VADDLVs) : in PerformIntrinsicCombine()