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Searched refs:ZEXT (Results 1 – 25 of 2270) sorted by relevance

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/dports/net/binkd/binkd-1.0.4/
H A D	zlibdl.h	`63 #define ZEXT macro 65 #define ZEXT WINAPI macro 69 #define ZEXT macro 72 #define ZEXT macro 104 extern int ZEXT (ZEXP dl_deflate)(z_stream , int); 105 extern int ZEXT (ZEXP dl_deflateEnd)(z_stream ); 107 extern int ZEXT (ZEXP dl_inflate)(z_stream , int); 108 extern int ZEXT (ZEXP dl_inflateEnd)(z_stream ); 135 extern int ZEXT (ZEXP dl_BZ2_bzCompress)(bz_stream , int); 136 extern int ZEXT (ZEXP dl_BZ2_bzCompressEnd)(bz_stream ); [all …]`
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/X86/GlobalISel/
H A D	x86_64-irtranslator.ll	`10 ; CHECK: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[TRUNC]](s1) 11 ; CHECK: $al = COPY [[ZEXT]](s8) 24 ; CHECK: $ax = COPY [[ZEXT]](s16) 37 ; CHECK: $eax = COPY [[ZEXT]](s32) 50 ; CHECK: $rax = COPY [[ZEXT]](s64) 63 ; CHECK: $ax = COPY [[ZEXT]](s16) 76 ; CHECK: $eax = COPY [[ZEXT]](s32) 89 ; CHECK: $rax = COPY [[ZEXT]](s64) 102 ; CHECK: $eax = COPY [[ZEXT]](s32) 115 ; CHECK: $rax = COPY [[ZEXT]](s64) [all …]`
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/GlobalISel/
H A D	irtranslator-memcpy-inline.ll	11 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) 12 …; CHECK: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64), 0 :: (store (s8) into %ir.dst), (l… 26 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) 27 …; CHECK: G_MEMCPY_INLINE [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64) :: (store (s8) into %ir.dst)… 41 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) 56 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) 71 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) 72 …; CHECK: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64), 1 :: (store (s8) into %ir.dst), (l… 86 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) 101 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) [all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AArch64/GlobalISel/
H A D	irtranslator-memcpy-inline.ll	11 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) 12 …; CHECK: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64), 0 :: (store (s8) into %ir.dst), (l… 26 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) 27 …; CHECK: G_MEMCPY_INLINE [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64) :: (store (s8) into %ir.dst)… 41 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) 56 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) 71 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) 72 …; CHECK: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64), 1 :: (store (s8) into %ir.dst), (l… 86 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) 101 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) [all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/GlobalISel/
H A D	irtranslator-memcpy-inline.ll	11 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) 12 …; CHECK: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64), 0 :: (store (s8) into %ir.dst), (l… 26 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) 27 …; CHECK: G_MEMCPY_INLINE [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64) :: (store (s8) into %ir.dst)… 41 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) 56 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) 71 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) 72 …; CHECK: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64), 1 :: (store (s8) into %ir.dst), (l… 86 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) 101 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) [all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/GlobalISel/
H A D	irtranslator-memcpy-inline.ll	11 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) 12 …; CHECK: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64), 0 :: (store (s8) into %ir.dst), (l… 26 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) 27 …; CHECK: G_MEMCPY_INLINE [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64) :: (store (s8) into %ir.dst)… 41 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) 56 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) 71 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) 72 …; CHECK: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64), 1 :: (store (s8) into %ir.dst), (l… 86 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) 101 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) [all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AArch64/GlobalISel/
H A D	irtranslator-memcpy-inline.ll	11 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) 12 …; CHECK: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64), 0 :: (store (s8) into %ir.dst), (l… 26 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) 27 …; CHECK: G_MEMCPY_INLINE [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64) :: (store (s8) into %ir.dst)… 41 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) 56 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) 71 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) 72 …; CHECK: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64), 1 :: (store (s8) into %ir.dst), (l… 86 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) 101 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) [all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/Transforms/InstSimplify/
H A D	cmp_ext.ll	7 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 8 ; CHECK-NEXT: [[CMP:%.]] = icmp uge i64 [[ZEXT]], [[SEXT]] 30 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 31 ; CHECK-NEXT: [[CMP:%.]] = icmp ult i64 [[ZEXT]], [[SEXT]] 63 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 86 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 109 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 132 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 145 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 168 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 [all …]
/dports/devel/llvm11/llvm-11.0.1.src/test/Transforms/InstSimplify/
H A D	cmp_ext.ll	7 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 8 ; CHECK-NEXT: [[CMP:%.]] = icmp uge i64 [[ZEXT]], [[SEXT]] 30 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 31 ; CHECK-NEXT: [[CMP:%.]] = icmp ult i64 [[ZEXT]], [[SEXT]] 63 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 86 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 109 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 132 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 145 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 168 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 [all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/Transforms/InstSimplify/
H A D	cmp_ext.ll	7 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 8 ; CHECK-NEXT: [[CMP:%.]] = icmp uge i64 [[ZEXT]], [[SEXT]] 30 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 31 ; CHECK-NEXT: [[CMP:%.]] = icmp ult i64 [[ZEXT]], [[SEXT]] 63 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 86 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 109 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 132 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 145 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 168 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 [all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/Transforms/InstSimplify/
H A D	cmp_ext.ll	7 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 8 ; CHECK-NEXT: [[CMP:%.]] = icmp uge i64 [[ZEXT]], [[SEXT]] 30 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 31 ; CHECK-NEXT: [[CMP:%.]] = icmp ult i64 [[ZEXT]], [[SEXT]] 63 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 86 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 109 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 132 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 145 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 168 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 [all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/Transforms/InstSimplify/
H A D	cmp_ext.ll	7 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 8 ; CHECK-NEXT: [[CMP:%.]] = icmp uge i64 [[ZEXT]], [[SEXT]] 30 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 31 ; CHECK-NEXT: [[CMP:%.]] = icmp ult i64 [[ZEXT]], [[SEXT]] 63 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 86 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 109 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 132 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 145 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 168 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 [all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/Transforms/InstSimplify/
H A D	cmp_ext.ll	7 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 8 ; CHECK-NEXT: [[CMP:%.]] = icmp uge i64 [[ZEXT]], [[SEXT]] 30 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 31 ; CHECK-NEXT: [[CMP:%.]] = icmp ult i64 [[ZEXT]], [[SEXT]] 63 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 86 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 109 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 132 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 145 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 168 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 [all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/Transforms/InstSimplify/
H A D	cmp_ext.ll	7 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 8 ; CHECK-NEXT: [[CMP:%.]] = icmp uge i64 [[ZEXT]], [[SEXT]] 30 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 31 ; CHECK-NEXT: [[CMP:%.]] = icmp ult i64 [[ZEXT]], [[SEXT]] 63 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 86 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 109 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 132 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 145 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 168 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 [all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/Transforms/InstSimplify/
H A D	cmp_ext.ll	7 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 8 ; CHECK-NEXT: [[CMP:%.]] = icmp uge i64 [[ZEXT]], [[SEXT]] 30 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 31 ; CHECK-NEXT: [[CMP:%.]] = icmp ult i64 [[ZEXT]], [[SEXT]] 63 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 86 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 109 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 132 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 145 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 168 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 [all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/Transforms/InstSimplify/
H A D	cmp_ext.ll	7 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 8 ; CHECK-NEXT: [[CMP:%.]] = icmp uge i64 [[ZEXT]], [[SEXT]] 30 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 31 ; CHECK-NEXT: [[CMP:%.]] = icmp ult i64 [[ZEXT]], [[SEXT]] 63 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 86 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 109 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 132 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 145 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 168 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 [all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/Transforms/InstSimplify/
H A D	cmp_ext.ll	7 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 8 ; CHECK-NEXT: [[CMP:%.]] = icmp uge i64 [[ZEXT]], [[SEXT]] 30 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 31 ; CHECK-NEXT: [[CMP:%.]] = icmp ult i64 [[ZEXT]], [[SEXT]] 63 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 86 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 109 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 132 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 145 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 168 ; CHECK-NEXT: [[ZEXT:%.]] = zext i32 [[X]] to i64 [all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A D	legalize-zextload-flat.mir	70 ; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32) 71 ; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 75 ; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32) 76 ; VI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 90 ; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32) 91 ; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 96 ; VI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 110 ; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32) 111 ; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 115 ; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32) [all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/GlobalISel/
H A D	legalize-zextload-flat.mir	70 ; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32) 71 ; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 75 ; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32) 76 ; VI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 90 ; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32) 91 ; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 96 ; VI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 110 ; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32) 111 ; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 115 ; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32) [all …]
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A D	legalize-zextload-flat.mir	70 ; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32) 71 ; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 75 ; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32) 76 ; VI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 90 ; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32) 91 ; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 96 ; VI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 110 ; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32) 111 ; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 115 ; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32) [all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A D	legalize-zextload-flat.mir	68 ; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32) 69 ; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 73 ; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32) 74 ; VI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 88 ; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32) 89 ; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 94 ; VI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 108 ; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32) 109 ; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 113 ; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32) [all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A D	legalize-zextload-flat.mir	70 ; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32) 71 ; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 75 ; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32) 76 ; VI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 90 ; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32) 91 ; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 96 ; VI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 110 ; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32) 111 ; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 115 ; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32) [all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A D	legalize-zextload-flat.mir	70 ; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32) 71 ; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 75 ; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32) 76 ; VI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 90 ; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32) 91 ; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 96 ; VI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 110 ; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32) 111 ; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 115 ; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32) [all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/mlir/test/Conversion/SPIRVToLLVM/
H A D	shift-ops-to-llvm.mlir	19 // CHECK: %[[ZEXT:.]] = llvm.zext %{{.}} : i16 to i32 20 // CHECK: llvm.ashr %{{.}}, %[[ZEXT]] : i32 37 // CHECK: %[[ZEXT:.]] = llvm.zext %{{.}} : vector<4xi32> to vector<4xi64> 38 // CHECK: llvm.ashr %{{.}}, %[[ZEXT]] : vector<4xi64> 59 // CHECK: %[[ZEXT:.]] = llvm.zext %{{.}} : i16 to i32 60 // CHECK: llvm.lshr %{{.}}, %[[ZEXT]] : i32 77 // CHECK: %[[ZEXT:.]] = llvm.zext %{{.}} : vector<4xi32> to vector<4xi64> 78 // CHECK: llvm.lshr %{{.}}, %[[ZEXT]] : vector<4xi64> 99 // CHECK: %[[ZEXT:.]] = llvm.zext %{{.}} : i16 to i32 100 // CHECK: llvm.shl %{{.*}}, %[[ZEXT]] : i32 [all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/mlir/test/Conversion/SPIRVToLLVM/
H A D	shift-ops-to-llvm.mlir	19 // CHECK: %[[ZEXT:.]] = llvm.zext %{{.}} : i16 to i32 20 // CHECK: llvm.ashr %{{.}}, %[[ZEXT]] : i32 37 // CHECK: %[[ZEXT:.]] = llvm.zext %{{.}} : vector<4xi32> to vector<4xi64> 38 // CHECK: llvm.ashr %{{.}}, %[[ZEXT]] : vector<4xi64> 59 // CHECK: %[[ZEXT:.]] = llvm.zext %{{.}} : i16 to i32 60 // CHECK: llvm.lshr %{{.}}, %[[ZEXT]] : i32 77 // CHECK: %[[ZEXT:.]] = llvm.zext %{{.}} : vector<4xi32> to vector<4xi64> 78 // CHECK: llvm.lshr %{{.}}, %[[ZEXT]] : vector<4xi64> 99 // CHECK: %[[ZEXT:.]] = llvm.zext %{{.}} : i16 to i32 100 // CHECK: llvm.shl %{{.*}}, %[[ZEXT]] : i32 [all …]

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