| /dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/testsuite/sim/m32r/ |
| H A D | and3.cgs | 1 # m32r testcase for and3 $dr,$sr,#$uimm16
8 .global and3
9 and3:
13 and3 r4, r5, #3
|
| /dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/testsuite/sim/m32r/ |
| H A D | and3.cgs | 1 # m32r testcase for and3 $dr,$sr,#$uimm16
8 .global and3
9 and3:
13 and3 r4, r5, #3
|
| /dports/devel/avr-gdb/gdb-7.3.1/sim/testsuite/sim/m32r/ |
| H A D | and3.cgs | 1 # m32r testcase for and3 $dr,$sr,#$uimm16
8 .global and3
9 and3:
13 and3 r4, r5, #3
|
| /dports/devel/gdb761/gdb-7.6.1/sim/testsuite/sim/m32r/ |
| H A D | and3.cgs | 1 # m32r testcase for and3 $dr,$sr,#$uimm16
8 .global and3
9 and3:
13 and3 r4, r5, #3
|
| /dports/cad/ghdl/ghdl-1.0.0/testsuite/synth/comp01/ |
| H A D | testsuite.sh | 6 analyze and3.vhdl and6.vhdl tb_and6.vhdl
10 synth and3.vhdl and6.vhdl -e and6 > syn_and6.vhdl
16 analyze and3.vhdl and6comp.vhdl tb_and6.vhdl
20 synth and3.vhdl and6comp.vhdl -e and6 > syn_and6.vhdl
|
| H A D | and3.vhdl | 4 entity and3 is entity
7 end and3;
9 architecture behav of and3 is
|
| H A D | and6comp.vhdl | 10 component and3 is
16 a1: and3
18 a2: and3
|
| /dports/math/cudd/cudd-3.0.0/dddmp/exp/ |
| H A D | test3.sh.in | 49 ${dest}/2and3.bdd.tmp
74 diff --strip-trailing-cr --brief ${where}/2and3.bdd ${dest}/2and3.bdd.tmp
79 rm -f ${dest}/0or1.bdd.tmp ${dest}/2and3.bdd.tmp ${dest}/4xor5.bdd.tmp
|
| /dports/cad/lepton-eda/lepton-eda-1.9.17/utils/netlist/examples/ |
| H A D | 7447.sch | 156 C 29400 28700 1 0 0 and3-1.sym
161 C 29400 27900 1 0 0 and3-1.sym
166 C 29400 25900 1 0 0 and3-1.sym
171 C 29400 24600 1 0 0 and3-1.sym
176 C 29400 23800 1 0 0 and3-1.sym
181 C 29400 23000 1 0 0 and3-1.sym
186 C 29400 19000 1 0 0 and3-1.sym
191 C 29400 17900 1 0 0 and3-1.sym
|
| /dports/cad/geda/geda-gaf-1.8.2/gnetlist/examples/ |
| H A D | 7447.sch | 156 C 29400 28700 1 0 0 and3-1.sym
161 C 29400 27900 1 0 0 and3-1.sym
166 C 29400 25900 1 0 0 and3-1.sym
171 C 29400 24600 1 0 0 and3-1.sym
176 C 29400 23800 1 0 0 and3-1.sym
181 C 29400 23000 1 0 0 and3-1.sym
186 C 29400 19000 1 0 0 and3-1.sym
191 C 29400 17900 1 0 0 and3-1.sym
|
| /dports/cad/yosys/yosys-yosys-0.12/tests/asicworld/ |
| H A D | code_hdl_models_full_adder_gates.v | 10 wire and1,and2,and3,sum1; net
14 U_and3 (and3,y,z);
15 or U_or (carry,and1,and2,and3);
|
| /dports/cad/ghdl/ghdl-1.0.0/testsuite/synth/lib01/ |
| H A D | testsuite.sh | 6 analyze and3.vhdl tb_and3.vhdl
11 synth --work=work and3.vhdl --work=mylib and2.vhdl --work=work -e and3 > syn_and3.vhdl
|
| H A D | and3.vhdl | 5 entity and3 is entity
8 end and3;
10 architecture behav of and3 is
|
| /dports/lang/qmasm/qmasm-4.1/examples/ |
| H A D | and4.qmasm | 20 !use_macro and_chain $and1 $and2 $and3
24 D = $and3.B
25 Y = $and3.Y
|
| /dports/cad/ghdl/ghdl-1.0.0/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/ |
| H A D | inline_24.vhd | 22 entity and3 is entity
25 end entity and3;
33 architecture functional of and3 is
73 g1 : entity work.and3 port map ( a => s1, b => s2, not_z => ctrl1 );
90 g1 : entity work.and3 port map ( a => s1, b => s2, not_z => ctrl1,
|
| /dports/cad/ghdl/ghdl-1.0.0/testsuite/vests/vhdl-93/ashenden/compliant/ |
| H A D | ch_05_ch_05_24.vhd | 29 entity and3 is entity
32 end entity and3;
36 architecture functional of and3 is
70 g1 : entity work.and3 port map (a => s1, b => s2, not_z => ctrl1);
83 g1 : entity work.and3 port map (a => s1, b => s2, not_z => ctrl1,
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/PowerPC/ |
| H A D | ppc-crbits-onoff.ll | 11 %and3 = and i1 %tobool, %lnot
12 %and = zext i1 %and3 to i32
34 %and3 = and i1 %tobool, %lnot
35 %and = zext i1 %and3 to i32
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/PowerPC/ |
| H A D | ppc-crbits-onoff.ll | 11 %and3 = and i1 %tobool, %lnot
12 %and = zext i1 %and3 to i32
34 %and3 = and i1 %tobool, %lnot
35 %and = zext i1 %and3 to i32
|
| /dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/PowerPC/ |
| H A D | ppc-crbits-onoff.ll | 11 %and3 = and i1 %tobool, %lnot
12 %and = zext i1 %and3 to i32
34 %and3 = and i1 %tobool, %lnot
35 %and = zext i1 %and3 to i32
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/PowerPC/ |
| H A D | ppc-crbits-onoff.ll | 11 %and3 = and i1 %tobool, %lnot
12 %and = zext i1 %and3 to i32
34 %and3 = and i1 %tobool, %lnot
35 %and = zext i1 %and3 to i32
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/PowerPC/ |
| H A D | ppc-crbits-onoff.ll | 11 %and3 = and i1 %tobool, %lnot
12 %and = zext i1 %and3 to i32
34 %and3 = and i1 %tobool, %lnot
35 %and = zext i1 %and3 to i32
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/PowerPC/ |
| H A D | ppc-crbits-onoff.ll | 11 %and3 = and i1 %tobool, %lnot
12 %and = zext i1 %and3 to i32
34 %and3 = and i1 %tobool, %lnot
35 %and = zext i1 %and3 to i32
|
| /dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/PowerPC/ |
| H A D | ppc-crbits-onoff.ll | 11 %and3 = and i1 %tobool, %lnot
12 %and = zext i1 %and3 to i32
34 %and3 = and i1 %tobool, %lnot
35 %and = zext i1 %and3 to i32
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/ |
| H A D | ppc-crbits-onoff.ll | 11 %and3 = and i1 %tobool, %lnot
12 %and = zext i1 %and3 to i32
34 %and3 = and i1 %tobool, %lnot
35 %and = zext i1 %and3 to i32
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/ |
| H A D | ppc-crbits-onoff.ll | 11 %and3 = and i1 %tobool, %lnot
12 %and = zext i1 %and3 to i32
34 %and3 = and i1 %tobool, %lnot
35 %and = zext i1 %and3 to i32
|