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Searched refs:axi_parents (Results 1 – 25 of 324) sorted by relevance

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/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/clk/mediatek/
H A Dclk-mt8135.c102 static const char * const axi_parents[] __initconst = { variable
352 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
H A Dclk-mt7629.c90 static const char * const axi_parents[] = { variable
487 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
H A Dclk-mt7622.c115 static const char * const axi_parents[] = { variable
515 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
H A Dclk-mt6797.c88 static const char * const axi_parents[] = { variable
328 MUX(CLK_TOP_MUX_AXI, "axi_sel", axi_parents,
H A Dclk-mt2701.c144 static const char * const axi_parents[] = { variable
488 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/clk/mediatek/
H A Dclk-mt8135.c102 static const char * const axi_parents[] __initconst = { variable
352 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
H A Dclk-mt7629.c90 static const char * const axi_parents[] = { variable
487 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
H A Dclk-mt7622.c115 static const char * const axi_parents[] = { variable
515 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
H A Dclk-mt6797.c88 static const char * const axi_parents[] = { variable
328 MUX(CLK_TOP_MUX_AXI, "axi_sel", axi_parents,
H A Dclk-mt2701.c144 static const char * const axi_parents[] = { variable
488 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/clk/mediatek/
H A Dclk-mt8135.c102 static const char * const axi_parents[] __initconst = { variable
352 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
H A Dclk-mt7629.c90 static const char * const axi_parents[] = { variable
487 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
H A Dclk-mt6797.c88 static const char * const axi_parents[] = { variable
328 MUX(CLK_TOP_MUX_AXI, "axi_sel", axi_parents,
H A Dclk-mt7622.c115 static const char * const axi_parents[] = { variable
515 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
H A Dclk-mt2701.c144 static const char * const axi_parents[] = { variable
488 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
/dports/sysutils/u-boot-tools/u-boot-2020.07/drivers/clk/mediatek/
H A Dclk-mt7622.c142 static const int axi_parents[] = { variable
313 MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/clk/mediatek/
H A Dclk-mt7629.c150 static const int axi_parents[] = { variable
363 MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/clk/mediatek/
H A Dclk-mt7629.c150 static const int axi_parents[] = { variable
363 MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/clk/mediatek/
H A Dclk-mt7629.c150 static const int axi_parents[] = { variable
363 MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/clk/mediatek/
H A Dclk-mt7629.c150 static const int axi_parents[] = { variable
363 MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/drivers/clk/mediatek/
H A Dclk-mt7629.c150 static const int axi_parents[] = { variable
363 MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt7622.c142 static const int axi_parents[] = { variable
313 MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt7622.c142 static const int axi_parents[] = { variable
313 MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
H A Dclk-mt7629.c153 static const int axi_parents[] = { variable
366 MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
H A Dclk-mt8512.c136 static const int axi_parents[] = { variable
451 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, axi_parents,

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