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/dports/cad/verilator/verilator-4.216/test_regress/t/
H A Dt_math_vliw.v23 wire [223:0] bxiouf; net
27 .bxiouf (bxiouf),
46 sum <= {sum[222:0],sum[223]} ^ bxiouf;
66 output wire [223:0] bxiouf port
75 assign bxiouf = {rzyeut[7:0],