1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2005 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/
8   // Inputs
9   clk
10   );
11
12   input clk;
13   integer cyc; initial cyc = 0;
14   reg [7:0] crc;
15   reg [223:0] sum;
16
17   wire [255:0] mglehy = {32{~crc}};
18   wire [215:0] drricx = {27{crc}};
19   wire [15:0]  apqrli = {2{~crc}};
20   wire [2:0]   szlfpf = crc[2:0];
21   wire [15:0]  dzosui = {2{crc}};
22   wire [31:0]  zndrba = {16{crc[1:0]}};
23   wire [223:0] bxiouf;
24
25   vliw vliw (
26	      // Outputs
27	      .bxiouf (bxiouf),
28	      // Inputs
29	      .mglehy	(mglehy[255:0]),
30	      .drricx	(drricx[215:0]),
31	      .apqrli	(apqrli[15:0]),
32	      .szlfpf	(szlfpf[2:0]),
33	      .dzosui	(dzosui[15:0]),
34	      .zndrba	(zndrba[31:0]));
35
36   always @ (posedge clk) begin
37      cyc <= cyc + 1;
38      crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
39      if (cyc==0) begin
40	 // Setup
41	 crc <= 8'hed;
42	 sum <= 224'h0;
43      end
44      else if (cyc<90) begin
45	 //$write("[%0t] cyc==%0d BXI=%x\n", $time, cyc, bxiouf);
46	 sum <= {sum[222:0],sum[223]} ^ bxiouf;
47      end
48      else if (cyc==99) begin
49	 $write("[%0t] cyc==%0d crc=%b %x\n", $time, cyc, crc, sum);
50	 if (crc !== 8'b01110000) $stop;
51	 if (sum !== 224'h1fdff998855c3c38d467e28124847831f9ad6d4a09f2801098f032a8) $stop;
52	 $write("*-* All Finished *-*\n");
53	 $finish;
54      end
55   end
56
57endmodule
58
59module vliw (
60	     input[255:0]  mglehy,
61	     input[215:0]  drricx,
62	     input[15:0]   apqrli,
63	     input[2:0]    szlfpf,
64	     input[15:0]   dzosui,
65	     input[31:0]   zndrba,
66	     output wire [223:0] bxiouf
67	     );
68
69   wire [463:0] zhknfc  =   ({29{~apqrli}} & {mglehy, drricx[215:8]})
70		| ({29{apqrli}}  & {mglehy[247:0], drricx});
71   wire [335:0] umntwz =   ({21{~dzosui}} & zhknfc[463:128])
72		| ({21{dzosui}}  & zhknfc[335:0]);
73   wire [335:0] viuvoc = umntwz << {szlfpf, 4'b0000};
74   wire [223:0] rzyeut = viuvoc[335:112];
75   assign bxiouf       = {rzyeut[7:0],
76             		  rzyeut[15:8],
77             		  rzyeut[23:16],
78             		  rzyeut[31:24],
79             		  rzyeut[39:32],
80             		  rzyeut[47:40],
81             		  rzyeut[55:48],
82             		  rzyeut[63:56],
83             		  rzyeut[71:64],
84             		  rzyeut[79:72],
85             		  rzyeut[87:80],
86             		  rzyeut[95:88],
87             		  rzyeut[103:96],
88             		  rzyeut[111:104],
89             		  rzyeut[119:112],
90             		  rzyeut[127:120],
91             		  rzyeut[135:128],
92             		  rzyeut[143:136],
93             		  rzyeut[151:144],
94             		  rzyeut[159:152],
95             		  rzyeut[167:160],
96             		  rzyeut[175:168],
97             		  rzyeut[183:176],
98             		  rzyeut[191:184],
99             		  rzyeut[199:192],
100             		  rzyeut[207:200],
101             		  rzyeut[215:208],
102             		  rzyeut[223:216]};
103
104endmodule
105