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Searched refs:cond_reg (Results 1 – 25 of 63) sorted by relevance

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/dports/emulators/qemu60/qemu-6.0.0/roms/openbios/include/arch/sparc32/
H A Ddma.h28 __volatile__ __u32 cond_reg; /* DMA condition register */ member
141 #define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))
143 #define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))
144 #define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
145 #define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
146 #define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
147 #define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
179 while((regs->cond_reg&bit) && (ctr>0)) {
195 regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \
197 regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \
[all …]
/dports/emulators/qemu42/qemu-4.2.1/roms/openbios/include/arch/sparc32/
H A Ddma.h28 __volatile__ __u32 cond_reg; /* DMA condition register */ member
141 #define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))
143 #define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))
144 #define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
145 #define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
146 #define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
147 #define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
179 while((regs->cond_reg&bit) && (ctr>0)) {
195 regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \
197 regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \
[all …]
/dports/emulators/qemu5/qemu-5.2.0/roms/openbios/include/arch/sparc32/
H A Ddma.h28 __volatile__ __u32 cond_reg; /* DMA condition register */ member
141 #define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))
143 #define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))
144 #define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
145 #define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
146 #define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
147 #define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
179 while((regs->cond_reg&bit) && (ctr>0)) {
195 regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \
197 regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/openbios/include/arch/sparc32/
H A Ddma.h28 __volatile__ __u32 cond_reg; /* DMA condition register */ member
141 #define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))
143 #define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))
144 #define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
145 #define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
146 #define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
147 #define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
179 while((regs->cond_reg&bit) && (ctr>0)) {
195 regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \
197 regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/roms/openbios/include/arch/sparc32/
H A Ddma.h28 __volatile__ __u32 cond_reg; /* DMA condition register */ member
141 #define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))
143 #define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))
144 #define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
145 #define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
146 #define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
147 #define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
179 while((regs->cond_reg&bit) && (ctr>0)) {
195 regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \
197 regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/openbios/include/arch/sparc32/
H A Ddma.h28 __volatile__ __u32 cond_reg; /* DMA condition register */ member
141 #define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))
143 #define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))
144 #define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
145 #define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
146 #define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
147 #define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
179 while((regs->cond_reg&bit) && (ctr>0)) {
195 regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \
197 regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \
[all …]
/dports/emulators/qemu/qemu-6.2.0/roms/openbios/include/arch/sparc32/
H A Ddma.h28 __volatile__ __u32 cond_reg; /* DMA condition register */ member
141 #define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))
143 #define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))
144 #define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
145 #define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
146 #define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
147 #define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
179 while((regs->cond_reg&bit) && (ctr>0)) {
195 regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \
197 regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \
[all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/m68k/include/asm/
H A Ddvma.h90 __volatile__ unsigned long cond_reg; /* DMA condition register */ member
197 #define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))
199 #define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))
200 #define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
201 #define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
202 #define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
203 #define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
206 ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
229 regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \
231 regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \
[all …]
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/m68k/include/asm/
H A Ddvma.h90 __volatile__ unsigned long cond_reg; /* DMA condition register */ member
197 #define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))
199 #define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))
200 #define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
201 #define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
202 #define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
203 #define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
206 ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
229 regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \
231 regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \
[all …]
/dports/multimedia/libv4l/linux-5.13-rc2/arch/m68k/include/asm/
H A Ddvma.h90 __volatile__ unsigned long cond_reg; /* DMA condition register */ member
197 #define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))
199 #define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))
200 #define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
201 #define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
202 #define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
203 #define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
206 ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
229 regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \
231 regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \
[all …]
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/scsi/
H A Dzorro_esp.c101 unsigned char cond_reg; /* DMA cond (ro) [0x402] */ member
102 #define ctrl_reg cond_reg /* DMA control (wo) [0x402] */
114 unsigned char cond_reg; /* DMA cond (ro) [0x000] */ member
115 #define ctrl_reg cond_reg /* DMA control (wo) [0x000] */
129 unsigned char cond_reg; /* DMA status (ro) [0x0000] */ member
130 #define ctrl_reg cond_reg /* DMA control (wo) [0x0000] */
194 unsigned char dma_status = readb(&dregs->cond_reg); in cyber_esp_irq_pending()
206 dma_status = readb(&dregs->cond_reg); in fastlane_esp_irq_pending()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/scsi/
H A Dzorro_esp.c101 unsigned char cond_reg; /* DMA cond (ro) [0x402] */ member
102 #define ctrl_reg cond_reg /* DMA control (wo) [0x402] */
114 unsigned char cond_reg; /* DMA cond (ro) [0x000] */ member
115 #define ctrl_reg cond_reg /* DMA control (wo) [0x000] */
129 unsigned char cond_reg; /* DMA status (ro) [0x0000] */ member
130 #define ctrl_reg cond_reg /* DMA control (wo) [0x0000] */
194 unsigned char dma_status = readb(&dregs->cond_reg); in cyber_esp_irq_pending()
206 dma_status = readb(&dregs->cond_reg); in fastlane_esp_irq_pending()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/scsi/
H A Dzorro_esp.c101 unsigned char cond_reg; /* DMA cond (ro) [0x402] */ member
102 #define ctrl_reg cond_reg /* DMA control (wo) [0x402] */
114 unsigned char cond_reg; /* DMA cond (ro) [0x000] */ member
115 #define ctrl_reg cond_reg /* DMA control (wo) [0x000] */
129 unsigned char cond_reg; /* DMA status (ro) [0x0000] */ member
130 #define ctrl_reg cond_reg /* DMA control (wo) [0x0000] */
194 unsigned char dma_status = readb(&dregs->cond_reg); in cyber_esp_irq_pending()
206 dma_status = readb(&dregs->cond_reg); in fastlane_esp_irq_pending()
/dports/emulators/qemu42/qemu-4.2.1/roms/openbios/drivers/
H A Desp.c99 esp->espdma.regs->cond_reg = DMA_ENABLE; in do_command()
103 while ((esp->espdma.regs->cond_reg & DMA_HNDL_INTR) == 0) /* no-op */; in do_command()
130 esp->espdma.regs->cond_reg = DMA_ST_WRITE | DMA_ENABLE; in do_command()
134 while ((esp->espdma.regs->cond_reg & DMA_HNDL_INTR) == 0) /* no-op */; in do_command()
386 switch ((espdma->regs->cond_reg) & DMA_DEVICE_ID) { in espdma_init()
413 (espdma->regs->cond_reg) & DMA_DEVICE_ID); in espdma_init()
/dports/emulators/qemu5/qemu-5.2.0/roms/openbios/drivers/
H A Desp.c99 esp->espdma.regs->cond_reg = DMA_ENABLE; in do_command()
103 while ((esp->espdma.regs->cond_reg & DMA_HNDL_INTR) == 0) /* no-op */; in do_command()
130 esp->espdma.regs->cond_reg = DMA_ST_WRITE | DMA_ENABLE; in do_command()
134 while ((esp->espdma.regs->cond_reg & DMA_HNDL_INTR) == 0) /* no-op */; in do_command()
386 switch ((espdma->regs->cond_reg) & DMA_DEVICE_ID) { in espdma_init()
413 (espdma->regs->cond_reg) & DMA_DEVICE_ID); in espdma_init()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/openbios/drivers/
H A Desp.c99 esp->espdma.regs->cond_reg = DMA_ENABLE; in do_command()
103 while ((esp->espdma.regs->cond_reg & DMA_HNDL_INTR) == 0) /* no-op */; in do_command()
130 esp->espdma.regs->cond_reg = DMA_ST_WRITE | DMA_ENABLE; in do_command()
134 while ((esp->espdma.regs->cond_reg & DMA_HNDL_INTR) == 0) /* no-op */; in do_command()
386 switch ((espdma->regs->cond_reg) & DMA_DEVICE_ID) { in espdma_init()
413 (espdma->regs->cond_reg) & DMA_DEVICE_ID); in espdma_init()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/openbios/drivers/
H A Desp.c99 esp->espdma.regs->cond_reg = DMA_ENABLE; in do_command()
103 while ((esp->espdma.regs->cond_reg & DMA_HNDL_INTR) == 0) /* no-op */; in do_command()
130 esp->espdma.regs->cond_reg = DMA_ST_WRITE | DMA_ENABLE; in do_command()
134 while ((esp->espdma.regs->cond_reg & DMA_HNDL_INTR) == 0) /* no-op */; in do_command()
386 switch ((espdma->regs->cond_reg) & DMA_DEVICE_ID) { in espdma_init()
413 (espdma->regs->cond_reg) & DMA_DEVICE_ID); in espdma_init()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/openbios/drivers/
H A Desp.c99 esp->espdma.regs->cond_reg = DMA_ENABLE; in do_command()
103 while ((esp->espdma.regs->cond_reg & DMA_HNDL_INTR) == 0) /* no-op */; in do_command()
130 esp->espdma.regs->cond_reg = DMA_ST_WRITE | DMA_ENABLE; in do_command()
134 while ((esp->espdma.regs->cond_reg & DMA_HNDL_INTR) == 0) /* no-op */; in do_command()
386 switch ((espdma->regs->cond_reg) & DMA_DEVICE_ID) { in espdma_init()
413 (espdma->regs->cond_reg) & DMA_DEVICE_ID); in espdma_init()
/dports/emulators/qemu/qemu-6.2.0/roms/openbios/drivers/
H A Desp.c99 esp->espdma.regs->cond_reg = DMA_ENABLE; in do_command()
103 while ((esp->espdma.regs->cond_reg & DMA_HNDL_INTR) == 0) /* no-op */; in do_command()
130 esp->espdma.regs->cond_reg = DMA_ST_WRITE | DMA_ENABLE; in do_command()
134 while ((esp->espdma.regs->cond_reg & DMA_HNDL_INTR) == 0) /* no-op */; in do_command()
386 switch ((espdma->regs->cond_reg) & DMA_DEVICE_ID) { in espdma_init()
413 (espdma->regs->cond_reg) & DMA_DEVICE_ID); in espdma_init()
/dports/emulators/qemu60/qemu-6.0.0/roms/openbios/drivers/
H A Desp.c99 esp->espdma.regs->cond_reg = DMA_ENABLE; in do_command()
103 while ((esp->espdma.regs->cond_reg & DMA_HNDL_INTR) == 0) /* no-op */; in do_command()
130 esp->espdma.regs->cond_reg = DMA_ST_WRITE | DMA_ENABLE; in do_command()
134 while ((esp->espdma.regs->cond_reg & DMA_HNDL_INTR) == 0) /* no-op */; in do_command()
386 switch ((espdma->regs->cond_reg) & DMA_DEVICE_ID) { in espdma_init()
413 (espdma->regs->cond_reg) & DMA_DEVICE_ID); in espdma_init()
/dports/games/libretro-paralleln64/parallel-n64-6e26fbb/mupen64plus-rsp-paraLLEl/
H A Drsp_jit.cpp359 jit_stxi(-JIT_FRAME_SIZE + sizeof(jit_word_t), JIT_FP, cond_reg); in jit_save_illegal_cond_branch_taken()
1149 jit_lti(cond_reg, rs_reg, 0); in jit_instruction()
1172 jit_lti(cond_reg, rs_reg, 0); in jit_instruction()
1190 jit_gei(cond_reg, rs_reg, 0); in jit_instruction()
1212 jit_gei(cond_reg, rs_reg, 0); in jit_instruction()
1277 unsigned cond_reg = regs.modify_mips_register(_jit, RegisterCache::COND_BRANCH_TAKEN); in jit_instruction() local
1278 jit_eqr(cond_reg, rs_reg, rt_reg); in jit_instruction()
1296 unsigned cond_reg = regs.modify_mips_register(_jit, RegisterCache::COND_BRANCH_TAKEN); in jit_instruction() local
1297 jit_ner(cond_reg, rs_reg, rt_reg); in jit_instruction()
1318 jit_lei(cond_reg, rs_reg, 0); in jit_instruction()
[all …]
/dports/lang/gravity/gravity-0.8.5/src/compiler/
H A Dgravity_codegen.c468 uint32_t cond_reg, reg; in visit_flow_switch_stmt() local
474 cond_reg = ircode_register_last(code); in visit_flow_switch_stmt()
475 …if (cond_reg == REGISTER_ERROR) report_error(self, (gnode_t *)node, "Invalid switch condition expr… in visit_flow_switch_stmt()
491 ircode_add(code, NEQ, reg, cond_reg, reg, LINE_NUMBER(case_stmt)); in visit_flow_switch_stmt()
/dports/devel/valgrind/valgrind-dragonfly-dragonfly/none/tests/ppc32/
H A Dtest_isa_2_07_part2.c58 static volatile unsigned int cond_reg; variable
/dports/devel/valgrind/valgrind-dragonfly-dragonfly/none/tests/ppc64/
H A Dtest_isa_2_07_part2.c58 static volatile unsigned int cond_reg; variable
/dports/devel/valgrind-lts/valgrind-dragonfly-dragonfly/none/tests/ppc32/
H A Dtest_isa_2_07_part2.c58 static volatile unsigned int cond_reg; variable

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