1 /* 2 * Local copy of include/asm-sparc/dma.h 3 * 4 * Copyright 1995 (C) David S. Miller (davem@caip.rutgers.edu) 5 */ 6 7 #ifndef _ASM_SPARC_DMA_H 8 #define _ASM_SPARC_DMA_H 9 10 /* #include <linux/kernel.h> */ 11 /* #include <linux/types.h> */ 12 typedef unsigned int __u32; 13 14 /* These are irrelevant for Sparc DMA, but we leave it in so that 15 * things can compile. 16 */ 17 #define MAX_DMA_CHANNELS 8 18 #define MAX_DMA_ADDRESS (~0UL) 19 #define DMA_MODE_READ 1 20 #define DMA_MODE_WRITE 2 21 22 /* Useful constants */ 23 #define SIZE_16MB (16*1024*1024) 24 #define SIZE_64K (64*1024) 25 26 /* Structure to describe the current status of DMA registers on the Sparc */ 27 struct sparc_dma_registers { 28 __volatile__ __u32 cond_reg; /* DMA condition register */ 29 __volatile__ __u32 st_addr; /* Start address of this transfer */ 30 __volatile__ __u32 cnt; /* How many bytes to transfer */ 31 __volatile__ __u32 dma_test; /* DMA test register */ 32 }; 33 34 /* DVMA chip revisions */ 35 enum dvma_rev { 36 dvmarev0, 37 dvmaesc1, 38 dvmarev1, 39 dvmarev2, 40 dvmarev3, 41 dvmarevplus, 42 dvmahme 43 }; 44 45 #define DMA_HASCOUNT(rev) ((rev)==dvmaesc1) 46 47 #if 0 48 /* Linux DMA information structure, filled during probe. */ 49 struct Linux_SBus_DMA { 50 struct Linux_SBus_DMA *next; 51 struct linux_sbus_device *SBus_dev; 52 struct sparc_dma_registers *regs; 53 54 /* Status, misc info */ 55 int node; /* Prom node for this DMA device */ 56 int running; /* Are we doing DMA now? */ 57 int allocated; /* Are we "owned" by anyone yet? */ 58 59 /* Transfer information. */ 60 unsigned long addr; /* Start address of current transfer */ 61 int nbytes; /* Size of current transfer */ 62 int realbytes; /* For splitting up large transfers, etc. */ 63 64 /* DMA revision */ 65 enum dvma_rev revision; 66 }; 67 68 extern struct Linux_SBus_DMA *dma_chain; 69 #endif 70 71 /* Broken hardware... */ 72 /* Have to sort this out. Does rev0 work fine on sun4[cmd] without isbroken? 73 * Or is rev0 present only on sun4 boxes? -jj */ 74 #define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev0 || (dma)->revision == dvmarev1) 75 #define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1) 76 77 /* Fields in the cond_reg register */ 78 /* First, the version identification bits */ 79 #define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */ 80 #define DMA_VERS0 0x00000000 /* Sunray DMA version */ 81 #define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */ 82 #define DMA_VERS1 0x80000000 /* DMA rev 1 */ 83 #define DMA_VERS2 0xa0000000 /* DMA rev 2 */ 84 #define DMA_VERHME 0xb0000000 /* DMA hme gate array */ 85 #define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */ 86 87 #define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */ 88 #define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */ 89 #define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */ 90 #define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */ 91 #define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */ 92 #define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */ 93 #define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */ 94 #define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */ 95 #define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */ 96 #define DMA_ST_WRITE 0x00000100 /* write from device to memory */ 97 #define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */ 98 #define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */ 99 #define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */ 100 #define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */ 101 #define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */ 102 #define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */ 103 #define DMA_TERM_CNTR 0x00004000 /* Terminal counter */ 104 #define DMA_SCSI_SBUS64 0x00008000 /* HME: Enable 64-bit SBUS mode. */ 105 #define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */ 106 #define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */ 107 #define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */ 108 #define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */ 109 #define DMA_E_BURST8 0x00040000 /* ENET: SBUS r/w burst size */ 110 #define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */ 111 #define DMA_BRST64 0x00080000 /* SCSI: 64byte bursts (HME on UltraSparc only) */ 112 #define DMA_BRST32 0x00040000 /* SCSI: 32byte bursts */ 113 #define DMA_BRST16 0x00000000 /* SCSI: 16byte bursts */ 114 #define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */ 115 #define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */ 116 #define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */ 117 #define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */ 118 #define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */ 119 #define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */ 120 #define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */ 121 #define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */ 122 #define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */ 123 #define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */ 124 #define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */ 125 #define DMA_RESET_FAS366 0x08000000 /* HME: Assert RESET to FAS366 */ 126 127 /* Values describing the burst-size property from the PROM */ 128 #define DMA_BURST1 0x01 129 #define DMA_BURST2 0x02 130 #define DMA_BURST4 0x04 131 #define DMA_BURST8 0x08 132 #define DMA_BURST16 0x10 133 #define DMA_BURST32 0x20 134 #define DMA_BURST64 0x40 135 #define DMA_BURSTBITS 0x7f 136 137 /* Determine highest possible final transfer address given a base */ 138 #define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL)) 139 140 /* Yes, I hack a lot of elisp in my spare time... */ 141 #define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR)) 142 #define DMA_IRQ_P(regs) ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))) 143 #define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE)) 144 #define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE))) 145 #define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB))) 146 #define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB))) 147 #define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV)) 148 #define DMA_SETSTART(regs, addr) ((((regs)->st_addr) = (char *) addr)) 149 #define DMA_BEGINDMA_W(regs) \ 150 ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB)))) 151 #define DMA_BEGINDMA_R(regs) \ 152 ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE))))) 153 154 #if 0 155 156 /* For certain DMA chips, we need to disable ints upon irq entry 157 * and turn them back on when we are done. So in any ESP interrupt 158 * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT 159 * when leaving the handler. You have been warned... 160 */ 161 #define DMA_IRQ_ENTRY(dma, dregs) do { \ 162 if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \ 163 } while (0) 164 165 #define DMA_IRQ_EXIT(dma, dregs) do { \ 166 if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \ 167 } while(0) 168 169 170 /* Pause until counter runs out or BIT isn't set in the DMA condition 171 * register. 172 */ 173 extern __inline__ void sparc_dma_pause(struct sparc_dma_registers *regs, 174 unsigned long bit) 175 { 176 int ctr = 50000; /* Let's find some bugs ;) */ 177 178 /* Busy wait until the bit is not set any more */ 179 while((regs->cond_reg&bit) && (ctr>0)) { 180 ctr--; 181 __delay(5); 182 } 183 184 /* Check for bogus outcome. */ 185 if(!ctr) 186 panic("DMA timeout"); 187 } 188 189 /* Reset the friggin' thing... */ 190 #define DMA_RESET(dma) do { \ 191 struct sparc_dma_registers *regs = dma->regs; \ 192 /* Let the current FIFO drain itself */ \ 193 sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN)); \ 194 /* Reset the logic */ \ 195 regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \ 196 __delay(400); /* let the bits set ;) */ \ 197 regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \ 198 sparc_dma_enable_interrupts(regs); /* Re-enable interrupts */ \ 199 /* Enable FAST transfers if available */ \ 200 if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS; \ 201 dma->running = 0; \ 202 } while(0) 203 204 #define for_each_dvma(dma) \ 205 for((dma) = dma_chain; (dma); (dma) = (dma)->next) 206 207 extern int get_dma_list(char *); 208 extern int request_dma(unsigned int, __const__ char *); 209 extern void free_dma(unsigned int); 210 211 #endif 212 213 #endif /* !(_ASM_SPARC_DMA_H) */ 214