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Searched refs:create_generated_clock (Results 1 – 25 of 31) sorted by relevance

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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/
H A De320_dram.xdc7 create_generated_clock -name ddr3_ext_refclk -period 7.5 [get_ports sys_clk_p]
11 create_generated_clock -name ddr3_iodelay_refclk \
13 create_generated_clock -name ddr3_iodelay_refclk_fb \
18 create_generated_clock -name ddr3_ui_clk \
22 create_generated_clock -name ddr3_ui_clk_2x \
26 create_generated_clock -name ddr3_ps_clk \
H A De320_aurora.xdc7 create_generated_clock -name aurora_init_clk [get_pins -hierarchical -filter {NAME =~ "*aurora_clk_…
H A Dmb_timing.xdc28 create_generated_clock -name radio_clk_1x \
34 create_generated_clock -name radio_clk_2x \
69 create_generated_clock -name ddr3_dma_clk \
211 create_generated_clock \
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/rh/
H A Ddb_clocks.xdc66 create_generated_clock -name radio_clk_fb [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKFBOU…
67 create_generated_clock -name radio_clk [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKOUT0…
68 create_generated_clock -name radio_clk_2x [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKOUT1…
71 create_generated_clock -name radio_clk_b [get_pins {dbb_core/RadioClockingx/RadioClkMmcm/CLKOUT0…
72 create_generated_clock -name radio_clk_b_2x [get_pins {dbb_core/RadioClockingx/RadioClkMmcm/CLKOUT1…
92 create_generated_clock -name pl_spi_clk_a \
95 create_generated_clock -name pl_spi_rb_clk_a \
100 create_generated_clock -name pl_spi_clk_b \
103 create_generated_clock -name pl_spi_rb_clk_b \
111 create_generated_clock -name dba_jtag_tck -divide_by $DB_JTAG_DIVISOR \
[all …]
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/
H A Dn310_dram.xdc12 create_generated_clock -name ddr3_iodelay_refclk \
14 create_generated_clock -name ddr3_iodelay_refclk_fb \
19 create_generated_clock -name ddr3_ui_clk \
23 create_generated_clock -name ddr3_ui_clk_2x \
27 create_generated_clock -name ddr3_ps_clk \
H A Dmb_clocks.xdc64 create_generated_clock -name meas_clk_fb [get_pins {n3xx_clocking_i/misc_clock_gen_i/inst/mmcm_adv_…
65 create_generated_clock -name meas_clk [get_pins {n3xx_clocking_i/misc_clock_gen_i/inst/mmcm_adv_…
72 create_generated_clock -name wr_bus_clk \
83 create_generated_clock -name fp_gpio_bus_clk \
H A Dn310_aurora.xdc7 create_generated_clock -name aurora_init_clk [get_pins -hierarchical -filter {NAME =~ "*aurora_clk_…
H A Dn3xx_wr.xdc21 create_generated_clock -name wr_sysclk \
25 create_generated_clock -name wr_dmtdclk \
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/
H A Dx300_dram.xdc5 create_generated_clock -name ddr3_axi_clk [get_pins -hierarchical -filter {NAME =~ "*u_ddr3_infr…
6 create_generated_clock -name ddr3_axi_clk_x2 [get_pins -hierarchical -filter {NAME =~ "*u_ddr3_infr…
H A Dx300_aurora.xdc12 create_generated_clock -name aurora_init_clk [get_pins -hierarchical -filter {NAME =~ "*aurora_clk_…
H A Dtiming.xdc48 create_generated_clock -name DB0_DAC_DCI -source [get_pins gen_db0/oddr_clk/C] -divide_by 1 [get_p…
49 create_generated_clock -name DB1_DAC_DCI -source [get_pins gen_db1/oddr_clk/C] -divide_by 1 [get_p…
50 create_generated_clock -name IoTxClock -multiply_by 1 …
58 create_generated_clock -name radio_clk [get_pins -hierarchical -filter {NAME =~ "*ra…
59 create_generated_clock -name radio_clk_2x [get_pins -hierarchical -filter {NAME =~ "*ra…
61 create_generated_clock -name bus_clk [get_pins -hierarchical -filter {NAME =~ "*bu…
62 create_generated_clock -name bus_clk_div2 [get_pins -hierarchical -filter {NAME =~ "*bu…
63 create_generated_clock -name ce_clk [get_pins -hierarchical -filter {NAME =~ "*bu…
64 create_generated_clock -name ioport2_clk [get_pins -hierarchical -filter {NAME =~ "*bu…
65 create_generated_clock -name rio40_clk [get_pins -hierarchical -filter {NAME =~ "*pc…
[all …]
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/rh/cpld/
H A Drhodium_top.sdc45 create_generated_clock -source [get_ports CPLD_PS_SPI_CLK_25] \
47 create_generated_clock -source [get_ports CPLD_PS_SPI_CLK_25] \
49 create_generated_clock -source [get_ports CPLD_PS_SPI_CLK_25] \
51 create_generated_clock -source [get_ports CPLD_PS_SPI_CLK_25] \
54 create_generated_clock -source [get_ports CPLD_PL_SPI_SCLK_18] \
57 create_generated_clock -source [get_ports CPLD_PL_SPI_SCLK_18] \
60 create_generated_clock -source [get_ports CPLD_PL_SPI_SCLK_18] \
65 #create_generated_clock -source [get_pins lo_gain_table\|dsa1_le\|clk]
66 create_generated_clock -source [get_ports CPLD_PL_SPI_SCLK_18] \
70 create_generated_clock -source [get_pins lo_gain_table\|dsa1_le\|q] \
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/mg/
H A Ddb_timing.xdc53 create_generated_clock -name radio_clk_fb [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKFBOU…
54 create_generated_clock -name radio_clk [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKOUT0…
55 create_generated_clock -name radio_clk_2x [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKOUT1…
57 create_generated_clock -name radio_clk_b_fb [get_pins {dbb_core/RadioClockingx/RadioClkMmcm/CLKFBOU…
58 create_generated_clock -name radio_clk_b [get_pins {dbb_core/RadioClockingx/RadioClkMmcm/CLKOUT0…
59 create_generated_clock -name radio_clk_b_2x [get_pins {dbb_core/RadioClockingx/RadioClkMmcm/CLKOUT1…
74 create_generated_clock -name pl_spi_clk_a \
78 create_generated_clock -name pl_spi_clk_b \
86 create_generated_clock -name dsa_bus_clk \
91 create_generated_clock -name atr_bus_clk \
[all …]
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon.constraints/
H A Dchipscope_icon.xdc3 create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BS…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b2xxmini/coregen/
H A Dchipscope_icon.xdc3 create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BS…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.constraints/
H A Db200_chipscope_icon.xdc3 create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BS…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen/
H A Dchipscope_icon.xdc3 create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BS…
H A Db200_chipscope_icon.xdc3 create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BS…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen/chipscope_icon.constraints/
H A Dchipscope_icon.xdc3 create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BS…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/
H A Dten_gige_phy.xdc51 create_generated_clock -name ddrclock -divide_by 1 -invert -source [get_pins *rx_clk_ddr/C] [get_po…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/
H A Dten_gige_phy.xdc51 create_generated_clock -name ddrclock -divide_by 1 -invert -source [get_pins *rx_clk_ddr/C] [get_po…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e31x/
H A De31x_timing.xdc50 create_generated_clock -name CAT_FB_CLK -multiply_by 1 -source [get_pins e310_io/oddr_clk/C] [get_p…
/dports/cad/opentimer/OpenTimer-18d28ff/ot/sdc/
H A Dsdc1.3.tcl42 declare create_generated_clock {
H A Dsdc1.4.tcl43 declare create_generated_clock {
H A Dsdc1.6.tcl37 declare create_generated_clock {

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