1# 2# Copyright 2018 Ettus Research, A National Instruments Company 3# SPDX-License-Identifier: LGPL-3.0 4# 5# Description: Timing constraints for the USRP E320 6# 7 8 9############################################################################### 10# Input Clocks 11############################################################################### 12 13# External Reference Clock 14set REF_CLK_PERIOD 50.00 15create_clock -name ref_clk -period $REF_CLK_PERIOD [get_ports CLK_REF_RAW] 16 17# Radio clock from AD9361 18set rx_clk_period 8.138 19create_clock -name rx_clk -period $rx_clk_period [get_ports RX_CLK_P] 20 21# 1 Gigabit Ethernet Reference Clock 22create_clock -name ge_clk -period 8.000 [get_ports CLK_MGT_125M_P] 23 24# 10 Gigabit and Aurora Reference Clock 25create_clock -name xge_clk -period 6.400 [get_ports CLK_MGT_156_25M_P] 26 27# Derived radio clocks (two mutually-exclusive clocks using a BUFGMUX) 28create_generated_clock -name radio_clk_1x \ 29 -divide_by 4 \ 30 -add \ 31 -master_clock rx_clk \ 32 -source [get_pins cat_io_lvds_dual_mode_i0/cat_io_lvds_i0/cat_input_lvds_i0/sdr_clk_2x_bufr/O] \ 33 [get_pins cat_io_lvds_dual_mode_i0/BUFGCTRL_radio_clk/O] 34create_generated_clock -name radio_clk_2x \ 35 -divide_by 2 \ 36 -add \ 37 -master_clock rx_clk \ 38 -source [get_pins cat_io_lvds_dual_mode_i0/cat_io_lvds_i0/cat_input_lvds_i0/sdr_clk_bufr/O] \ 39 [get_pins cat_io_lvds_dual_mode_i0/BUFGCTRL_radio_clk/O] 40set_clock_groups -physically_exclusive -group radio_clk_1x -group radio_clk_2x 41 42 43 44############################################################################### 45# Rename Clocks 46############################################################################### 47 48create_clock -name clk100 \ 49 -period [get_property PERIOD [get_clocks clk_fpga_0]] \ 50 [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_0]]] 51set_input_jitter clk100 0.3 52 53create_clock -name clk40 \ 54 -period [get_property PERIOD [get_clocks clk_fpga_1]] \ 55 [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_1]]] 56set_input_jitter clk40 0.75 57 58create_clock -name meas_clk_ref \ 59 -period [get_property PERIOD [get_clocks clk_fpga_2]] \ 60 [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_2]]] 61set_input_jitter meas_clk_ref 0.18 62 63create_clock -name bus_clk \ 64 -period [get_property PERIOD [get_clocks clk_fpga_3]] \ 65 [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_3]]] 66set_input_jitter bus_clk 0.15 67 68# DMA Clock 69create_generated_clock -name ddr3_dma_clk \ 70 [get_pins {e320_clocking_i/mmcm_adv_inst/CLKOUT0}] 71 72 73 74############################################################################### 75# Clock Crossings 76############################################################################### 77 78set DDR3_UI_CLK_PERIOD [get_property period [get_clocks ddr3_ui_clk]] 79set RADIO_CLK_1X_PERIOD [get_property period [get_clocks radio_clk_1x]] 80set RADIO_CLK_2X_PERIOD [get_property period [get_clocks radio_clk_2x]] 81set XGE_CLK_PERIOD [get_property period [get_clocks xge_clk]] 82 83# XADC temperature 84set_max_delay -from [get_pins tempmon_i/device_temp_r_reg[*]/C] -to [get_clocks ddr3_ui_clk] $DDR3_UI_CLK_PERIOD -datapath_only 85 86# GPIO muxing 87set_max_delay -from [get_pins e320_core_i/fp_gpio_src_reg_reg[*]/C] -to [get_clocks radio_clk_1x] $RADIO_CLK_1X_PERIOD -datapath_only 88set_max_delay -from [get_pins e320_core_i/fp_gpio_src_reg_reg[*]/C] -to [get_clocks radio_clk_2x] $RADIO_CLK_2X_PERIOD -datapath_only 89 90# Codec reset 91set_max_delay -from [get_pins e320_core_i/dboard_ctrl_reg[2]/C] -to [get_clocks radio_clk_1x_1] $RADIO_CLK_1X_PERIOD -datapath_only 92 93# Power-on reset 94set_max_delay -from [get_pins por_gen/por_rst_reg/C] -to [get_clocks xge_clk] $XGE_CLK_PERIOD -datapath_only 95 96# SFP MDIO data and clock signal crossings. These are double synchronized in 97# the Xilinx MDIO IP. 98set_max_delay -from [get_pins sfp_wrapper_i/mgt_io_i/mdio_master_i/mdio_out_reg/C] \ 99 -to [get_clocks xge_clk] $XGE_CLK_PERIOD -datapath_only 100set_max_delay -from [get_pins sfp_wrapper_i/mgt_io_i/mdio_master_i/mdc_reg/C] \ 101 -to [get_clocks xge_clk] $XGE_CLK_PERIOD -datapath_only 102 103 104 105############################################################################### 106# False Paths 107############################################################################### 108 109# Synchronizer core false paths 110set_false_path -to [get_pins -hierarchical -filter {NAME =~ */synchronizer_false_path/stages[0].value_reg[0][*]/D}] 111set_false_path -to [get_pins -hierarchical -filter {NAME =~ */synchronizer_false_path/stages[0].value_reg[0][*]/S}] 112 113 114# MIG core reset 115# According to Xilinx AR 61112, it is safe to make sys_rst a false path. 116set_false_path -from [get_pins bus_reset_gen/reset_out_reg/C] \ 117 -to [get_clocks ddr3_ui_clk] 118set_false_path -from [get_pins bus_reset_gen/reset_out_reg/C] \ 119 -to [get_clocks ddr3_ui_clk_2x] 120 121# USR_ACCESS build date 122set_false_path -through [get_pins usr_access_i/DATA[*]] 123 124 125 126############################################################################### 127# PPS Input Timing 128############################################################################### 129 130# The external PPS is synchronous to the external reference clock. We want to 131# allow for 5 ns of setup and 5 ns of hold at the external connectors of the 132# device. 133set t_ext_setup 5.0 134set t_ext_hold 5.0 135 136# Board delays for external REF/PPS 137set t_ext_pps_to_fpga(min) 1.673 ; # Delay from external pin of PPS to FPGA 138set t_ext_pps_to_fpga(max) 5.011 139set t_ext_ref_to_fpga(min) 1.452 ; # Delay from external pin of reference clock to FPGA 140set t_ext_ref_to_fpga(max) 4.000 141 142# Calculate the needed setup and hold at FPGA for external PPS, taking into 143# account worst-case clock and data path skew. 144set t_ext_fpga_setup [expr $t_ext_setup + ($t_ext_ref_to_fpga(min) - $t_ext_pps_to_fpga(max))] 145set t_ext_fpga_hold [expr $t_ext_hold + ($t_ext_pps_to_fpga(min) - $t_ext_ref_to_fpga(max))] 146 147set_input_delay -clock ref_clk -max [expr $REF_CLK_PERIOD - $t_ext_fpga_setup] [get_ports CLK_SYNC_EXT] 148set_input_delay -clock ref_clk -min $t_ext_fpga_hold [get_ports CLK_SYNC_EXT] 149 150 151# The GPS provides 2 ns setup and 2 ns of hold around the rising clock edge 152set t_int_setup 2.0 153set t_int_hold 2.0 154 155# Board delays for internal REF/PPS 156set t_int_pps_to_fpga(min) 0.359 ; # Delay from PPS output of GPS to FPGA 157set t_int_pps_to_fpga(max) 0.438 158set t_int_ref_to_fpga(min) 1.699 ; # Delay from reference clock output of GPS to FPGA 159set t_int_ref_to_fpga(max) 3.149 160 161# Calculate the needed setup and hold at FPGA for internal PPS, taking into 162# account worst-case clock and data path skew. 163set t_int_fpga_setup [expr $t_int_setup + ($t_int_ref_to_fpga(min) - $t_int_pps_to_fpga(max))] 164set t_int_fpga_hold [expr $t_int_hold + ($t_int_pps_to_fpga(min) - $t_int_ref_to_fpga(max))] 165 166set_input_delay -clock ref_clk -max [expr $REF_CLK_PERIOD - $t_int_fpga_setup] [get_ports CLK_SYNC_INT] 167set_input_delay -clock ref_clk -min $t_int_fpga_hold [get_ports CLK_SYNC_INT] 168 169 170 171############################################################################### 172# LVDS Interface 173############################################################################### 174 175# LVDS interface is source synchronous DDR. tPCB numbers are taken from 176# HyperLynx for the Rev B PCB. 10 ps was added to each PCB delay for additional 177# margin. 178 179# From the AD9361 data sheet 180set tDDRX(min) 0.25 181set tDDRX(max) 1.25 182set tSTX(min) 1.0 183set tHTX(min) 0.0 184 185# Other timing parameters 186set tCP2X(min) [expr 0.45 * $rx_clk_period] ; # Worst-case bit period 187set tTrns(max) 0.220 ; # Amount of time it takes an input to transition 188 189# Input timing parameters 190set tPCB_RX(max) 0.058 ; # Max delay by which the clock trace is longer than the data trace 191set tPCB_RX(min) -0.059 ; # Min delay by which the clock trace is longer than the data trace 192set tSetupIn [expr $tCP2X(min) - $tDDRX(max) + $tPCB_RX(min)] 193set tHoldIn [expr $tDDRX(min) - $tTrns(max) - $tPCB_RX(max)] 194 195# Input Setup/Hold (Rising Clock Edge) 196set_input_delay -clock [get_clocks rx_clk] -max [expr $tCP2X(min) - $tSetupIn] [get_ports {RX_DATA_*[*] RX_FRAME_*}] 197set_input_delay -clock [get_clocks rx_clk] -min $tHoldIn [get_ports {RX_DATA_*[*] RX_FRAME_*}] 198 199# Input Setup/Hold (Falling Clock Edge) 200set_input_delay -clock [get_clocks rx_clk] -max [expr $tCP2X(min) - $tSetupIn] [get_ports {RX_DATA_*[*] RX_FRAME_*}] -clock_fall -add_delay 201set_input_delay -clock [get_clocks rx_clk] -min $tHoldIn [get_ports {RX_DATA_*[*] RX_FRAME_*}] -clock_fall -add_delay 202 203 204# Output timing parameters 205set tPCB_TX(max) 0.066 ; # Max delay by which the clock trace is longer than the data trace 206set tPCB_TX(min) -0.049 ; # Min delay by which the clock trace is longer than the data trace 207set tSetupOut [expr $tSTX(min) - $tPCB_TX(min)] 208set tHoldOut [expr $tHTX(min) + $tPCB_TX(max)] 209 210# Create tx_clk (FB_CLK) 211create_generated_clock \ 212 -name tx_clk \ 213 -multiply_by 1 \ 214 -source [get_pins cat_io_lvds_dual_mode_i0/cat_io_lvds_i0/cat_output_lvds_i0/ddr_clk_oserdese2/CLK] \ 215 [get_ports TX_CLK_P] 216 217# Output Setup 218set_output_delay -clock [get_clocks tx_clk] -max $tSetupOut [get_ports {TX_DATA_*[*] TX_FRAME_*}] 219set_output_delay -clock [get_clocks tx_clk] -max $tSetupOut [get_ports {TX_DATA_*[*] TX_FRAME_*}] -clock_fall -add_delay 220 221# Output Hold 222set_output_delay -clock [get_clocks tx_clk] -min [expr -$tHoldOut] [get_ports {TX_DATA_*[*] TX_FRAME_*}] 223set_output_delay -clock [get_clocks tx_clk] -min [expr -$tHoldOut] [get_ports {TX_DATA_*[*] TX_FRAME_*}] -clock_fall -add_delay 224 225 226 227############################################################################### 228# SPI 229############################################################################### 230 231# Xilinx doesn't allow you to fully constrain EMIO because the internal SPI 232# clock is not accessible. So delay constraints are used to limit the delays to 233# compatible values. 234 235# Transceiver SPI 236set_max_delay -from [get_pins e320_ps_bd_i/processing_system7_0/inst/PS7_i/EMIOSPI0MO] \ 237 -to [get_ports XCVR_SPI_MOSI] 6.0 -datapath_only 238set_min_delay -to [get_ports XCVR_SPI_MOSI] 0.0 239# 240set_max_delay -from [get_pins e320_ps_bd_i/processing_system7_0/inst/PS7_i/EMIOSPI0SCLKO] \ 241 -to [get_ports XCVR_SPI_CLK] 6.0 -datapath_only 242set_min_delay -to [get_ports XCVR_SPI_CLK] 0.0 243# 244set_max_delay -from [get_pins e320_ps_bd_i/processing_system7_0/inst/PS7_i/EMIOSPI0SSON[0]] \ 245 -to [get_ports XCVR_SPI_CS_N] 6.0 -datapath_only 246set_min_delay -to [get_ports XCVR_SPI_CS_N] 0.0 247# 248set_max_delay -from [get_ports XCVR_SPI_MISO] \ 249 -to [get_pins e320_ps_bd_i/processing_system7_0/inst/PS7_i/EMIOSPI0MI] 4.0 -datapath_only 250set_min_delay -from [get_ports XCVR_SPI_MISO] -to [get_pins e320_ps_bd_i/processing_system7_0/inst/PS7_i/EMIOSPI0MI] 0.0 251 252# Clock synthesizer SPI 253set_max_delay -from [get_pins e320_ps_bd_i/processing_system7_0/inst/PS7_i/EMIOSPI1MO] \ 254 -to [get_ports CLK_PLL_SDATA] 9.0 -datapath_only 255set_min_delay -to [get_ports XCVR_SPI_MOSI] 0.0 256# 257set_max_delay -from [get_pins e320_ps_bd_i/processing_system7_0/inst/PS7_i/EMIOSPI1SCLKO] \ 258 -to [get_ports CLK_PLL_SCLK] 9.0 -datapath_only 259set_min_delay -to [get_ports XCVR_SPI_CLK] 0.0 260# 261set_max_delay -from [get_pins e320_ps_bd_i/processing_system7_0/inst/PS7_i/EMIOSPI1SSON[0]] \ 262 -to [get_ports CLK_PLL_SLE] 9.0 -datapath_only 263set_min_delay -to [get_ports XCVR_SPI_CS_N] 0.0 264 265 266 267############################################################################### 268# Miscellaneous I/O Constraints 269############################################################################### 270 271# Transceiver 272set_max_delay -to [get_ports XCVR_RESET_N] 50.0 273set_min_delay -to [get_ports XCVR_RESET_N] 0.0 274# 275set_max_delay -from [get_ports XCVR_CTRL_OUT[*]] 5.0 -datapath_only 276set_min_delay -from [get_ports XCVR_CTRL_OUT[*]] 0.0 277 278# GPIO 279set_max_delay -from [get_ports GPIO_PREBUFF[*]] 5.0 -datapath_only 280set_min_delay -from [get_ports GPIO_PREBUFF[*]] 0.0 281# 282set_max_delay -from [all_fanin -only_cells -startpoints_only -flat [get_ports GPIO_DIR[*]]] \ 283 -to [get_ports GPIO_DIR[*]] 8.0 -datapath_only 284set_min_delay -to [get_ports GPIO_DIR[*]] 0.0 285# 286set_max_delay -from [all_fanin -only_cells -startpoints_only -flat [get_ports GPIO_PREBUFF[*]]] \ 287 -to [get_ports GPIO_PREBUFF[*]] 8.0 -datapath_only 288set_min_delay -to [get_ports GPIO_PREBUFF[*]] 0.0 289# 290set_max_delay -from [all_fanin -only_cells -startpoints_only -flat [get_ports GPIO_OE_N]] \ 291 -to [get_ports GPIO_OE_N] 8.0 -datapath_only 292set_min_delay -to [get_ports GPIO_OE_N] 0.0 293# 294set_max_delay -to [get_ports {EN_GPIO_2V5 EN_GPIO_3V3 EN_GPIO_VAR_SUPPLY}] 50.0 295set_min_delay -to [get_ports {EN_GPIO_2V5 EN_GPIO_3V3 EN_GPIO_VAR_SUPPLY}] 0.0 296 297# GPS 298set_max_delay -from [get_ports {GPS_ALARM GPS_LOCK GPS_PHASELOCK GPS_SURVEY GPS_WARMUP}] 10.0 -datapath_only 299set_min_delay -from [get_ports {GPS_ALARM GPS_LOCK GPS_PHASELOCK GPS_SURVEY GPS_WARMUP}] 0.0 300# 301set_max_delay -to [get_ports GPS_INITSURV_N] 50.0 302set_min_delay -to [get_ports GPS_INITSURV_N] 0.0 303set_max_delay -to [get_ports GPS_RST_N] 50.0 304set_min_delay -to [get_ports GPS_RST_N] 0.0 305# 306set_max_delay -to [get_ports CLK_GPS_PWR_EN] 50.0 307set_min_delay -to [get_ports CLK_GPS_PWR_EN] 0.0 308 309# Clock Control 310set_max_delay -from [all_fanin -only_cells -startpoints_only -flat [get_ports CLK_REF_SEL]] \ 311 -to [get_ports CLK_REF_SEL] 8.0 -datapath_only 312set_min_delay -to [get_ports CLK_REF_SEL] 0.0 313# 314set_max_delay -from [get_ports CLK_MUX_OUT] 5.0 -datapath_only 315set_min_delay -from [get_ports CLK_MUX_OUT] 0.0 316 317# DDR3 318set_max_delay -to [get_ports ddr3_reset_n] 50.0 319set_min_delay -to [get_ports ddr3_reset_n] 0.0 320 321# LEDs 322set_max_delay -to [get_ports RX1_GRN_ENA] 50.0 323set_min_delay -to [get_ports RX1_GRN_ENA] 0.0 324set_max_delay -to [get_ports TX1_RED_ENA] 50.0 325set_min_delay -to [get_ports TX1_RED_ENA] 0.0 326set_max_delay -to [get_ports TXRX1_GRN_ENA] 50.0 327set_min_delay -to [get_ports TXRX1_GRN_ENA] 0.0 328set_max_delay -to [get_ports RX2_GRN_ENA] 50.0 329set_min_delay -to [get_ports RX2_GRN_ENA] 0.0 330set_max_delay -to [get_ports TX2_RED_ENA] 50.0 331set_min_delay -to [get_ports TX2_RED_ENA] 0.0 332set_max_delay -to [get_ports TXRX2_GRN_ENA] 50.0 333set_min_delay -to [get_ports TXRX2_GRN_ENA] 0.0 334# 335set_max_delay -to [get_ports LED_ACT1] 50.0 336set_min_delay -to [get_ports LED_ACT1] 0.0 337set_max_delay -to [get_ports LED_LINK1] 50.0 338set_min_delay -to [get_ports LED_LINK1] 0.0 339 340# Control Filters 341set_max_delay -from [all_fanin -only_cells -startpoints_only -flat [get_ports FE*_SEL[*]]] \ 342 -to [get_ports FE*_SEL[*]] 10.0 -datapath_only 343set_max_delay -from [all_fanin -only_cells -startpoints_only -flat [get_ports RX*_SEL[*]]] \ 344 -to [get_ports RX*_SEL[*]] 10.0 -datapath_only 345set_max_delay -from [all_fanin -only_cells -startpoints_only -flat [get_ports RX*_BSEL[*]]] \ 346 -to [get_ports RX*_BSEL[*]] 10.0 -datapath_only 347set_max_delay -from [all_fanin -only_cells -startpoints_only -flat [get_ports TX*_BSEL[*]]] \ 348 -to [get_ports TX*_BSEL[*]] 10.0 -datapath_only 349 350# PA Control 351set_max_delay -from [all_fanin -only_cells -startpoints_only -flat [get_ports TX_HFAMP*_ENA]] \ 352 -to [get_ports TX_HFAMP*_ENA] 10.0 -datapath_only 353set_max_delay -from [all_fanin -only_cells -startpoints_only -flat [get_ports TX_LFAMP*_ENA]] \ 354 -to [get_ports TX_LFAMP*_ENA] 10.0 -datapath_only 355 356# SFP 357set_max_delay -from [get_ports SFP1_RXLOS] 50.0 358set_min_delay -from [get_ports SFP1_RXLOS] 0.0 359set_max_delay -to [get_ports SFP1_TXDISABLE] 50.0 360set_min_delay -to [get_ports SFP1_TXDISABLE] 0.0 361