| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/i915/display/ |
| H A D | intel_color.c | 1337 crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state); in i9xx_color_check()
1391 crtc_state->cgm_mode = chv_cgm_mode(crtc_state); in chv_color_check()
1397 crtc_state->preload_luts = chv_can_preload_luts(crtc_state); in chv_color_check()
1445 crtc_state->gamma_mode = ilk_gamma_mode(crtc_state); in ilk_color_check()
1447 crtc_state->csc_mode = ilk_csc_mode(crtc_state); in ilk_color_check()
1512 crtc_state->gamma_mode = ivb_gamma_mode(crtc_state); in ivb_color_check()
1514 crtc_state->csc_mode = ivb_csc_mode(crtc_state); in ivb_color_check()
1558 crtc_state->hw.ctm || crtc_state->limited_color_range; in glk_color_check()
1560 crtc_state->gamma_mode = glk_gamma_mode(crtc_state); in glk_color_check()
1615 crtc_state->gamma_mode = icl_gamma_mode(crtc_state); in icl_color_check()
[all …]
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| H A D | intel_vrr.c | 76 return crtc_state->vrr.vmin + 1 - intel_vrr_vblank_exit_length(crtc_state); in intel_vrr_vmin_vblank_start()
81 return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state); in intel_vrr_vmax_vblank_start()
100 if (!crtc_state->uapi.vrr_enabled) in intel_vrr_compute_config()
119 crtc_state->vrr.vmin = vmin - 1; in intel_vrr_compute_config()
120 crtc_state->vrr.vmax = vmax; in intel_vrr_compute_config()
121 crtc_state->vrr.enable = true; in intel_vrr_compute_config()
123 crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1; in intel_vrr_compute_config()
135 crtc_state->vrr.pipeline_full = in intel_vrr_compute_config()
148 if (!crtc_state->vrr.enable) in intel_vrr_enable()
169 if (!crtc_state->vrr.enable) in intel_vrr_send_push()
[all …]
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| H A D | intel_vdsc.c | 498 if (crtc_state->bigjoiner) in intel_dsc_pps_configure()
515 if (!is_pipe_dsc(crtc_state)) { in intel_dsc_pps_configure()
522 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
529 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
539 if (!is_pipe_dsc(crtc_state)) { in intel_dsc_pps_configure()
546 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
553 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
564 if (!is_pipe_dsc(crtc_state)) { in intel_dsc_pps_configure()
1048 if (crtc_state->bigjoiner) { in intel_dsc_enable()
1099 crtc_state->bigjoiner = true; in intel_dsc_get_config()
[all …]
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| H A D | intel_atomic.c | 230 crtc_state = kmemdup(old_crtc_state, sizeof(*crtc_state), GFP_KERNEL); in intel_crtc_duplicate_state()
231 if (!crtc_state) in intel_crtc_duplicate_state()
239 if (crtc_state->hw.ctm) in intel_crtc_duplicate_state()
241 if (crtc_state->hw.gamma_lut) in intel_crtc_duplicate_state()
251 crtc_state->inherited = false; in intel_crtc_duplicate_state()
253 crtc_state->fb_bits = 0; in intel_crtc_duplicate_state()
255 crtc_state->dsb = NULL; in intel_crtc_duplicate_state()
257 return &crtc_state->uapi; in intel_crtc_duplicate_state()
301 kfree(crtc_state); in intel_crtc_destroy_state()
399 &crtc_state->scaler_state; in intel_atomic_setup_scalers()
[all …]
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| H A D | intel_ddi.c | 511 crtc_state)); in intel_ddi_enable_transcoder_func()
3025 crtc_state); in trans_port_sync_stop_link_train()
3180 crtc_state, in intel_enable_ddi()
3279 int required_lanes = crtc_state ? crtc_state->lane_count : 1; in intel_ddi_update_prepare()
3285 if (crtc_state && crtc_state->hw.active) in intel_ddi_update_prepare()
3728 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, in intel_ddi_get_clock()
3788 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, in icl_ddi_tc_get_clock()
3966 crtc_state)) in intel_ddi_port_sync_transcoders()
3984 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); in intel_ddi_compute_config_late()
3999 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { in intel_ddi_compute_config_late()
[all …]
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| H A D | intel_ddi_buf_trans.c | 1082 if (crtc_state->port_clock > 540000) { in icl_get_combo_buf_trans_edp()
1101 const struct intel_crtc_state *crtc_state, in icl_get_combo_buf_trans() argument
1123 const struct intel_crtc_state *crtc_state, in icl_get_mg_buf_trans_dp() argument
1126 if (crtc_state->port_clock > 270000) { in icl_get_mg_buf_trans_dp()
1181 const struct intel_crtc_state *crtc_state, in ehl_get_combo_buf_trans() argument
1218 if (crtc_state->port_clock > 270000) { in jsl_get_combo_buf_trans_edp()
1232 const struct intel_crtc_state *crtc_state, in jsl_get_combo_buf_trans() argument
1259 if (crtc_state->port_clock > 270000) { in tgl_get_combo_buf_trans_dp()
1289 if (crtc_state->port_clock > 540000) { in tgl_get_combo_buf_trans_edp()
1305 const struct intel_crtc_state *crtc_state, in tgl_get_combo_buf_trans() argument
[all …]
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| H A D | intel_dp_link_training.c | 351 const struct intel_crtc_state *crtc_state, in intel_dp_set_link_train() argument
365 len = crtc_state->lane_count + 1; in intel_dp_set_link_train()
404 const struct intel_crtc_state *crtc_state, in intel_dp_set_signal_levels() argument
450 return ret == crtc_state->lane_count; in intel_dp_update_link_train()
493 link_config[1] = crtc_state->lane_count; in intel_dp_prepare_link_train()
716 crtc_state->lane_count)) { in intel_dp_link_training_channel_equalization()
725 crtc_state->lane_count)) { in intel_dp_link_training_channel_equalization()
789 const struct intel_crtc_state *crtc_state, in intel_dp_link_train_phy() argument
810 crtc_state->port_clock, crtc_state->lane_count, in intel_dp_link_train_phy()
826 crtc_state->port_clock, in intel_dp_schedule_fallback_link_training()
[all …]
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| H A D | intel_dpll.c | 1091 if (!crtc_state->clock_set && in ilk_crtc_compute_clock()
1092 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in ilk_crtc_compute_clock()
1154 if (!crtc_state->clock_set && in chv_crtc_compute_clock()
1155 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in chv_crtc_compute_clock()
1176 if (!crtc_state->clock_set && in vlv_crtc_compute_clock()
1177 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in vlv_crtc_compute_clock()
1220 if (!crtc_state->clock_set && in g4x_crtc_compute_clock()
1221 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in g4x_crtc_compute_clock()
1258 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in pnv_crtc_compute_clock()
1295 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in i9xx_crtc_compute_clock()
[all …]
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| H A D | intel_ddi.h | 24 const struct intel_crtc_state *crtc_state);
26 const struct intel_crtc_state *crtc_state);
32 const struct intel_crtc_state *crtc_state);
34 struct intel_crtc_state *crtc_state,
37 const struct intel_crtc_state *crtc_state);
41 struct intel_crtc_state *crtc_state);
44 const struct intel_crtc_state *crtc_state);
53 const struct intel_crtc_state *crtc_state);
61 struct intel_crtc_state *crtc_state);
63 const struct intel_crtc_state *crtc_state);
[all …]
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| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/i915/display/ |
| H A D | intel_color.c | 1337 crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state); in i9xx_color_check()
1391 crtc_state->cgm_mode = chv_cgm_mode(crtc_state); in chv_color_check()
1397 crtc_state->preload_luts = chv_can_preload_luts(crtc_state); in chv_color_check()
1445 crtc_state->gamma_mode = ilk_gamma_mode(crtc_state); in ilk_color_check()
1447 crtc_state->csc_mode = ilk_csc_mode(crtc_state); in ilk_color_check()
1512 crtc_state->gamma_mode = ivb_gamma_mode(crtc_state); in ivb_color_check()
1514 crtc_state->csc_mode = ivb_csc_mode(crtc_state); in ivb_color_check()
1558 crtc_state->hw.ctm || crtc_state->limited_color_range; in glk_color_check()
1560 crtc_state->gamma_mode = glk_gamma_mode(crtc_state); in glk_color_check()
1615 crtc_state->gamma_mode = icl_gamma_mode(crtc_state); in icl_color_check()
[all …]
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| H A D | intel_vrr.c | 76 return crtc_state->vrr.vmin + 1 - intel_vrr_vblank_exit_length(crtc_state); in intel_vrr_vmin_vblank_start()
81 return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state); in intel_vrr_vmax_vblank_start()
100 if (!crtc_state->uapi.vrr_enabled) in intel_vrr_compute_config()
119 crtc_state->vrr.vmin = vmin - 1; in intel_vrr_compute_config()
120 crtc_state->vrr.vmax = vmax; in intel_vrr_compute_config()
121 crtc_state->vrr.enable = true; in intel_vrr_compute_config()
123 crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1; in intel_vrr_compute_config()
135 crtc_state->vrr.pipeline_full = in intel_vrr_compute_config()
148 if (!crtc_state->vrr.enable) in intel_vrr_enable()
169 if (!crtc_state->vrr.enable) in intel_vrr_send_push()
[all …]
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| H A D | intel_vdsc.c | 498 if (crtc_state->bigjoiner) in intel_dsc_pps_configure()
515 if (!is_pipe_dsc(crtc_state)) { in intel_dsc_pps_configure()
522 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
529 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
539 if (!is_pipe_dsc(crtc_state)) { in intel_dsc_pps_configure()
546 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
553 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
564 if (!is_pipe_dsc(crtc_state)) { in intel_dsc_pps_configure()
1048 if (crtc_state->bigjoiner) { in intel_dsc_enable()
1099 crtc_state->bigjoiner = true; in intel_dsc_get_config()
[all …]
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| H A D | intel_atomic.c | 230 crtc_state = kmemdup(old_crtc_state, sizeof(*crtc_state), GFP_KERNEL); in intel_crtc_duplicate_state()
231 if (!crtc_state) in intel_crtc_duplicate_state()
239 if (crtc_state->hw.ctm) in intel_crtc_duplicate_state()
241 if (crtc_state->hw.gamma_lut) in intel_crtc_duplicate_state()
251 crtc_state->inherited = false; in intel_crtc_duplicate_state()
253 crtc_state->fb_bits = 0; in intel_crtc_duplicate_state()
255 crtc_state->dsb = NULL; in intel_crtc_duplicate_state()
257 return &crtc_state->uapi; in intel_crtc_duplicate_state()
301 kfree(crtc_state); in intel_crtc_destroy_state()
399 &crtc_state->scaler_state; in intel_atomic_setup_scalers()
[all …]
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| H A D | intel_ddi.c | 511 crtc_state)); in intel_ddi_enable_transcoder_func()
3025 crtc_state); in trans_port_sync_stop_link_train()
3180 crtc_state, in intel_enable_ddi()
3279 int required_lanes = crtc_state ? crtc_state->lane_count : 1; in intel_ddi_update_prepare()
3285 if (crtc_state && crtc_state->hw.active) in intel_ddi_update_prepare()
3728 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, in intel_ddi_get_clock()
3788 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, in icl_ddi_tc_get_clock()
3966 crtc_state)) in intel_ddi_port_sync_transcoders()
3984 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); in intel_ddi_compute_config_late()
3999 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { in intel_ddi_compute_config_late()
[all …]
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| H A D | intel_ddi_buf_trans.c | 1082 if (crtc_state->port_clock > 540000) { in icl_get_combo_buf_trans_edp()
1101 const struct intel_crtc_state *crtc_state, in icl_get_combo_buf_trans() argument
1123 const struct intel_crtc_state *crtc_state, in icl_get_mg_buf_trans_dp() argument
1126 if (crtc_state->port_clock > 270000) { in icl_get_mg_buf_trans_dp()
1181 const struct intel_crtc_state *crtc_state, in ehl_get_combo_buf_trans() argument
1218 if (crtc_state->port_clock > 270000) { in jsl_get_combo_buf_trans_edp()
1232 const struct intel_crtc_state *crtc_state, in jsl_get_combo_buf_trans() argument
1259 if (crtc_state->port_clock > 270000) { in tgl_get_combo_buf_trans_dp()
1289 if (crtc_state->port_clock > 540000) { in tgl_get_combo_buf_trans_edp()
1305 const struct intel_crtc_state *crtc_state, in tgl_get_combo_buf_trans() argument
[all …]
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| H A D | intel_dp_link_training.c | 351 const struct intel_crtc_state *crtc_state, in intel_dp_set_link_train() argument
365 len = crtc_state->lane_count + 1; in intel_dp_set_link_train()
404 const struct intel_crtc_state *crtc_state, in intel_dp_set_signal_levels() argument
450 return ret == crtc_state->lane_count; in intel_dp_update_link_train()
493 link_config[1] = crtc_state->lane_count; in intel_dp_prepare_link_train()
716 crtc_state->lane_count)) { in intel_dp_link_training_channel_equalization()
725 crtc_state->lane_count)) { in intel_dp_link_training_channel_equalization()
789 const struct intel_crtc_state *crtc_state, in intel_dp_link_train_phy() argument
810 crtc_state->port_clock, crtc_state->lane_count, in intel_dp_link_train_phy()
826 crtc_state->port_clock, in intel_dp_schedule_fallback_link_training()
[all …]
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| H A D | intel_dpll.c | 1091 if (!crtc_state->clock_set && in ilk_crtc_compute_clock()
1092 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in ilk_crtc_compute_clock()
1154 if (!crtc_state->clock_set && in chv_crtc_compute_clock()
1155 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in chv_crtc_compute_clock()
1176 if (!crtc_state->clock_set && in vlv_crtc_compute_clock()
1177 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in vlv_crtc_compute_clock()
1220 if (!crtc_state->clock_set && in g4x_crtc_compute_clock()
1221 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in g4x_crtc_compute_clock()
1258 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in pnv_crtc_compute_clock()
1295 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in i9xx_crtc_compute_clock()
[all …]
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| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/i915/display/ |
| H A D | intel_color.c | 1337 crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state); in i9xx_color_check()
1391 crtc_state->cgm_mode = chv_cgm_mode(crtc_state); in chv_color_check()
1397 crtc_state->preload_luts = chv_can_preload_luts(crtc_state); in chv_color_check()
1445 crtc_state->gamma_mode = ilk_gamma_mode(crtc_state); in ilk_color_check()
1447 crtc_state->csc_mode = ilk_csc_mode(crtc_state); in ilk_color_check()
1512 crtc_state->gamma_mode = ivb_gamma_mode(crtc_state); in ivb_color_check()
1514 crtc_state->csc_mode = ivb_csc_mode(crtc_state); in ivb_color_check()
1558 crtc_state->hw.ctm || crtc_state->limited_color_range; in glk_color_check()
1560 crtc_state->gamma_mode = glk_gamma_mode(crtc_state); in glk_color_check()
1615 crtc_state->gamma_mode = icl_gamma_mode(crtc_state); in icl_color_check()
[all …]
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| H A D | intel_vrr.c | 76 return crtc_state->vrr.vmin + 1 - intel_vrr_vblank_exit_length(crtc_state); in intel_vrr_vmin_vblank_start()
81 return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state); in intel_vrr_vmax_vblank_start()
100 if (!crtc_state->uapi.vrr_enabled) in intel_vrr_compute_config()
119 crtc_state->vrr.vmin = vmin - 1; in intel_vrr_compute_config()
120 crtc_state->vrr.vmax = vmax; in intel_vrr_compute_config()
121 crtc_state->vrr.enable = true; in intel_vrr_compute_config()
123 crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1; in intel_vrr_compute_config()
135 crtc_state->vrr.pipeline_full = in intel_vrr_compute_config()
148 if (!crtc_state->vrr.enable) in intel_vrr_enable()
169 if (!crtc_state->vrr.enable) in intel_vrr_send_push()
[all …]
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| H A D | intel_vdsc.c | 498 if (crtc_state->bigjoiner) in intel_dsc_pps_configure()
515 if (!is_pipe_dsc(crtc_state)) { in intel_dsc_pps_configure()
522 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
529 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
539 if (!is_pipe_dsc(crtc_state)) { in intel_dsc_pps_configure()
546 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
553 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
564 if (!is_pipe_dsc(crtc_state)) { in intel_dsc_pps_configure()
1048 if (crtc_state->bigjoiner) { in intel_dsc_enable()
1099 crtc_state->bigjoiner = true; in intel_dsc_get_config()
[all …]
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| H A D | intel_atomic.c | 230 crtc_state = kmemdup(old_crtc_state, sizeof(*crtc_state), GFP_KERNEL); in intel_crtc_duplicate_state()
231 if (!crtc_state) in intel_crtc_duplicate_state()
239 if (crtc_state->hw.ctm) in intel_crtc_duplicate_state()
241 if (crtc_state->hw.gamma_lut) in intel_crtc_duplicate_state()
251 crtc_state->inherited = false; in intel_crtc_duplicate_state()
253 crtc_state->fb_bits = 0; in intel_crtc_duplicate_state()
255 crtc_state->dsb = NULL; in intel_crtc_duplicate_state()
257 return &crtc_state->uapi; in intel_crtc_duplicate_state()
301 kfree(crtc_state); in intel_crtc_destroy_state()
399 &crtc_state->scaler_state; in intel_atomic_setup_scalers()
[all …]
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| H A D | intel_ddi.c | 511 crtc_state)); in intel_ddi_enable_transcoder_func()
3025 crtc_state); in trans_port_sync_stop_link_train()
3180 crtc_state, in intel_enable_ddi()
3279 int required_lanes = crtc_state ? crtc_state->lane_count : 1; in intel_ddi_update_prepare()
3285 if (crtc_state && crtc_state->hw.active) in intel_ddi_update_prepare()
3728 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, in intel_ddi_get_clock()
3788 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, in icl_ddi_tc_get_clock()
3966 crtc_state)) in intel_ddi_port_sync_transcoders()
3984 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); in intel_ddi_compute_config_late()
3999 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { in intel_ddi_compute_config_late()
[all …]
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| H A D | intel_ddi_buf_trans.c | 1082 if (crtc_state->port_clock > 540000) { in icl_get_combo_buf_trans_edp()
1101 const struct intel_crtc_state *crtc_state, in icl_get_combo_buf_trans() argument
1123 const struct intel_crtc_state *crtc_state, in icl_get_mg_buf_trans_dp() argument
1126 if (crtc_state->port_clock > 270000) { in icl_get_mg_buf_trans_dp()
1181 const struct intel_crtc_state *crtc_state, in ehl_get_combo_buf_trans() argument
1218 if (crtc_state->port_clock > 270000) { in jsl_get_combo_buf_trans_edp()
1232 const struct intel_crtc_state *crtc_state, in jsl_get_combo_buf_trans() argument
1259 if (crtc_state->port_clock > 270000) { in tgl_get_combo_buf_trans_dp()
1289 if (crtc_state->port_clock > 540000) { in tgl_get_combo_buf_trans_edp()
1305 const struct intel_crtc_state *crtc_state, in tgl_get_combo_buf_trans() argument
[all …]
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| H A D | intel_dp_link_training.c | 351 const struct intel_crtc_state *crtc_state, in intel_dp_set_link_train() argument
365 len = crtc_state->lane_count + 1; in intel_dp_set_link_train()
404 const struct intel_crtc_state *crtc_state, in intel_dp_set_signal_levels() argument
450 return ret == crtc_state->lane_count; in intel_dp_update_link_train()
493 link_config[1] = crtc_state->lane_count; in intel_dp_prepare_link_train()
716 crtc_state->lane_count)) { in intel_dp_link_training_channel_equalization()
725 crtc_state->lane_count)) { in intel_dp_link_training_channel_equalization()
789 const struct intel_crtc_state *crtc_state, in intel_dp_link_train_phy() argument
810 crtc_state->port_clock, crtc_state->lane_count, in intel_dp_link_train_phy()
826 crtc_state->port_clock, in intel_dp_schedule_fallback_link_training()
[all …]
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| H A D | intel_dpll.c | 1091 if (!crtc_state->clock_set && in ilk_crtc_compute_clock()
1092 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in ilk_crtc_compute_clock()
1154 if (!crtc_state->clock_set && in chv_crtc_compute_clock()
1155 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in chv_crtc_compute_clock()
1176 if (!crtc_state->clock_set && in vlv_crtc_compute_clock()
1177 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in vlv_crtc_compute_clock()
1220 if (!crtc_state->clock_set && in g4x_crtc_compute_clock()
1221 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in g4x_crtc_compute_clock()
1258 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in pnv_crtc_compute_clock()
1295 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in i9xx_crtc_compute_clock()
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