1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2020 Intel Corporation
4 *
5 */
6
7 #include "i915_drv.h"
8 #include "intel_display_types.h"
9 #include "intel_vrr.h"
10
intel_vrr_is_capable(struct drm_connector * connector)11 bool intel_vrr_is_capable(struct drm_connector *connector)
12 {
13 struct intel_dp *intel_dp;
14 const struct drm_display_info *info = &connector->display_info;
15 struct drm_i915_private *i915 = to_i915(connector->dev);
16
17 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
18 connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
19 return false;
20
21 intel_dp = intel_attached_dp(to_intel_connector(connector));
22 /*
23 * DP Sink is capable of VRR video timings if
24 * Ignore MSA bit is set in DPCD.
25 * EDID monitor range also should be atleast 10 for reasonable
26 * Adaptive Sync or Variable Refresh Rate end user experience.
27 */
28 return HAS_VRR(i915) &&
29 drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd) &&
30 info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
31 }
32
33 void
intel_vrr_check_modeset(struct intel_atomic_state * state)34 intel_vrr_check_modeset(struct intel_atomic_state *state)
35 {
36 int i;
37 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
38 struct intel_crtc *crtc;
39
40 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
41 new_crtc_state, i) {
42 if (new_crtc_state->uapi.vrr_enabled !=
43 old_crtc_state->uapi.vrr_enabled)
44 new_crtc_state->uapi.mode_changed = true;
45 }
46 }
47
48 /*
49 * Without VRR registers get latched at:
50 * vblank_start
51 *
52 * With VRR the earliest registers can get latched is:
53 * intel_vrr_vmin_vblank_start(), which if we want to maintain
54 * the correct min vtotal is >=vblank_start+1
55 *
56 * The latest point registers can get latched is the vmax decision boundary:
57 * intel_vrr_vmax_vblank_start()
58 *
59 * Between those two points the vblank exit starts (and hence registers get
60 * latched) ASAP after a push is sent.
61 *
62 * framestart_delay is programmable 0-3.
63 */
intel_vrr_vblank_exit_length(const struct intel_crtc_state * crtc_state)64 static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_state)
65 {
66 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
67 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
68
69 /* The hw imposes the extra scanline before frame start */
70 return crtc_state->vrr.pipeline_full + i915->framestart_delay + 1;
71 }
72
intel_vrr_vmin_vblank_start(const struct intel_crtc_state * crtc_state)73 int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
74 {
75 /* Min vblank actually determined by flipline that is always >=vmin+1 */
76 return crtc_state->vrr.vmin + 1 - intel_vrr_vblank_exit_length(crtc_state);
77 }
78
intel_vrr_vmax_vblank_start(const struct intel_crtc_state * crtc_state)79 int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
80 {
81 return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state);
82 }
83
84 void
intel_vrr_compute_config(struct intel_crtc_state * crtc_state,struct drm_connector_state * conn_state)85 intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
86 struct drm_connector_state *conn_state)
87 {
88 struct intel_connector *connector =
89 to_intel_connector(conn_state->connector);
90 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
91 const struct drm_display_info *info = &connector->base.display_info;
92 int vmin, vmax;
93
94 if (!intel_vrr_is_capable(&connector->base))
95 return;
96
97 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
98 return;
99
100 if (!crtc_state->uapi.vrr_enabled)
101 return;
102
103 vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000,
104 adjusted_mode->crtc_htotal * info->monitor_range.max_vfreq);
105 vmax = adjusted_mode->crtc_clock * 1000 /
106 (adjusted_mode->crtc_htotal * info->monitor_range.min_vfreq);
107
108 vmin = max_t(int, vmin, adjusted_mode->crtc_vtotal);
109 vmax = max_t(int, vmax, adjusted_mode->crtc_vtotal);
110
111 if (vmin >= vmax)
112 return;
113
114 /*
115 * flipline determines the min vblank length the hardware will
116 * generate, and flipline>=vmin+1, hence we reduce vmin by one
117 * to make sure we can get the actual min vblank length.
118 */
119 crtc_state->vrr.vmin = vmin - 1;
120 crtc_state->vrr.vmax = vmax;
121 crtc_state->vrr.enable = true;
122
123 crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1;
124
125 /*
126 * FIXME: s/4/framestart_delay+1/ to get consistent
127 * earliest/latest points for register latching regardless
128 * of the framestart_delay used?
129 *
130 * FIXME: this really needs the extra scanline to provide consistent
131 * behaviour for all framestart_delay values. Otherwise with
132 * framestart_delay==3 we will end up extending the min vblank by
133 * one extra line.
134 */
135 crtc_state->vrr.pipeline_full =
136 min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay - 4 - 1);
137
138 crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
139 }
140
intel_vrr_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)141 void intel_vrr_enable(struct intel_encoder *encoder,
142 const struct intel_crtc_state *crtc_state)
143 {
144 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
145 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
146 u32 trans_vrr_ctl;
147
148 if (!crtc_state->vrr.enable)
149 return;
150
151 trans_vrr_ctl = VRR_CTL_VRR_ENABLE |
152 VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
153 VRR_CTL_PIPELINE_FULL(crtc_state->vrr.pipeline_full) |
154 VRR_CTL_PIPELINE_FULL_OVERRIDE;
155
156 intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1);
157 intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1);
158 intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl);
159 intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1);
160 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN);
161 }
162
intel_vrr_send_push(const struct intel_crtc_state * crtc_state)163 void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
164 {
165 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
166 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
167 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
168
169 if (!crtc_state->vrr.enable)
170 return;
171
172 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder),
173 TRANS_PUSH_EN | TRANS_PUSH_SEND);
174 }
175
intel_vrr_disable(const struct intel_crtc_state * old_crtc_state)176 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
177 {
178 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
179 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
180 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
181
182 if (!old_crtc_state->vrr.enable)
183 return;
184
185 intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), 0);
186 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), 0);
187 }
188
intel_vrr_get_config(struct intel_crtc * crtc,struct intel_crtc_state * crtc_state)189 void intel_vrr_get_config(struct intel_crtc *crtc,
190 struct intel_crtc_state *crtc_state)
191 {
192 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
193 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
194 u32 trans_vrr_ctl;
195
196 trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder));
197 crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
198 if (!crtc_state->vrr.enable)
199 return;
200
201 if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE)
202 crtc_state->vrr.pipeline_full = REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);
203 if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN)
204 crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1;
205 crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(cpu_transcoder)) + 1;
206 crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1;
207
208 crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
209 }
210