Searched refs:data_b_b (Results 1 – 1 of 1) sorted by relevance
| /dports/cad/verilator/verilator-4.216/test_regress/t/ |
| H A D | t_clk_latch.v | 29 reg [7:0] data_b_b; register
32 wire [8*6-1:0] compare = {data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b};
79 data_b_b <= data_b + 8'd1;
88 $write("%d %x %x %x %x %x %x\n",cyc,data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b);
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