1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2005 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/
8   // Inputs
9   fastclk, clk
10   );
11
12`ifdef EDGE_DETECT_STYLE	// Two 'common' forms of latching, with full combo, and with pos/negedge
13 `define posstyle posedge
14 `define negstyle negedge
15`else
16 `define posstyle
17 `define negstyle
18`endif
19
20   input fastclk;
21   input clk;
22
23   reg [7:0] data;
24   reg [7:0] data_a;
25   reg [7:0] data_a_a;
26   reg [7:0] data_a_b;
27   reg [7:0] data_b;
28   reg [7:0] data_b_a;
29   reg [7:0] data_b_b;
30
31   reg [8*6-1:0] check [100:0];
32   wire [8*6-1:0] compare = {data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b};
33   initial begin
34      check[7'd19] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
35      check[7'd20] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
36      check[7'd21] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
37      check[7'd22] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
38      check[7'd23] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
39      check[7'd24] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
40      check[7'd25] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
41      check[7'd26] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e};
42      check[7'd27] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e};
43      check[7'd28] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
44      check[7'd29] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
45      check[7'd30] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
46      check[7'd31] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16};
47      check[7'd32] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16};
48      check[7'd33] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
49      check[7'd34] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
50      check[7'd35] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
51      check[7'd36] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16};
52      check[7'd37] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16};
53   end
54
55   // verilator lint_off COMBDLY
56   // verilator lint_off LATCH
57   always @ (`posstyle clk /*AS*/ or data) begin
58      if (clk) begin
59	 data_a <= data + 8'd1;
60      end
61   end
62
63   always @ (`posstyle clk /*AS*/ or data_a) begin
64      if (clk) begin
65	 data_a_a <= data_a + 8'd1;
66      end
67   end
68
69   always @ (`posstyle clk /*AS*/ or data_b) begin
70      if (clk) begin
71	 data_b_a <= data_b + 8'd1;
72      end
73   end
74
75   always @ (`negstyle clk /*AS*/ or data or data_a) begin
76      if (~clk) begin
77	 data_b <= data + 8'd1;
78	 data_a_b <= data_a + 8'd1;
79	 data_b_b <= data_b + 8'd1;
80      end
81   end
82
83   integer cyc; initial cyc = 0;
84
85   always @ (posedge fastclk) begin
86      cyc <= cyc+1;
87`ifdef TEST_VERBOSE
88      $write("%d  %x %x %x  %x %x %x\n",cyc,data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b);
89`endif
90      if (cyc>=19 && cyc<36) begin
91	 if (compare !== check[cyc]) begin
92	    $write("[%0t] Mismatch, got=%x, exp=%x\n", $time, compare, check[cyc]);
93	    $stop;
94	 end
95      end
96      if (cyc == 10) begin
97	 data <= 8'd12;
98      end
99      if (cyc == 20) begin
100	 data <= 8'd20;
101      end
102      if (cyc == 30) begin
103	 data <= 8'd30;
104      end
105      if (cyc == 40) begin
106	 $write("*-* All Finished *-*\n");
107	 $finish;
108      end
109   end
110
111endmodule
112