| /dports/cad/yosys/yosys-yosys-0.12/tests/asicworld/ |
| H A D | code_hdl_models_mux_using_if.v | 9 din_1 , // Mux Second input
14 input din_0, din_1, sel ; port
20 always @ (sel or din_0 or din_1)
25 mux_out = din_1 ;
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| H A D | code_hdl_models_mux_using_case.v | 9 din_1 , // Mux Second input
14 input din_0, din_1, sel ; port
20 always @ (sel or din_0 or din_1)
24 1'b1 : mux_out = din_1;
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| H A D | code_hdl_models_mux_using_assign.v | 9 din_1 , // Mux Second input
14 input din_0, din_1, sel ; port
20 assign mux_out = (sel) ? din_1 : din_0;
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| /dports/devel/icestorm/icestorm-710470f9/icefuzz/tests/ |
| H A D | sb_io_od.v | 33 output din_1 port
45 wire din_1; net
60 .DIN1(din_1)
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| H A D | sb_io.v | 33 output din_1 port
45 wire din_1; net
62 .D_IN_1(din_1)
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| H A D | sb_gb_io.v | 11 output [7:0] din_1, port
29 .D_IN_1(din_1),
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| H A D | test_pio_tb.v | 32 .din_1 (gold_din_1 )
46 .din_1 (gate_din_1 )
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| H A D | sb_io_od.pcf | 12 # set_io din_1
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| H A D | sb_io.pcf | 12 # set_io din_1
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| H A D | test_pio.sh | 27 output din_1,
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| /dports/devel/doxygen/doxygen-1.9.3/examples/ |
| H A D | mux.vhdl | 18 din_1 : in std_logic; --! Mux Second input port
30 din_1 when others;
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| /dports/devel/py-breathe/breathe-4.31.0/examples/doxygen/ |
| H A D | mux.vhdl | 18 din_1 : in std_logic; --! Mux Second input port
30 din_1 when others;
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| /dports/devel/icestorm/icestorm-710470f9/icefuzz/ |
| H A D | make_gbio.py | 30 din_1 = np.random.choice(["din_1", "{din_1[1:0], din_1[%d:2]}" % (w - 1,)]) variable
82 din_1,
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b2xxmini/coregen_dsp/ |
| H A D | hbdec1.veo | 68 .din_1(din_1), // input [23 : 0] din_1
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| H A D | hbdec2.veo | 68 .din_1(din_1), // input [23 : 0] din_1
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| H A D | hbdec1.asy | 11 PINATTR PinName din_1[23:0]
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| H A D | hbdec2.asy | 11 PINATTR PinName din_1[23:0]
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen_dsp/ |
| H A D | hbdec2.veo | 68 .din_1(din_1), // input [23 : 0] din_1
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| H A D | hbdec1.veo | 68 .din_1(din_1), // input [23 : 0] din_1
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/coregen_dsp/ |
| H A D | hbdec2.veo | 68 .din_1(din_1), // input [23 : 0] din_1
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| H A D | hbdec1.veo | 68 .din_1(din_1), // input [23 : 0] din_1
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| H A D | hbdec3.veo | 68 .din_1(din_1), // input [23 : 0] din_1
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| H A D | hbdec1.asy | 11 PINATTR PinName din_1[23:0]
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| H A D | hbdec2.asy | 11 PINATTR PinName din_1[23:0]
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| H A D | hbdec3.asy | 11 PINATTR PinName din_1[23:0]
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