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Searched refs:fp_gpio_master_reg (Results 1 – 3 of 3) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e31x/
H A De31x_core.v180 reg [31:0] fp_gpio_master_reg = 32'h0; register
364 fp_gpio_master_reg <= cp_glob_req_data;
406 cp_glob_resp_data <= fp_gpio_master_reg;
615 .I2(fp_gpio_master_reg[i]) // LUT input. Select bit
626 .I2(fp_gpio_master_reg[i]) // LUT input. Select bit
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/
H A De320_core.v245 reg [31:0] fp_gpio_master_reg = 32'h0; register
432 fp_gpio_master_reg <= cp_glob_req_data;
480 cp_glob_resp_data <= fp_gpio_master_reg;
971 .I2(fp_gpio_master_reg[i]) // LUT input. Select bit
982 .I2(fp_gpio_master_reg[i]) // LUT input. Select bit
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/
H A Dn3xx_core.v275 reg [31:0] fp_gpio_master_reg = 32'h0; register
474 fp_gpio_master_reg <= 32'h0;
498 fp_gpio_master_reg <= cp_glob_req_data;
553 cp_glob_resp_data <= fp_gpio_master_reg;
1059 .I2(fp_gpio_master_reg[i])// LUT input. Select bit
1068 .I2(fp_gpio_master_reg[i]) // LUT input. Select bit